Preparation method for improving electrical property of through silicon via

Abstract

The invention provides a preparation method for improving the electrical property of a silicon through hole. The preparation method comprises the following steps of: 1, forming a silicon dioxide layer on a wafer; 2, arranging photoresist on the silicon dioxide layer and forming a photoresist pattern; 3, forming a pattern of a silicon dioxide layer by using the photoresist pattern; 4, removing the photoresist pattern; a fifth step of executing a silicon through hole etching process by using the pattern of the silicon dioxide layer so as to form a silicon through hole in the wafer; 6, growing a layer of silicon oxide film on the side wall of the silicon through hole by using an ISSG in-situ water vapor oxidation process; and 7, removing the silicon oxide thin film. According to the method, the side wall of the through hole can become flat and smooth, after the silicon through hole structure is completed, high-temperature annealing is carried out on the device to repair lattice damage caused by etching process ion bombardment, meanwhile, hardening is carried out on the lining oxide layer, and the purpose of improving the yield and the reliability is achieved.

Description

Technical Field

[0001] The invention relates to a preparation method for improving the electrical properties of a through silicon via, belonging to the technical field of semiconductor packaging mid-sections. Background Art

[0002] In the existing through silicon via manufacturing process, a hard mask is deposited on the surface of the silicon substrate; then the silicon substrate is deep reactive ion etched to form a through hole; and an oxide layer is deposited on the side wall of the through hole by atomic layer deposition (ALD). However, the through silicon via (TSV) etching uses the Bosch process, which first uses an etching gas SF 6 Etching a groove of a certain depth (such as Figure 1 As shown), and then through the gas C 4 F 8 Deposition protection sidewalls (such as Figure 2 As shown), and then use etching gas SF 6 Etching (such as Figure 3 This will result in scallop-shaped protrusion defects on the side wall (such as Figure 4 The defects of scallop-shaped protrusions and bottom streaks affect the yield and reliability of TSV devices. Especially at the scallop-shaped protrusions and bottom streaks, the deposited oxide layer has sharp corners and is weak and easily punctured, so the TSV devices with this morphology have a short service life. How to obtain a flat and smooth through-hole sidewall is a bottleneck in the TSV process.

[0003] Another problem with the TSV process is that the film formation temperature of the liner oxide layer deposited by ALD is relatively low, generally around 300 degrees, which affects the electrical parameters of the TSV device. Summary of the invention

[0004] The technical problem to be solved by the present invention is to provide a preparation method for improving the electrical properties of silicon vias in view of the above-mentioned defects in the prior art, which can make the side walls of the vias flat and smooth, and after the silicon via structure is completed, the device is subjected to high-temperature annealing to repair the lattice damage caused by ion bombardment in the etching process, and at the same time, the lining oxide layer is hardened, so as to achieve the purpose of improving yield and reliability.

[0005] According to the present invention, a preparation method for improving electrical properties of through silicon vias is provided, comprising:

[0006] Step 1: forming a silicon dioxide layer on the wafer;

[0007] The second step: arranging a photoresist on the silicon dioxide layer and forming a photoresist pattern;

[0008] The third step: forming a pattern of the silicon dioxide layer using a photoresist pattern;

[0009] Step 4: removing the photoresist pattern;

[0010] Step 5: performing a through silicon via etching process using the pattern of the silicon dioxide layer to form a through silicon via in the wafer;

[0011] Step 6: Using ISSG in-situ water vapor oxidation process to grow a layer of silicon oxide film on the side wall of the through silicon via;

[0012] Step 7: Remove the silicon oxide film.

[0013] Preferably, the sixth step and the seventh step are performed multiple times.

[0014] Preferably, the process and preparation method for improving the electrical properties of through silicon vias further include:

[0015] Step 8: Using ISSG in-situ water vapor oxidation process to grow a layer of silicon oxide film on the side wall of the through silicon via again;

[0016] Step 9: Based on the silicon oxide film, an oxide layer is deposited on the sidewall of the through hole and the sidewall of the pattern of the silicon dioxide layer by atomic layer deposition to form a liner oxide layer.

[0017] Preferably, the process and preparation method for improving electrical properties of through silicon vias further includes a tenth step: performing a high temperature annealing process.

[0018] Preferably, in the through silicon via etching process, the etching gas SF 6 Etching to obtain the initial groove, then performing a single or multiple pass through the gas C 4 F 8 Deposit protective sidewalls and use the protective sidewalls to etch with SF 6 Etching cycle steps.

[0019] Preferably, a DHF cleaning process is used to remove the silicon oxide film.

[0020] The present invention can make the through hole sidewall flat and smooth, and after the through silicon via structure is completed, the device is subjected to high temperature annealing to repair the lattice damage caused by ion bombardment in the etching process, and the liner oxide layer is hardened, so as to achieve the purpose of improving yield and reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] A more complete understanding of the present invention and its attendant advantages and features will be more readily appreciated by reference to the following detailed description taken in conjunction with the accompanying drawings, in which:

[0022] Figures 1 to 4 The through silicon via process of the prior art is schematically shown;

[0023] Figure 5 A flowchart schematically shows a process for improving electrical properties of through silicon vias and a method for preparing the same according to a preferred embodiment of the present invention;

[0024] Figures 6 to 14 A schematic diagram schematically shows various steps of a process and a method for preparing a through silicon via for improving electrical properties according to a preferred embodiment of the present invention;

[0025] in, Fig.12 for Fig.11 A magnified schematic diagram of through-hole details;

[0026] It should be noted that the drawings are used to illustrate the present invention, rather than to limit the present invention. Note that the drawings showing structures may not be drawn to scale; and in the drawings, the same or similar elements are marked with the same or similar reference numerals. DETAILED DESCRIPTION

[0027] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0028] For ease of description, spatial relational terms such as "under", "below", "below", "below", "above", "on", etc. may be used herein to describe the relationship between an element or feature shown in the drawings and other elements or features. It will be understood that these spatial relational terms are intended to include other directions of the device in use or operation in addition to the directions depicted in the drawings. In addition, when a layer is referred to as being "between" two layers, it may be the only layer between the two layers, or there may be one or more intervening layers. Among them, when an element is referred to as being "fixed to" or "disposed on" another element, it may be directly on the other element or indirectly on the other element. When an element is referred to as being "connected to" another element, it may be directly connected to the other element or indirectly connected to the other element.

[0029] Here, expressions such as "between..." may be used, which indicates that the two end points are included, and expressions such as "plurality" may be used, which indicates two or more, unless otherwise clearly and specifically limited. In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features.

[0030] Figure 5 The flowchart of the process and preparation method for improving the electrical properties of through silicon vias according to a preferred embodiment of the present invention is schematically shown. Figures 6 to 12 The schematic diagram schematically shows various steps of a process and a method for preparing a through silicon via according to a preferred embodiment of the present invention.

[0031] like Figures 5 to 12 As shown, the process and preparation method for improving the electrical properties of through silicon vias according to a preferred embodiment of the present invention include:

[0032] The first step S1: forming a silicon dioxide layer 20 on the wafer 10, such as Figure 6 As shown;

[0033] The second step S2: arranging photoresist on the silicon dioxide layer 20 and forming a photoresist pattern 30, such as Figure 7 As shown;

[0034] The third step S3: using the photoresist pattern 30 to form a pattern of the silicon dioxide layer 20, such as Figure 8 As shown;

[0035] Step 4 S4: removing the photoresist pattern 30, such as Fig. 9 As shown;

[0036] The fifth step S5: performing a through silicon via etching process using the pattern of the silicon dioxide layer 20 to form a through silicon via 40 in the wafer 10, such as Fig.10 As shown;

[0037] Specifically, refer to Figures 1 to 4 In the through silicon via etching process, the etching gas SF 6 Etching to obtain the initial groove, then performing a single or multiple pass through the gas C 4 F 8 Deposit protective sidewalls and use the protective sidewalls to etch with SF 6 Etching cycle steps.

[0038] Step 6 S6: Using ISSG (In-Situ Steam Generation) in-situ steam oxidation process to grow a layer of silicon oxide film 50 on the side wall of the through silicon via 40, such as Fig.11 As shown;

[0039] ISSG has good temperature uniformity, usually at 0 2 A small amount of H 2 As a "catalyst", a chemical reaction similar to combustion occurs on the wafer surface at high temperature. This reaction generates a large number of gas-phase active free radicals, mainly oxygen free radicals, which participate in the oxidation process of Si. ISSG grows SIO 2 Need to consume silicon, 1 unit of SIO 2It needs to consume 0.46 units of silicon, so the surface area of ​​the scallop-shaped protrusions on the sidewall is larger and easier to react with oxygen atoms. The silicon consumption at the protrusions is faster. The scallop-shaped protrusion defects and the stripe-shaped defects at the bottom of the hole will be oxidized to part of the hot oxygen, such as Fig.12 As shown, Fig.12 The schematic diagram shows the smooth changes in the direction of the scallop-shaped protrusion defects and the stripe-shaped defects at the bottom of the hole after the ISSG thermal oxidation process.

[0040] Step S7: removing the silicon oxide film 50, such as Fig.13 As shown; with the removal of the silicon oxide film 50, the stripe-shaped defects and the scallop-shaped protrusion defects on the sidewalls are also eliminated.

[0041] Preferably, a DHF (dilute hydrofluoric acid solution) cleaning process is used to remove the silicon oxide film 50 .

[0042] Preferably, before executing the subsequent steps, the sixth step S6 of ISSG thermal oxidation to generate the silicon oxide film 50 and the seventh step of removing the silicon oxide film 50 are performed multiple times to eliminate the scallop-shaped protrusion defects and the stripe-shaped defects at the bottom of the hole more thoroughly.

[0043] Step 8: Using the ISSG in-situ water vapor oxidation process, a layer of silicon oxide film 50 is grown on the side wall of the through silicon via 40 again. The obtained structure is referenced to Fig.11 ;

[0044] Ninth step S9: On the basis of the silicon oxide film, an oxide layer is deposited on the sidewall of the through silicon via 40 and the pattern sidewall of the silicon dioxide layer 20 by atomic layer deposition to form a liner oxide layer 60, such as Fig.14 As shown. Fig.14 The figure shows the formation of the liner oxide layer 60. The growth of a layer of silicon oxide film on the sidewall of the through silicon via in the eighth step is not shown. As an example, the liner oxide layer 60 is silicon dioxide. In other examples, the liner oxide layer 60 is silicon oxynitride. The liner oxide layer 60 is formed on the sidewall of the through silicon via 40 and the pattern sidewall of the silicon dioxide layer 20, which can prevent the copper metal material subsequently filled in the through silicon via 40 from laterally diffusing into the interior of the wafer 10 and affecting the electrical properties.

[0045] The tenth step S10: performing a high temperature annealing process.

[0046] In the present invention, since the temperature uniformity of the ISSG process is better, the thermal oxide film generated by the traditional furnace tube has fewer defects and a smoother interface. In addition, the present invention changes the formation of the liner oxide layer by ALD alone to the formation of the liner oxide layer by ISSG thermal oxidation plus ALD. The electrical properties and adhesion of ISSG thermal oxidation will be better, and there will be fewer defects; ALD has better conformality, and the advantages of the two processes are combined to improve the device yield, reliability, and service life.

[0047] In addition, after the TSV structure is completed, the device is subjected to high-temperature annealing to repair the lattice damage caused by ion bombardment during the etching process, and the liner oxide layer is hardened to achieve the purpose of improving yield and reliability.

[0048] It should be noted that, unless otherwise specified, the terms "first", "second", "third", etc. in the specification are only used to distinguish the various components, elements, steps, etc. in the specification, and are not used to indicate the logical relationship or sequential relationship between the various components, elements, steps, etc.

[0049] It is to be understood that, although the present invention has been disclosed as a preferred embodiment, the above embodiment is not intended to limit the present invention. For any technician familiar with the art, without departing from the scope of the technical solution of the present invention, the technical content disclosed above can be used to make many possible changes and modifications to the technical solution of the present invention, or modified into equivalent embodiments of equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention without departing from the content of the technical solution of the present invention still falls within the scope of protection of the technical solution of the present invention.

Claims

1. A method for improving the electrical properties of through silicon vias, characterized in that include: Step 1: forming a silicon dioxide layer on the wafer; The second step: arranging a photoresist on the silicon dioxide layer and forming a photoresist pattern; The third step: forming a pattern of the silicon dioxide layer using a photoresist pattern; Step 4: removing the photoresist pattern; Step 5: performing a through silicon via etching process using the pattern of the silicon dioxide layer to form a through silicon via in the wafer; Step 6: Using ISSG in-situ water vapor oxidation process to grow a layer of silicon oxide film on the side wall of the through silicon via; Step 7: Remove the silicon oxide film.

2. The process and method for preparing a through silicon via for improving electrical properties according to claim 1, characterized in that: The sixth and seventh steps are performed multiple times.

3. The process and method for preparing a through silicon via according to claim 1 or 2, characterized in that Also includes: Step 8: Using ISSG in-situ water vapor oxidation process to grow a layer of silicon oxide film on the side wall of the through silicon via again; Step 9: Based on the silicon oxide film, an oxide layer is deposited on the sidewall of the through hole and the sidewall of the pattern of the silicon dioxide layer by atomic layer deposition to form a liner oxide layer.

4. The process and method for preparing a through silicon via according to claim 1 or 2, characterized in that The method further comprises a tenth step: performing a high temperature annealing process.

5. The process and method for preparing a through silicon via for improving electrical properties according to claim 1 or 2, characterized in that: In the through silicon via etching process, an initial groove is first etched with etching gas SF6, and then a cycle step of depositing a protective sidewall with gas C4F8 and etching with etching gas SF6 using the protective sidewall is performed once or multiple times.

6. The process and method for preparing a through silicon via for improving electrical properties according to claim 1 or 2, characterized in that: The silicon oxide film is removed by DHF cleaning process.

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