Semiconductor structure, forming method and related device

Abstract

The embodiment of the invention provides a semiconductor structure, a forming method and a related device, and the method comprises the steps: providing a first substrate and a second substrate, and forming a barrier layer on the first substrate and / or the second substrate; a first substrate and a second substrate are bonded to form a laminated substrate, and the barrier layer is located between the first substrate and the second substrate; forming a plurality of mutually spaced through holes in the laminated substrate, the through holes at least penetrating through one of the first substrate and the second substrate and the barrier layer, and taking one side of the laminated substrate, where the through holes are formed, as the front surface of the laminated substrate, taking one side far away from the laminated substrate to form the through hole as the back surface of the laminated substrate; forming a conductive structure in the through hole; and grinding the back surface of the laminated substrate by taking the barrier layer as a grinding stop layer, and taking the residual structure as a target semiconductor structure. The embodiment of the invention can improve the performance of the device.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of semiconductor technology, and specifically to a semiconductor structure, a formation method, and related devices. Background Art

[0002] As Moore's Law gradually slows down and chip feature sizes are approaching physical limits, Through-Silicon Via (TSV) technology, as a key technology to break through the boundaries of traditional packaging and achieve higher integration and performance, is becoming increasingly important. Based on this TSV technology, high-density electrical connections between different chip layers can be achieved, and this feature makes this technology have broad application prospects in the fields of 2.5D and 3D advanced packaging.

[0003] However, devices formed by existing semiconductor processes have poor performance. Summary of the invention

[0004] In view of this, embodiments of the present application provide a semiconductor structure, a formation method, and related devices to improve device performance.

[0005] To achieve the above objectives, the embodiments of the present application provide the following technical solutions.

[0006] In a first aspect, an embodiment of the present application provides a method for forming a semiconductor structure, comprising:

[0007] Providing a first substrate and a second substrate, wherein a barrier layer is formed on the first substrate and / or the second substrate;

[0008] Bonding the first substrate and the second substrate to form a stacked substrate, wherein the barrier layer is located between the first substrate and the second substrate;

[0009] A plurality of mutually spaced through holes are formed on the laminate substrate, wherein the through holes penetrate at least one of the first substrate and the second substrate and the barrier layer, and the side of the laminate substrate where the through holes are formed is the front side of the laminate substrate, and the side away from the laminate substrate where the through holes are formed is the back side of the laminate substrate;

[0010] forming a conductive structure in the through hole;

[0011] The barrier layer is used as a grinding stop layer to grind the back side of the stacked substrate, and the remaining structure is used as a target semiconductor structure.

[0012] Optionally, when a barrier layer is formed on the first substrate or the second substrate, the step of bonding the first substrate and the second substrate to form a stacked substrate is specifically:

[0013] Bonding the first substrate formed with the barrier layer to the second substrate to form a stacked substrate; or,

[0014] A second substrate having a barrier layer formed thereon is bonded to the first substrate to form a stacked substrate.

[0015] Optionally, when a barrier layer is formed on the first substrate and the second substrate, the step of using the barrier layer as a grinding stop layer, grinding the back side of the stacked substrate, and using the remaining structure as the target semiconductor structure is specifically:

[0016] The barrier layer close to the front surface of the stacked substrate is used as a grinding stop layer, the back surface of the stacked substrate is ground, and the remaining structure is used as a target semiconductor structure.

[0017] Optionally, the step of bonding the first substrate and the second substrate to form a stacked substrate includes:

[0018] forming a first oxide layer on the first substrate;

[0019] forming a second oxide layer on the second substrate;

[0020] Based on the first oxide layer and the second oxide layer, the first substrate and the second substrate are bonded to form a stacked substrate.

[0021] Optionally, after the step of bonding the first substrate and the second substrate to form a laminated substrate and before the step of forming a plurality of mutually spaced through holes on the laminated substrate, the method further includes:

[0022] The laminated substrate is thinned.

[0023] Optionally, the step of forming a plurality of mutually spaced through holes on the laminate substrate includes:

[0024] forming a dielectric layer on the laminate substrate;

[0025] forming a patterned photolithography layer on the dielectric layer;

[0026] The dielectric layer exposed by the photoresist layer and at least a portion of the thickness of the laminated substrate are removed to form the through hole.

[0027] Optionally, the step of removing the dielectric layer exposed by the photolithography layer and at least a portion of the thickness of the laminated substrate to form the through hole comprises:

[0028] The dielectric layer and at least a portion of the thickness of the laminated substrate exposed by the photolithography layer are removed to form a through hole penetrating the dielectric layer and at least a portion of the thickness of the laminated substrate.

[0029] Optionally, an etching process is used to remove the dielectric layer exposed by the photolithography layer and at least a portion of the thickness of the laminated substrate to form the through hole.

[0030] Optionally, the etching process is a dry etching process or a wet etching process, or a combination of both.

[0031] Optionally, after the step of forming a plurality of mutually spaced through holes on the laminated substrate and before the step of forming a conductive structure in the through hole, the method further includes:

[0032] forming an insulating layer covering the dielectric layer, and the sidewalls and bottom of the through hole;

[0033] An isolation layer is formed on the insulating layer.

[0034] Optionally, after the step of forming a plurality of mutually spaced through holes on the laminated substrate and before the step of forming an insulating layer covering the dielectric layer and the sidewalls and bottom of the through holes, the method further includes:

[0035] The photoresist layer on the dielectric layer is removed.

[0036] Optionally, the step of forming a conductive structure in the through hole includes:

[0037] forming a conductive structural material layer on the isolation layer, wherein the conductive structural material layer completely fills the through hole;

[0038] The dielectric layer is used as a stop layer to grind the front surface of the laminated substrate, and the remaining conductive structure material layer is used as a conductive structure.

[0039] Optionally, the material of the barrier layer is silicon nitride or silicon carbonitride.

[0040] In a second aspect, an embodiment of the present application provides a semiconductor structure, which is formed based on the method for forming a semiconductor structure as described in the first aspect above.

[0041] In a third aspect, an embodiment of the present application provides a packaging structure, which includes the semiconductor structure as described in the second aspect above.

[0042] In a fourth aspect, an embodiment of the present application provides a chip, wherein the chip includes the semiconductor structure as described in the second aspect above, or the chip includes the packaging structure as described in the third aspect above.

[0043] In a fifth aspect, an embodiment of the present application provides an integrated circuit structure, which includes the semiconductor structure as described in the second aspect above, or the integrated circuit structure includes the packaging structure as described in the third aspect above.

[0044] Compared with the prior art, the technical solution of the embodiment of the present application has the following advantages:

[0045] The embodiments of the present application provide a semiconductor structure, a formation method and related devices, wherein the semiconductor structure formation method includes: providing a first substrate and a second substrate, wherein a barrier layer is formed on the first substrate and / or the second substrate; bonding the first substrate and the second substrate to form a stacked substrate, wherein the barrier layer is located between the first substrate and the second substrate; forming a plurality of mutually spaced through holes on the stacked substrate, wherein the through holes at least penetrate one of the first substrate and the second substrate and the barrier layer, wherein the side of the stacked substrate where the through holes are formed is the front side of the stacked substrate, and the side away from the stacked substrate where the through holes are formed is the back side of the stacked substrate; forming a conductive structure in the through hole; using the barrier layer as a grinding stop layer, grinding the back side of the stacked substrate, and using the remaining structure as the target semiconductor structure.

[0046] It can be seen that the method for forming a semiconductor structure provided in an embodiment of the present application forms a through hole that penetrates at least one substrate and a barrier layer in the first substrate and the second substrate, and a conductive structure located in the through hole. When grinding the back side of the stacked substrate, the barrier layer is used as a grinding stop layer to mark the grinding stop position of the back side of the stacked substrate, thereby avoiding grinding of the substrate on the front side of the stacked substrate during the grinding process, thereby avoiding the conductive material in the conductive structure in the through hole from diffusing into the substrate on the front side of the stacked substrate, thereby avoiding device leakage and improving device performance.

[0047] At the same time, based on the stacked substrate, a through hole is formed that penetrates at least one substrate and a barrier layer in the first substrate and the second substrate, as well as a conductive structure located in the through hole, and the barrier layer between the first substrate and the second substrate in the stacked substrate is further used as a grinding stop layer, which can ensure the grinding flatness of the back side of the stacked substrate, thereby avoiding the problem of incomplete or excessive exposure of the conductive structure, thereby improving the performance of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0049] Figure 1 It is a schematic diagram of the structure corresponding to each step in the BFR process;

[0050] Figure 2It is a schematic diagram of the structure corresponding to each step in the BVR process;

[0051] Figures 3 to 17 It is a structural schematic diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure according to an embodiment of the present application. DETAILED DESCRIPTION

[0052] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0053] A through-silicon via (TSV) fabrication and backside exposure process is as follows: first, a conductive structure is pre-buried in the through hole of a substrate; then, the side of the substrate where the conductive structure is formed is temporarily bonded to a glass carrier, and the side of the substrate away from the conductive structure is processed to expose the conductive structure for subsequent processes. There are usually two types of exposure processes, namely BFR (Backside via Flatness Reveal) and BVR (Backside Via Reveal).

[0054] Specifically, refer to Figure 1 The schematic diagram of the structure corresponding to each step in the BFR process shown is as follows: first, a conductive structure 11 is formed on the surface of the substrate 10 to achieve high-density electrical connection between different chip layers; then, the side of the substrate 10 where the conductive structure 11 is formed is temporarily bonded to the glass carrier 20, and the side of the substrate 10 away from the conductive structure 11 is thinned until the conductive structure 11 is exposed, and then the thinned substrate is etched to expose the conductive structure 11; then, a dielectric layer 12 is formed on the side of the substrate 10 where the conductive structure 11 is exposed, and finally, the exposed conductive structure 11 is ground off. However, in the process of thinning the substrate 10 to expose the conductive structure 11, the conductive material in the conductive structure will diffuse into the substrate, thereby increasing the leakage current of the device, thereby affecting the performance of the device.

[0055] Further, in order to prevent the conductive material in the conductive structure from diffusing into the substrate, refer to Figure 2The schematic diagram of the structure corresponding to each step in the BVR process shown is as follows: First, a conductive structure 11 is formed on the surface of the substrate 10 to achieve high-density electrical connection between different chip layers; then, the side of the substrate 10 where the conductive structure 11 is formed is temporarily bonded to the glass carrier 20, and the side of the substrate 10 away from the conductive structure 11 is thinned, and the thinned substrate 10 does not expose the conductive structure 11. Then, the thinned substrate 10 is etched to expose the conductive structure 11; then, a dielectric layer 12 is formed on the side of the substrate 10 where the conductive structure 11 is exposed, and finally, the exposed conductive structure 11 is ground away. However, although this method avoids the diffusion of the conductive material in the conductive structure into the substrate, when the total thickness variation (Total Thickness Variation, TTV) of the substrate is large (i.e., the substrate thickness is uneven), etching the thinned substrate that does not expose the conductive structure may easily lead to incomplete exposure of the conductive structure or excessive exposure of the conductive structure.

[0056] Among them, incomplete exposure of the conductive structure will result in the inability of subsequent processes (such as welding, etc.) to effectively connect with the conductive structure, thereby affecting the reliability of the electrical connection and further affecting the performance of the device. Excessive exposure of the conductive structure will lead to the phenomenon of conductive structure fracture during the subsequent grinding process, causing the conductive structure to be damaged during the grinding process, thereby affecting the performance of the device.

[0057] In view of this, an embodiment of the present application provides a semiconductor structure, a formation method and related devices, wherein the semiconductor structure formation method includes: providing a first substrate and a second substrate, a barrier layer being formed on the first substrate and / or the second substrate; bonding the first substrate and the second substrate to form a stacked substrate, wherein the barrier layer is located between the first substrate and the second substrate; forming a plurality of mutually spaced through holes on the stacked substrate, the through holes at least passing through one of the first substrate and the second substrate and the barrier layer, with the side of the stacked substrate where the through holes are formed being the front side of the stacked substrate, and the side away from the stacked substrate where the through holes are formed being the back side of the stacked substrate; forming a conductive structure in the through hole; using the barrier layer as a grinding stop layer, grinding the back side of the stacked substrate, and using the remaining structure as the target semiconductor structure.

[0058] It can be seen that the method for forming a semiconductor structure provided in an embodiment of the present application forms a through hole that penetrates at least one substrate and a barrier layer in the first substrate and the second substrate, and a conductive structure located in the through hole. When grinding the back side of the stacked substrate, the barrier layer is used as a grinding stop layer to mark the grinding stop position of the back side of the stacked substrate, thereby avoiding grinding of the substrate on the front side of the stacked substrate during the grinding process, thereby avoiding the conductive material in the conductive structure in the through hole from diffusing into the substrate on the front side of the stacked substrate, thereby avoiding device leakage and improving device performance.

[0059] At the same time, based on the stacked substrate, a through hole is formed that penetrates at least one substrate and a barrier layer in the first substrate and the second substrate, as well as a conductive structure located in the through hole, and the barrier layer between the first substrate and the second substrate in the stacked substrate is further used as a grinding stop layer, which can ensure the grinding flatness of the back side of the stacked substrate, thereby avoiding the problem of incomplete or excessive exposure of the conductive structure, thereby improving the performance of the device.

[0060] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments.

[0061] As an optional example of the disclosure content of the embodiment of this application, Figures 3 to 17 A schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure according to an embodiment of the present application is shown.

[0062] refer to Figure 3 , providing a first substrate 100 and a second substrate 200.

[0063] The first substrate 100 and the second substrate 200 are used to provide a basis for subsequently forming a semiconductor structure.

[0064] In this embodiment, the materials of the first substrate 100 and the second substrate 200 may both be silicon. In other embodiments, the materials of the first substrate 100 and the second substrate 200 may be, for example, one or more of silicon, germanium, silicon carbide, gallium arsenide, or indium gallium, or the first substrate 100 and the second substrate 200 may also be a silicon substrate on an insulator or a germanium substrate on an insulator. In a further example, an interface layer may be formed on the surface of the first substrate 100 and the second substrate 200, and the material of the interface layer may be, for example, silicon oxide, silicon nitride, or silicon oxynitride, etc., for isolating and protecting the surfaces of the first substrate 100 and the second substrate 200.

[0065] Wherein, a barrier layer is formed on the first substrate 100 and / or the second substrate 200. It is understood that a barrier layer is formed on the first substrate 100 and / or the second substrate 200, and it may be that only the first substrate 100 is formed with a barrier layer, or only the second substrate 200 is formed with a barrier layer, or both the first substrate 100 and the second substrate 200 are formed with a barrier layer. In the embodiment of the present application, an example is taken in which only the barrier layer is formed on the second substrate 200. In other embodiments, a barrier layer may be formed only on the first substrate 100, or both the first substrate 100 and the second substrate 200 are formed with a barrier layer.

[0066] Specifically, a barrier layer 201 is formed on the second substrate 200, and the barrier layer 201 can be used as a grinding stop layer when the back side of the laminated substrate is subsequently ground, and is used to mark the grinding stop position of the back side of the laminated substrate, thereby avoiding the grinding of the substrate on the front side of the laminated substrate during the grinding process, thereby preventing the conductive material in the conductive structure in the through hole from diffusing into the substrate on the front side of the laminated substrate, thereby avoiding device leakage and improving device performance. At the same time, using the barrier layer between the first substrate and the second substrate in the laminated substrate as a grinding stop layer can ensure the grinding flatness of the back side of the laminated substrate, thereby avoiding the problem of incomplete or excessive exposure of the conductive structure, thereby improving device performance.

[0067] In an optional implementation, the material of the barrier layer 201 may be, for example, silicon nitride or silicon carbonitride. Silicon nitride or silicon carbonitride has high density and a tight internal structure, and can effectively block the penetration and diffusion of conductive ions in the conductive structure. Therefore, the barrier layer made of silicon nitride or silicon carbonitride effectively prevents the conductive material from diffusing into the substrate during the subsequent grinding process.

[0068] refer to Figure 4-Figure 5 , bonding the first substrate 100 and the second substrate 200 to form a stacked substrate 1.

[0069] Wherein, the barrier layer is located between the first substrate and the second substrate.

[0070] In an optional implementation, the step of bonding the first substrate and the second substrate to form a stacked substrate may include: forming a first oxide layer on the first substrate; forming a second oxide layer on the second substrate; and bonding the first substrate and the second substrate based on the first oxide layer and the second oxide layer to form a stacked substrate. Accordingly, the process of bonding the first substrate 100 and the second substrate 200 to form the stacked substrate 1 may be, for example, as follows:

[0071] refer to Figure 4, a first oxide layer 101 is formed on the first substrate 100 , and a second oxide layer 202 is formed on the second substrate 200 .

[0072] The first oxide layer 101 and the second oxide layer 202 are used to bond the first substrate 100 and the second substrate 200. The first oxide layer 101 and the second oxide layer 202 can make the first substrate 100 and the second substrate 200 firmly bonded together. The material of the first oxide layer 101 can be, for example, silicon oxide. The material of the second oxide layer 202 can be, for example, silicon oxide.

[0073] In a specific implementation, the first oxide layer 101 and the second oxide layer 202 can be formed on the first substrate 100 and the second substrate 200 respectively by thermal oxidation or chemical vapor deposition. The thermal oxidation method refers to exposing the substrate to a high-temperature oxidizing environment (such as oxygen or water vapor) so that the substrate surface reacts with oxygen to generate a silicon oxide layer. The chemical vapor deposition (CVD) refers to introducing a compound gas containing silicon and oxygen into a reaction chamber to cause a chemical reaction on the substrate surface to deposit a silicon oxide layer.

[0074] It should be noted that since a barrier layer is formed on the first substrate and / or the second substrate, in the steps of forming a first oxide layer on the first substrate and forming a second oxide layer on the second substrate, if a barrier layer is formed on the first substrate, the first oxide layer is located on the barrier layer; if a barrier layer is formed on the second substrate, the second oxide layer is located on the barrier layer. In the embodiment of the present application, the example in which only a barrier layer is formed on the second substrate is used for explanation, and accordingly, in the embodiment of the present application, the second oxide layer is located on the barrier layer.

[0075] refer to Figure 5 Based on the first oxide layer 101 and the second oxide layer 202 , the first substrate 100 and the second substrate 200 are bonded to form a stacked substrate 1 .

[0076] Under the action of high temperature and pressure, atoms between the first oxide layer 101 and the second oxide layer 202 diffuse and combine with each other to form stable chemical bonds, thereby achieving a firm bond between the first substrate 100 and the second substrate 200 .

[0077] In the semiconductor manufacturing process, by forming the first oxide layer 101 and the second oxide layer 202 on the first substrate 100 and the second substrate 200 respectively, the bonding between the two substrates can be effectively promoted.

[0078] It should be noted that the above-mentioned bonding by forming an oxide layer is only an optional example. In other embodiments, other bonding methods known to those skilled in the art may also be selected, and the present application does not limit this.

[0079] In an optional implementation, when a barrier layer is formed on the first substrate or the second substrate, the step of bonding the first substrate and the second substrate to form a stacked substrate is specifically: bonding the first substrate formed with the barrier layer to the second substrate to form a stacked substrate; or bonding the second substrate formed with the barrier layer to the first substrate to form a stacked substrate.

[0080] In the embodiment of the present application, an example is used to illustrate that only the barrier layer is formed on the second substrate 200. Accordingly, the bonding of the first substrate and the second substrate to form a stacked substrate is specifically: bonding the second substrate with the barrier layer formed thereon to the first substrate to form a stacked substrate.

[0081] refer to Figure 6 , thinning the laminate substrate 1.

[0082] The stacked substrate 1 is thinned so that the remaining height of the second substrate 200 in the thinned stacked substrate 1 meets the height of a target semiconductor structure to be formed subsequently.

[0083] In this embodiment, a chemical mechanical polishing (CMP) process is used to thin the laminated substrate 1 to efficiently remove the material on the surface of the laminated substrate while maintaining a high surface flatness and smoothness. In other embodiments, other processes may also be used to thin the laminated substrate, and the embodiments of the present application are not limited to this.

[0084] refer to Figure 7-Figure 9 , a plurality of mutually spaced through holes are formed on the laminate substrate 1.

[0085] The side of the laminated substrate 1 where the through hole is formed is the front side of the laminated substrate 1 , and the side away from the laminated substrate 1 where the through hole is formed is the back side of the laminated substrate 1 .

[0086] The through hole is used to provide a receiving space for a conductive structure formed subsequently.

[0087] In an optional implementation, the through hole may be formed, for example, by combining photolithography and etching. Accordingly, the formation process of the through hole may be, for example, as follows:

[0088] refer to Figure 7 , a dielectric layer 300 is formed on the laminated substrate 1.

[0089] The dielectric layer 300 is used to protect the laminated substrate 1 to prevent the laminated substrate 1 from being damaged.

[0090] In this embodiment, the material of the dielectric layer 300 may be, for example, silicon oxide or silicon nitride. In other embodiments, the material of the dielectric layer 300 may also be amorphous carbon. In other embodiments, the material of the dielectric layer 300 may also be one or more of SiOC, SiOCH, SiC, SiCN, SiO2, SiN, and SiON.

[0091] refer to Figure 8 , a patterned photolithography layer 301 is formed on the dielectric layer 300 .

[0092] A layer of photoresist is coated on the surface of the dielectric layer 300, and the photoresist is patterned through a photolithography process (including exposure, development and other steps) to form a patterned photoresist layer 301. The patterned photoresist layer 301 is used to define the area of ​​the dielectric layer 300 that needs to be removed or retained in the subsequent process, thereby indirectly defining the position and shape of the through hole.

[0093] refer to Fig. 9 , removing the dielectric layer 300 exposed by the photolithography layer 301 and at least a portion of the thickness of the laminated substrate 1 to form a through hole.

[0094] In an optional implementation, an etching process may be used to remove the dielectric layer exposed by the photolithography layer and at least a portion of the thickness of the laminated substrate to form the through hole. The etching process may be a dry etching process or a wet etching process or a combination of the two. In other words, the etching process may be a dry etching process, a wet etching process, or an etching process combining dry and wet etching processes.

[0095] In order to ensure that the subsequent conductive structure can be fully exposed, the through hole at least penetrates one of the first substrate and the second substrate and the barrier layer. In the embodiment of the present application, the barrier layer 201 is formed only on the second substrate 200 as an example. Accordingly, the bonding of the first substrate 100 and the second substrate 200 to form the stacked substrate 1 is specifically: the second substrate 200 formed with the barrier layer 201 is bonded to the first substrate 100 to form the stacked substrate 1. Further, the through hole at least penetrates one of the first substrate 100 and the second substrate 200 and the barrier layer, specifically: the through hole at least penetrates the second substrate 200 and the barrier layer 201.

[0096] In an optional implementation, the step of removing the dielectric layer exposed by the photolithography layer and at least a portion of the thickness of the laminated substrate to form the through hole may include: removing the dielectric layer exposed by the photolithography layer and at least a portion of the thickness of the laminated substrate to form a through hole penetrating the dielectric layer and at least a portion of the thickness of the laminated substrate.

[0097] refer to Fig.10 , remove the photolithography layer on the dielectric layer 300.

[0098] refer to Fig.11 , forming an insulating layer 401 covering the dielectric layer 300 and the sidewalls and bottom of the through hole.

[0099] In an optional implementation, a layer of insulating material may be uniformly coated on the sidewall of the through hole by a deposition process (such as chemical vapor deposition CVD, physical vapor deposition PVD or atomic layer deposition ALD, etc.) to form an insulating layer 401. The insulating layer 401 may prevent the subsequently formed conductive structure from making electrical contact with the material around the through hole (such as a substrate or other layer structures), thereby ensuring the stability of the circuit.

[0100] The material of the insulating layer 401 may be, for example, silicon oxide or silicon nitride.

[0101] It should be noted that the material of the above-mentioned insulating layer is only an optional example. In practical applications, the material of the insulating layer can be selected from various materials familiar to those skilled in the art according to actual conditions. The embodiment of the present application does not limit the material of the insulating layer.

[0102] refer to Fig.12 , an isolation layer 402 is formed on the insulating layer 401 .

[0103] In an optional implementation, a layer of isolation material may be uniformly coated on the insulating layer 401 by a deposition process (such as chemical vapor deposition CVD, physical vapor deposition PVD or atomic layer deposition ALD, etc.) to form an isolation layer 402. The isolation layer 402 can effectively block the diffusion of the conductive material in the conductive structure and prevent it from damaging the insulating layer 401, thereby protecting the insulating layer 401.

[0104] The material of the isolation layer 402 may be, for example, tantalum (Ta), tantalum nitride (TaN) or titanium nitride (TiN).

[0105] It should be noted that the material of the above-mentioned isolation layer is only an optional example. In practical applications, the material of the isolation layer can be selected from various materials familiar to those skilled in the art according to actual conditions. The embodiment of the present application does not limit the material of the isolation layer.

[0106] refer to Figure 13-14, forming a conductive structure 404 in the through hole.

[0107] In an optional example, the step of forming a conductive structure in the through hole may include: forming a conductive structure material layer on the isolation layer, the conductive structure material layer completely filling the through hole; using the dielectric layer as a stop layer, grinding the front side of the laminated substrate, and using the remaining conductive structure material layer as the conductive structure. Accordingly, the process of forming the conductive structure in the through hole may be, for example, as follows:

[0108] refer to Fig.13 , a conductive structure material layer 403 is formed on the isolation layer 402, and the conductive structure material layer 403 completely fills the through hole.

[0109] After forming the insulating layer 401 and the isolation layer 402, a conductive material may be filled inside the through hole to form a conductive structure material layer 403. For example, the filling of the conductive material may be achieved by a deposition technique. The material of the conductive structure material layer 403 may be, for example, copper (Cu), tungsten (W), aluminum (Al), etc.

[0110] It should be noted that the material of the above-mentioned conductive structure material layer is only an optional example. In practical applications, the material of the conductive structure material layer can be selected from various materials familiar to technical personnel in this field according to actual conditions. The embodiment of the present application does not limit the material of the conductive structure material layer.

[0111] In a specific implementation, during the process of filling the conductive material, it is necessary to ensure that the conductive material completely fills the through hole to ensure the connectivity and reliability of the circuit.

[0112] refer to Fig.14 , using the dielectric layer 300 as a stop layer, grinding the front side of the laminated substrate 1 , and using the remaining conductive structure material layer 403 as a conductive structure 404 .

[0113] In this embodiment, a chemical mechanical polishing (CMP) process is used to polish the front side of the laminated substrate to efficiently remove the material on the front side of the laminated substrate while maintaining a high surface flatness and smoothness.

[0114] refer to Figure 15-17 , using the barrier layer 201 as a grinding stop layer, grinding the back side of the stacked substrate 1, and using the remaining structure as the target semiconductor structure.

[0115] The barrier layer 201 is used to mark the grinding stop position of the back side of the laminated substrate 1 .

[0116] In an optional implementation, in order to facilitate grinding the back side of the laminated substrate 1, the front side of the laminated substrate 1 may be temporarily bonded to a support structure (e.g., a glass slide). Accordingly, the specific process of grinding the back side of the laminated substrate using the barrier layer as a grinding stop layer and using the remaining structure as the target semiconductor structure may be as follows:

[0117] refer to Fig.15 , temporarily bond the front side of the laminate substrate 1 to the glass slide 2.

[0118] By temporarily bonding the laminated substrate 1 and the glass slide 2, the front side of the laminated substrate 1 can be protected to avoid damage during the grinding process, and the grinding uniformity of the back side of the laminated substrate 1 can be ensured.

[0119] In the temporary bonding process, it is necessary to select a suitable bonding material and ensure that it can be easily removed after the grinding process is completed without causing residual contamination or damage to the laminated substrate or the glass slide. Specifically, the bonding material may be, for example, an organic polymer, wax, glue, or the like.

[0120] In an optional implementation, a layer of bonding material may be coated on the surface of the glass slide 2 to achieve temporary bonding between the front side of the laminated substrate 1 and the glass slide 2. The coating method may include but is not limited to coating with a spin coater, spraying or manual coating.

[0121] refer to Fig.16 , using the barrier layer 201 as a grinding stop layer, grinding the back side of the stacked substrate, and using the remaining structure as the target semiconductor structure.

[0122] In this embodiment, a chemical mechanical polishing (CMP) process is used to polish the back side of the laminated substrate to efficiently remove the material on the back side of the laminated substrate while maintaining a high surface flatness and smoothness.

[0123] By forming a through hole that penetrates at least one substrate and a barrier layer in the first substrate and the second substrate, and a conductive structure located in the through hole, when grinding the back side of the laminated substrate, the barrier layer is used as a grinding stop layer to mark the grinding stop position of the back side of the laminated substrate, thereby avoiding grinding of the substrate on the front side of the laminated substrate during the grinding process, thereby avoiding the conductive material in the conductive structure in the through hole from diffusing into the substrate on the front side of the laminated substrate, thereby avoiding device leakage and improving device performance.

[0124] At the same time, based on the stacked substrate, a through hole is formed that penetrates at least one substrate and a barrier layer in the first substrate and the second substrate, as well as a conductive structure located in the through hole, and the barrier layer between the first substrate and the second substrate in the stacked substrate is further used as a grinding stop layer, which can ensure the grinding flatness of the back side of the stacked substrate, thereby avoiding the problem of incomplete or excessive exposure of the conductive structure, thereby improving the performance of the device.

[0125] In addition, after forming the conductive structure, the embodiment of the present application only needs to grind and planarize the back side of the laminated substrate to meet the required process requirements. This process eliminates the complicated subsequent steps in the BFR and BVR processes, such as etching and the formation of the dielectric layer, thereby not only simplifying the overall process flow, but also significantly reducing production costs and improving production efficiency.

[0126] refer to Fig.17 , remove the glass slide.

[0127] After the back grinding of the laminated substrate is completed, the bonding material can be removed by using an appropriate solvent or method to separate the laminated substrate 1 from the glass slide 2. By separating the laminated substrate 1 from the glass slide 2, a processed laminated substrate (i.e., the target semiconductor structure) can be obtained.

[0128] In an optional implementation, when a barrier layer is formed on the first substrate and the second substrate, the step of using the barrier layer as a grinding stop layer, grinding the back side of the stacked substrate, and using the remaining structure as the target semiconductor structure is specifically: using the barrier layer close to the front side of the stacked substrate as a grinding stop layer, grinding the back side of the stacked substrate, and using the remaining structure as the target semiconductor structure.

[0129] It can be seen that the method for forming a semiconductor structure provided in an embodiment of the present application forms a through hole that penetrates at least one substrate and a barrier layer in the first substrate and the second substrate, and a conductive structure located in the through hole. When grinding the back side of the stacked substrate, the barrier layer is used as a grinding stop layer to mark the grinding stop position of the back side of the stacked substrate, thereby avoiding grinding of the substrate on the front side of the stacked substrate during the grinding process, thereby avoiding the conductive material in the conductive structure in the through hole from diffusing into the substrate on the front side of the stacked substrate, thereby avoiding device leakage and improving device performance.

[0130] At the same time, based on the stacked substrate, a through hole is formed that penetrates at least one substrate and a barrier layer in the first substrate and the second substrate, as well as a conductive structure located in the through hole, and the barrier layer between the first substrate and the second substrate in the stacked substrate is further used as a grinding stop layer, which can ensure the grinding flatness of the back side of the stacked substrate, thereby avoiding the problem of incomplete or excessive exposure of the conductive structure, thereby improving the performance of the device.

[0131] An embodiment of the present application further provides a semiconductor structure, which is formed based on the method for forming the semiconductor structure as described above.

[0132] An embodiment of the present application also provides a packaging structure, which includes the semiconductor structure as described above.

[0133] An embodiment of the present application further provides a chip, wherein the chip includes the semiconductor structure as described above, or the chip includes the packaging structure as described above.

[0134] An embodiment of the present application further provides an integrated circuit structure, which includes the semiconductor structure as described above, or the integrated circuit structure includes the packaging structure as described above.

[0135] The above describes multiple implementation schemes provided by the embodiments of the present application. The various optional methods introduced in each implementation scheme can be combined and cross-referenced with each other without conflict, thereby extending a variety of possible implementation schemes, which can all be considered as implementation schemes disclosed and open in the embodiments of the present application.

[0136] Although the embodiments of the present application are disclosed above, the present application is not limited thereto. Any person skilled in the art may make various changes and modifications without departing from the spirit and scope of the present application. Therefore, the scope of protection of the present application shall be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: Providing a first substrate and a second substrate, wherein a barrier layer is formed on the first substrate and / or the second substrate; Bonding the first substrate and the second substrate to form a stacked substrate, wherein the barrier layer is located between the first substrate and the second substrate; A plurality of mutually spaced through holes are formed on the laminate substrate, wherein the through holes penetrate at least one of the first substrate and the second substrate and the barrier layer, and the side of the laminate substrate where the through holes are formed is the front side of the laminate substrate, and the side away from the laminate substrate where the through holes are formed is the back side of the laminate substrate; forming a conductive structure in the through hole; The barrier layer is used as a grinding stop layer to grind the back side of the stacked substrate, and the remaining structure is used as a target semiconductor structure.

2. The method for forming a semiconductor structure according to claim 1, wherein: When a barrier layer is formed on the first substrate or the second substrate, the step of bonding the first substrate and the second substrate to form a stacked substrate is specifically: Bonding the first substrate formed with the barrier layer to the second substrate to form a stacked substrate; or, A second substrate having a barrier layer formed thereon is bonded to the first substrate to form a stacked substrate.

3. The method for forming a semiconductor structure according to claim 1, wherein: When a barrier layer is formed on the first substrate and the second substrate, the step of using the barrier layer as a grinding stop layer, grinding the back side of the stacked substrate, and using the remaining structure as the target semiconductor structure is specifically: The barrier layer close to the front surface of the stacked substrate is used as a grinding stop layer, the back surface of the stacked substrate is ground, and the remaining structure is used as a target semiconductor structure.

4. The method for forming a semiconductor structure according to claim 1, wherein: The step of bonding the first substrate and the second substrate to form a stacked substrate comprises: forming a first oxide layer on the first substrate; forming a second oxide layer on the second substrate; Based on the first oxide layer and the second oxide layer, the first substrate and the second substrate are bonded to form a stacked substrate.

5. The method for forming a semiconductor structure according to claim 1, wherein: After the step of bonding the first substrate and the second substrate to form a laminated substrate and before the step of forming a plurality of mutually spaced through holes on the laminated substrate, the method further includes: The laminated substrate is thinned.

6. The method for forming a semiconductor structure according to claim 1, wherein: The step of forming a plurality of mutually spaced through holes on the laminate substrate comprises: forming a dielectric layer on the laminate substrate; forming a patterned photolithography layer on the dielectric layer; The dielectric layer exposed by the photoresist layer and at least a portion of the thickness of the laminated substrate are removed to form the through hole.

7. The method for forming a semiconductor structure according to claim 6, wherein: The step of removing the dielectric layer exposed by the photolithography layer and at least a portion of the thickness of the laminated substrate to form the through hole comprises: The dielectric layer and at least a portion of the thickness of the laminated substrate exposed by the photolithography layer are removed to form a through hole penetrating the dielectric layer and at least a portion of the thickness of the laminated substrate.

8. The method for forming a semiconductor structure according to claim 6, wherein: The dielectric layer exposed by the photolithography layer and at least a portion of the thickness of the laminated substrate are removed by an etching process to form the through hole.

9. The method for forming a semiconductor structure according to claim 8, characterized in that: The etching process is a dry etching process or a wet etching process or a combination of both.

10. The method for forming a semiconductor structure according to claim 6, wherein: After the step of forming a plurality of mutually spaced through holes on the laminated substrate and before the step of forming a conductive structure in the through hole, the method further includes: forming an insulating layer covering the dielectric layer, and the sidewalls and bottom of the through hole; An isolation layer is formed on the insulating layer.

11. The method for forming a semiconductor structure according to claim 10, characterized in that: After the step of forming a plurality of mutually spaced through holes on the laminated substrate and before the step of forming an insulating layer covering the dielectric layer and the sidewalls and bottom of the through holes, the method further includes: The photoresist layer on the dielectric layer is removed.

12. The method for forming a semiconductor structure according to claim 10, wherein: The step of forming a conductive structure in the through hole comprises: forming a conductive structural material layer on the isolation layer, wherein the conductive structural material layer completely fills the through hole; The dielectric layer is used as a stop layer to grind the front surface of the laminated substrate, and the remaining conductive structure material layer is used as a conductive structure.

13. The method for forming a semiconductor structure according to claim 1, wherein: The material of the barrier layer is silicon nitride or silicon carbonitride.

14. A semiconductor structure, characterized in that: The semiconductor structure is formed based on the method for forming a semiconductor structure according to any one of claims 1 to 13.

15. A packaging structure, characterized in that: The package structure comprises the semiconductor structure according to claim 14 .

16. A chip, characterized in that: The chip includes the semiconductor structure according to claim 14 , or the chip includes the package structure according to claim 15 .

17. An integrated circuit structure, characterized in that: The integrated circuit structure includes the semiconductor structure according to claim 14 , or the integrated circuit structure includes the package structure according to claim 15 .

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