Motor drive circuit

Abstract

A motor drive circuit includes first to fourth field effect transistors (FETs) forming a full bridge circuit, first to fourth drive circuits, a control circuit, and a switch. When the control circuit is in the sleep mode, the control circuit is switched on. The switch operates at least one of the first to fourth drive circuits such that the at least one of the first to fourth drive circuits outputs the first high voltage to at least one of the gates of the first to fourth FETs and at least one of the fourth high voltages.

Description

Technical Field

[0001] The present disclosure relates to a motor drive circuit. Background Art

[0002] Japanese Patent Application Laid-Open No. 2015-171206 discloses an inverter circuit configured to drive an electric motor using an active high switch. The active high switch is a switch configured to be turned on in response to receiving a positive logic signal. Summary of the invention

[0003] A typical motor drive circuit includes (i) four field effect transistors (FETs), (ii) four drive circuits configured to turn on or off the respective FETs, and (iii) a control unit configured to control the output of the respective drive circuits (i.e., the respective voltages applied to the respective gates of the FETs).

[0004] In the case where each of the driving circuits has a bipolar transistor, when the control unit enters the sleep mode, if the control unit outputs a negative logic signal to all the driving circuits, the standby current in all the driving circuits can be reduced.

[0005] However, the drive circuit is sometimes configured to operate in negative logic (or active low). The drive circuit turns on each FET when receiving a negative logic signal, and turns off each FET when receiving a positive logic signal.

[0006] Therefore, when the control unit outputs negative logic signals to the four drive circuits to reduce the standby current of the motor drive circuit during the sleep mode, all four FETs are turned on, so-called arm short circuit occurs. As a result, the motor drive circuit may be damaged by the through current flowing through the motor drive circuit.

[0007] One aspect of the present disclosure is to reduce standby current and shoot-through current in a motor drive circuit during sleep mode.

[0008] One aspect of the present disclosure provides a motor drive circuit configured to drive an electric motor for a vehicle seat. The motor drive circuit includes first to fourth field effect transistors (FETs), first to fourth drive circuits, a control circuit, and a switch.

[0009] The first FET to the fourth FET form a full-bridge circuit. The first FET and the second FET are high-side switches of the full-bridge circuit. The third FET and the fourth FET are low-side switches of the full-bridge circuit. The first FET to the fourth FET are configured to (i) switch to their respective on-states in response to their respective gates receiving the first low voltage to the fourth low voltage respectively; and (ii) switch to their respective off-states in response to their respective gates receiving the first high voltage to the fourth high voltage respectively. The first high voltage to the fourth high voltage are all higher than the corresponding first low voltage to the fourth low voltage.

[0010] The first to fourth drive circuits each include a first to fourth bipolar transistor. The first to fourth bipolar transistors are configured to (i) switch to their respective on-states in response to their respective bases receiving first to fourth positive logic signals, respectively; and (ii) switch to their respective off-states in response to their respective bases receiving first to fourth negative logic signals, respectively. The first to fourth drive circuits are configured to (i) output the first to fourth low voltages to the respective gates of the first FET to the fourth FET in response to the first to fourth bipolar transistors being in their respective on-states; and (ii) output the first to fourth high voltages to the respective gates of the first FET to the fourth FET in response to the first to fourth bipolar transistors being in their respective off-states.

[0011] The control circuit is configured to output the corresponding first positive logic signal to the fourth positive logic signal or the corresponding first negative logic signal to the fourth negative logic signal to the respective bases of the first bipolar transistor to the fourth bipolar transistor. The control circuit is configured to output the corresponding first negative logic signal to the fourth negative logic signal to the respective bases of the first bipolar transistor to the fourth bipolar transistor when the control circuit is in its sleep mode.

[0012] The switch is configured to operate at least one of the first to fourth drive circuits when the control circuit is in the sleep mode so that the at least one of the first to fourth drive circuits outputs at least one of the first to fourth high voltages.

[0013] In the motor drive circuit configured as above, when the control circuit is in the sleep mode, the control circuit outputs the corresponding first to fourth negative logic signals to the first to fourth drive circuits. As a result, the standby current of the first to fourth drive circuits can be reduced.

[0014] Furthermore, when the control circuit is in the sleep mode, the switch is operated so that at least one of the first to fourth drive circuits outputs at least one of the first to fourth high voltages. As a result, at least one of the first to fourth FETs is turned off, thereby reducing the through current.

[0015] The motor drive circuit may have a reference ground (GND). The first drive circuit to the fourth drive circuit may have respective output stages connected to the respective gates of the first FET to the fourth FET. The respective output stages may be configured to (i) output the corresponding first low voltage to the fourth low voltage in response to the respective output stages being electrically connected to the reference ground; and (ii) output the corresponding first high voltage to the fourth high voltage in response to the respective output stages being electrically disconnected from the reference ground. The switch may be configured to electrically disconnect at least one of the respective output stages from the reference ground when the control circuit is in the sleep mode.

[0016] The switch may be a semiconductor switch configured to electrically disconnect the at least one of the respective output stages from the reference ground by switching to an off state of the semiconductor switch. Examples of the semiconductor switch include a Darlington transistor.

[0017] The first FET and the second FET may include: (i) their respective sources connected to the positive electrode of the power supply of the electric motor, and (ii) their respective drains connected to the electric motor. The third FET and the fourth FET may include: (i) their respective sources connected to the electric motor, and (ii) their respective drains connected to the reference ground.

[0018] The switch can be configured to operate the first drive circuit and / or the second drive circuit in response to receiving the third negative logic signal and the fourth negative logic signal so that the first drive circuit and / or the second drive circuit output the corresponding first high voltage and / or the second high voltage.

[0019] The motor drive circuit may include a first transmission path configured to transmit the third positive logic signal and the third negative logic signal from the control circuit to the third drive circuit. The motor drive circuit may include a second transmission path configured to transmit the fourth positive logic signal and the fourth negative logic signal from the control circuit to the fourth drive circuit. The motor drive circuit may include a first diode, the first diode including: (i) a first cathode connected to the switch, and (ii) a first anode connected to the first transmission path. The motor drive circuit may include a second diode, the second diode including: (i) a second cathode connected to the switch, and (ii) a second anode connected to the second transmission path.

[0020] In the motor drive circuit configured as above, the switch operates the first drive circuit and / or the second drive circuit in response to the third negative logic signal for the third drive circuit or the fourth negative logic signal for the fourth drive circuit, so the control circuit does not need to output an additional negative logic signal for the switch. In addition, when (i) the third negative logic signal is output to the switch and (ii) the fourth positive logic signal is output to the switch, the first diode can prevent the fourth positive logic signal from being transmitted to the third drive circuit. When (i) the third positive logic signal is output to the switch and (ii) the fourth negative logic signal is output to the switch, the second diode can prevent the third positive logic signal from being transmitted to the fourth drive circuit.

[0021] The control circuit may be a microcomputer having a first output port to a fourth output port. The first output port to the fourth output port may be configured to output the corresponding first positive logic signal to the fourth positive logic signal or the corresponding first negative logic signal to the fourth negative logic signal, respectively.

[0022] The motor control circuit may include: a first circuit board, the first circuit board includes the control circuit; and a second circuit board, the second circuit board (i) is different from the first circuit board and (ii) includes the first FET to the fourth FET, the first drive circuit to the fourth drive circuit, and the switch.

[0023] If the second circuit board is stacked on the first circuit board, or if the first circuit board is stacked on the second circuit board, an area required for providing the motor drive circuit can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1is a circuit diagram of a motor drive circuit according to an embodiment.

[0025] Figure 2 It is shown Figure 1 A circuit diagram showing details of the first drive circuit and the switch in the circuit diagram.

[0026] Figure 3 is a schematic diagram showing the configuration of a motor drive circuit. DETAILED DESCRIPTION

[0027] Exemplary embodiments of the present disclosure are described below with reference to the accompanying drawings.

[0028] The embodiment described below is merely an example of an embodiment to show the technical scope of the present disclosure. That is, the technical solutions and the like described in the claims are not limited to the specific structures or configurations shown in the following embodiment.

[0029] This embodiment provides an example of applying the motor drive circuit of the present disclosure to a seat installed in a vehicle (hereinafter referred to as a "seat"). For components or parts that are marked with at least one symbol for explanation, at least one is provided unless it is stated in advance that "only one" or the like.

[0030] 1. Overview of Motor Drive Circuit

[0031] This embodiment provides Figure 1 The motor drive circuit 1 is shown. The motor drive circuit 1 is configured to drive an electric motor 3 mounted on the seat 20. The electric motor 3 is configured to function as a drive source for a sliding device (not shown) or a reclining device (not shown) in the seat 20. In the present embodiment, the motor drive circuit 1 is also mounted on the seat 20, but it does not necessarily have to be mounted on the seat 20.

[0032] 2. Configuration of the motor drive circuit

[0033] The motor drive circuit 1 includes at least first FET5 to fourth FET8, first drive circuit 9 to fourth drive circuit 12, control circuit 13, switch 14, first diode 15A, and second diode 15B. In the present embodiment, first FET5 to fourth FET8 are enhancement mode P-channel metal oxide semiconductor field effect transistors (MOSFET). In other embodiments, first FET5 to fourth FET8 may be P-channel crystalline field effect transistors (JFET).

[0034] The 1st FET5 to the 4th FET8 form a full-bridge circuit (or an H-bridge circuit). More specifically, the 1st FET5 and the 2nd FET6 are high-side switches, and their sources (S) are connected to the positive electrode V+ of the power supply. The power supply supplies direct current to the electric motor drive circuit 1 and the electric motor 3. The 3rd FET7 and the 4th FET8 are low-side switches, and their drains (D) are connected to the reference ground (GND) of the motor drive circuit 1. The reference ground has a potential equal to the potential of the negative electrode of the power supply. The drains of the 1st FET5 and the 2nd FET6 are connected to the sources of the 3rd FET7 and the 4th FET8, respectively. The electric motor 3 has (i) a first terminal connected to the drain of the 1st FET5 and the source of the 3rd FET7, and (ii) a second terminal connected to the drain of the 2nd FET6 and the source of the 4th FET8.

[0035] The first drive circuit 9 to the fourth drive circuit 12 are configured to respectively turn on or off the corresponding first FET 5 to the fourth FET 8. Specifically, the first drive circuit 9 and the second drive circuit 10 are configured to apply voltages to the respective gates (G) of the first FET 5 and the second FET 6. The third drive circuit 11 and the fourth drive circuit 12 are configured to apply voltages to the respective gates of the third FET 7 and the fourth FET 8.

[0036] Each of the first to fourth drive circuits 9 to 12 includes one or more bipolar transistors (three bipolar transistors in the present embodiment).

[0037] The control circuit 13 is configured to independently control the first drive circuit 9 to the fourth drive circuit 12. In the present embodiment, the control circuit 13 is a microcomputer, but is not limited to a microcomputer. The control circuit 13 has a first output port P1 to a fourth output port P4, and the control circuit 13 is configured to output a first negative logic signal to a fourth negative logic signal or a first positive logic signal to a fourth positive logic signal from the first output port P1 to the fourth output port P4 to control the first FET 5 to the fourth FET 8. Each of the first negative logic signal to the fourth negative logic signal has a first voltage (approximately 0 volts in the present embodiment), and each of the first positive logic signal to the fourth positive logic signal has a second voltage (for example, approximately 5 volts) higher than the first voltage.

[0038] The switch 14 is configured to operate the first drive circuit 9 and the second drive circuit 10 to set (i) the voltage between the gate and the source of the first FET5 and (ii) the voltage between the gate and the source of the second FET6 to a low voltage or a high voltage. In the present embodiment, the switch 14 includes a semiconductor switch. The low voltage has a magnitude that turns off the first FET5 and the second FET6 (approximately 0 volts in the present embodiment). The high voltage has a magnitude that turns on the first FET5 and the second FET6 (approximately equal to the voltage of the positive electrode V+ of the power supply in the present embodiment).

[0039] like Figure 2 As shown, in the present embodiment, the first drive circuit 9 includes (i) an input stage including a first bipolar transistor Tr1 and (ii) an output stage including a second bipolar transistor Tr2 and a third bipolar transistor Tr3 .

[0040] The first bipolar transistor Tr1 is an npn-type bipolar transistor, and the second bipolar transistor Tr2 and the third bipolar transistor Tr3 are pnp bipolar transistors.

[0041] The base of the first bipolar transistor Tr1 is connected to the first output port P1 of the control circuit 13 via the first resistor R1. The emitter of the first bipolar transistor Tr1 is connected to the reference ground and is also connected to the base of the first bipolar transistor Tr1 via the second resistor R2. The collector of the first bipolar transistor Tr1 is connected to the positive electrode V+ of the power supply via the third resistor R3 and the fourth resistor R4.

[0042] The base of the second bipolar transistor Tr2 is connected to the collector of the first bipolar transistor Tr1 via the third resistor R3. The emitter of the second bipolar transistor Tr2 is connected to the positive electrode V+ of the power supply. The collector of the second bipolar transistor Tr2 is connected to the switch 14 via the fifth resistor R5.

[0043] The base of the third bipolar transistor Tr3 is connected to the collector of the second bipolar transistor Tr2. The emitter of the third bipolar transistor Tr3 is connected to the positive electrode V+ of the power supply via the sixth resistor R6 and the seventh resistor R7. The emitter of the third bipolar transistor Tr3 is also connected to the collector of the second bipolar transistor Tr2 via the third diode D3. The anode of the third diode D3 is connected to the collector of the second bipolar transistor Tr2. The cathode of the third diode is connected to the emitter of the third bipolar transistor Tr3. The emitter of the third bipolar transistor Tr3 is also connected to the gate of the first FET5 via the sixth resistor R6.

[0044] The output stage of the first drive circuit 9 further includes a Zener diode ZD1 . The cathode of the Zener diode ZD1 is connected to the positive electrode V+ of the power supply, and the anode of the Zener diode ZD1 is connected to the gate of the first field effect transistor 5 .

[0045] In the first drive circuit 9 constructed as described above, when the base of the first bipolar transistor Tr1 receives the first positive logic signal from the first output port P1, the first bipolar transistor Tr1 is turned on, and then the second bipolar transistor Tr2 is also turned on. If the switch 14 is in its on state when the second bipolar transistor Tr2 is turned on, the third bipolar transistor Tr3 is turned on. While the third transistor Tr3 is in its on state, the above-mentioned low voltage continues to be applied to the gate of the first FET5.

[0046] When the base of the first bipolar transistor Tr1 receives the first negative logic signal from the first output port P1, the first bipolar transistor Tr1 is turned off, and then the second bipolar transistor Tr2 and the third bipolar transistor Tr3 are also turned off. During the period when the third transistor Tr3 is in its off state, the above-mentioned high voltage continues to be applied to the gate of the first FET5.

[0047] In this embodiment, the second drive circuit 10 has the same electrical structure as the first drive circuit 9. The third drive circuit 11 and the fourth drive circuit 12 have the same electrical structure as the first drive circuit 9, but are different from the first drive circuit 9 in that the collectors of the third transistors Tr3 are not connected to the reference ground via the switch 14.

[0048] In the present embodiment, the switch 14 includes a Darlington transistor Tr4. The base of the Darlington transistor Tr4 is connected to the cathode of the first diode 15A and the cathode of the second diode 15B via the eighth resistor R8. The collector of the Darlington transistor Tr4 is connected to the collector of the third bipolar transistor Tr3 of the first drive circuit 9. The emitter of the Darlington transistor Tr4 is connected to the reference ground. The emitter of the Darlington transistor Tr4 is also connected to the base of the Darlington transistor Tr4 via the ninth resistor R9.

[0049] An anode of the first diode 15A and an anode of the second diode 15B are connected to a third output port P3 and a fourth output port P4 of the control circuit 13 , respectively.

[0050] In the switch 14 constructed as described above, when the base of the Darlington transistor Tr4 receives the third positive logic signal from the third output port P3 or the fourth positive logic signal from the fourth output port P4, the Darlington transistor Tr4 is turned on, and the collector of the third bipolar transistor Tr3 of the first drive circuit 9 and the second drive circuit 10 is electrically connected to the reference ground.

[0051] When the corresponding third and fourth negative logic signals are output from the third and fourth output ports P3 and P4, respectively, the Darlington transistor Tr4 is turned off, and the collectors of the third bipolar transistors Tr3 of the first and second drive circuits 9 and 10 are electrically disconnected from the reference ground.

[0052] When (i) the third negative logic signal is output from the third output port P3 and (ii) the fourth positive logic signal is output from the fourth output port P3 , the first diode 15A prevents the fourth positive logic signal from being transmitted to the third drive circuit 11 .

[0053] When (i) the third positive logic signal is output from the third output port P3 and (ii) the fourth negative logic signal is output from the fourth output port P3 , the second diode 15B prevents the third positive logic signal from being transmitted to the fourth drive circuit 12 .

[0054] When the control circuit 13 turns on any one of the first FET5 to the fourth FET8, the control circuit 13 outputs a corresponding one of the first positive logic signal to the fourth positive logic signal to the corresponding one of the first drive circuit 9 to the fourth drive circuit 12. When the control circuit 13 is in its sleep mode, the control circuit 13 outputs a corresponding first negative logic signal to the fourth negative logic signal to the first drive circuit 9 to the fourth drive circuit 12, respectively.

[0055] 3. Installation of motor drive circuit

[0056] like Figure 3 As shown, the control circuit 13 is mounted on the first circuit board 16. The first FET 5 to the fourth FET 8, the first drive circuit 9 to the fourth drive circuit 12, the switch 14, and the first diode 15A and the second diode 15B are mounted on the second circuit board 17. The first circuit board 16 is electrically connected to the second circuit board 17 via the connection member 18.

[0057] In this embodiment, the second circuit board 17 is stacked on the first circuit board 16 in the sheet 20. In other embodiments, the first circuit board 16 may be stacked on the second circuit board 17.

[0058] 4. Technical Effects of the Embodiment

[0059] When the control circuit 13 is in the sleep mode, the control circuit 13 outputs corresponding first to fourth negative logic signals to the first to fourth drive circuits 9 to 12. Therefore, in the motor drive circuit 1, the standby current of the first to fourth drive circuits 9 to 12 can be reduced.

[0060] When the control circuit 13 enters the sleep mode and outputs the third negative logic signal and the fourth negative logic signal, the switch 14 electrically disconnects the collector of the third bipolar transistor Tr3 of the first drive circuit 9 and the second drive circuit 10 from the reference ground. As a result, the first drive circuit 9 and the second drive circuit 10 apply a high voltage to the gates of the first FET5 and the second FET6, respectively. In this state, the voltage between the respective gates and the respective sources of the first FET5 and the second FET6 is approximately 0 volts, so the first FET5 and the second FET6 are turned off. Thus, it is possible to suppress the through current from flowing through the motor drive circuit 1, more specifically, through the full bridge circuit.

[0061] When the control circuit 13 is not in the sleep mode, the control circuit 13 outputs the corresponding third positive logic signal and / or fourth positive logic signal to the third drive circuit 11 and / or the fourth drive circuit 12. As a result, the switch 14 electrically connects the collector of the third bipolar transistor Tr3 of the first drive circuit 9 and the second drive circuit 10 to the reference ground. In this state, the first FET 5 and the second FET 6 (i) are turned on in response to the first positive logic signal or the second positive logic signal, or (ii) are turned off in response to the first negative logic signal or the second positive logic signal.

[0062] Since the switch 14 is turned on by the third positive logic signal for the third drive circuit 11 or the fourth positive logic signal for the fourth drive circuit 12 , there is no need to provide an additional output port in the control circuit 13 for outputting an additional signal required to turn on the switch 14 .

[0063] The control circuit 13 is mounted on the first circuit board 16, and the first FET5 to the fourth FET8, the first drive circuit 9 to the fourth drive circuit 12, the switch 14, and the first diode 15A and the second diode 15B are mounted on the second circuit board 17. Since the second circuit board 17 is stacked on the first circuit board 16, the area occupied by the first circuit board 16 and the second circuit board 17 on the sheet 20 can be reduced.

[0064] 5. Word correspondence

[0065] In the present embodiment, the first bipolar transistor Tr1 in each of the first drive circuit 9 to the fourth drive circuit 12 corresponds to an example of each of the first bipolar transistor to the fourth bipolar transistor in the appended claims. Each high voltage output from the first drive circuit 9 to the fourth drive circuit 12 corresponds to an example of each of the first high voltage to the fourth high voltage in the appended claims. Each low voltage output from the first drive circuit 9 to the fourth drive circuit 12 corresponds to an example of each of the first low voltage to the fourth low voltage in the appended claims.

[0066] 6. Other Implementation Methods

[0067] In the above embodiment, the switch 14 is connected to the first drive circuit 9 and the second drive circuit 10. However, the present disclosure is not limited thereto. The switch 14 may be connected to the third drive circuit 11 and / or the fourth drive circuit 12 instead of being connected to the first drive circuit 9 and the second drive circuit 10. Alternatively, the switch 14 may be connected to any one or all of the first drive circuit 9 to the fourth drive circuit 12.

[0068] In the above embodiment, the switch 14 includes the Darlington transistor Tr4 . However, the present disclosure is not limited thereto. The switch 14 may include a semiconductor switch other than the Darlington transistor Tr4 .

[0069] In the above-mentioned embodiment, the motor drive circuit involved in the present disclosure is applied to the seat 20 installed in the vehicle. However, the present disclosure is not limited thereto. The present disclosure can also be applied to seats installed in transportation vehicles such as railway vehicles, ships, and aircraft, as well as fixed seats used in theaters or homes.

[0070] In addition, the present disclosure is not limited to the above-mentioned embodiments as long as it conforms to the gist of the disclosure described in the above-mentioned embodiments. Therefore, the present disclosure may be configured by eliminating any of the constituent elements shown in the drawings or the constituent elements described with reference numerals in the above-mentioned embodiments.

Claims

1. A motor drive circuit configured to drive an electric motor for a vehicle seat, the motor drive circuit comprising: First to fourth field effect transistors (FETs), the first to fourth FETs forming a full-bridge circuit, the first to second FETs being high-side switches of the full-bridge circuit, the third and fourth FETs being low-side switches of the full-bridge circuit, the first to fourth FETs being configured to (i) switch to their respective on-states in response to first to fourth low voltages being received by their respective gates, and (ii) switch to their respective off-states in response to first to fourth high voltages being received by their respective gates, wherein the first to fourth high voltages are all higher than the corresponding first to fourth low voltages; The first to fourth drive circuits each include a corresponding first to fourth bipolar transistor, wherein the first to fourth bipolar transistors are configured to: (i) switch to their respective on-states in response to first to fourth positive logic signals being received at their respective bases; and (ii) switch to their respective off-states in response to first to fourth negative logic signals being received at their respective bases. The first to fourth drive circuits are configured to: (i) output the corresponding first to fourth low voltages to the respective gates of the first to fourth FETs in response to the first to fourth bipolar transistors being in their respective on-states; and (ii) output the corresponding first to fourth high voltages to the respective gates of the first to fourth FETs in response to the first to fourth bipolar transistors being in their respective off-states. a control circuit configured to output the corresponding first to fourth positive logic signals or the corresponding first to fourth negative logic signals to the respective bases of the first to fourth bipolar transistors, and configured to output the corresponding first to fourth negative logic signals to the respective bases of the first to fourth bipolar transistors when the control circuit is in a sleep mode; and The switch is configured to operate at least one of the first to fourth drive circuits when the control circuit is in the sleep mode so that the at least one drive circuit outputs at least one of the first to fourth high voltages.

2. The motor drive circuit according to claim 1, wherein: The motor drive circuit has its reference ground (GND), The first to fourth drive circuits include respective output stages connected to the respective gates of the first to fourth FETs. The respective output stages are configured to: (i) output the corresponding first to fourth low voltages in response to the respective output stages being electrically connected to the reference ground; and (ii) output the corresponding first to fourth high voltages in response to the respective output stages being electrically disconnected from the reference ground. The switch is configured to electrically disconnect at least one of the respective output stages from the reference ground when the control circuit is in the sleep mode.

3. The motor drive circuit according to claim 2, wherein: The switch is a semiconductor switch configured to electrically disconnect the at least one of the respective output stages from the reference ground by switching to an off state of the semiconductor switch.

4. The motor drive circuit according to any one of claims 1 to 3, wherein: The motor drive circuit has its reference ground (GND), The first FET and the second FET include: (i) a source connected to a positive electrode of a power source of the electric motor; and (ii) a drain connected to the electric motor. The third FET and the fourth FET include: (i) respective sources connected to the electric motor; and (ii) respective drains connected to the reference ground.

5. The motor drive circuit according to any one of claims 1 to 4, characterized in that: The switch is configured to operate the first drive circuit and / or the second drive circuit in response to receiving the third negative logic signal and the fourth negative logic signal so that the first drive circuit and / or the second drive circuit output the corresponding first high voltage and / or the second high voltage.

6. The motor driving circuit according to claim 5, wherein: The motor drive circuit further comprises: a first transmission path configured to transmit the third positive logic signal and the third negative logic signal from the control circuit to the third drive circuit; a second transmission path configured to transmit the fourth positive logic signal and the fourth negative logic signal from the control circuit to the fourth drive circuit; a first diode having (i) a first cathode connected to the switch and (ii) a first anode connected to the first transmission path; and a second diode including (i) a second cathode connected to the switch and (ii) a second anode connected to the second transmission path.

7. The motor drive circuit according to any one of claims 1 to 6, characterized in that: The control circuit is a microcomputer having a first output port to a fourth output port. The first to fourth output ports are configured to output the corresponding first to fourth positive logic signals or the corresponding first to fourth negative logic signals, respectively.

8. The motor drive circuit according to any one of claims 1 to 7, wherein: The motor drive circuit has: a first circuit board, the first circuit board including the control circuit; and A second circuit board (i) is different from the first circuit board and (ii) includes the first to fourth FETs, the first to fourth drive circuits, and the switch.

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