Control method for realizing external synchronization PAL system picture display based on FPGA (Field Programmable Gate Array)

Abstract

The invention relates to a control method for realizing external synchronous PAL system picture display based on an FPGA (Field Programmable Gate Array), and belongs to the technical field of development of logic gate arrays such as aerospace and the like. An EP4CE115F23I7 FPGA is adopted in a processor, a 20M clock 50 is divided into 400KHz to serve as a configuration clock of an I2C interface, meanwhile, a PLL in the FPGA is instantiated to generate a 27M clock to achieve a BT656 encoder protocol, and therefore pixel control information and synchronous blanking control signals of a 7121 chip are generated, and fast and slow indication, direction indication and wide and narrow view field indication of a center vernier of a pod display screen are achieved. According to the invention, an FPGA is used as a master control, and a line-field separation chip EL1883 and an encoder chip SAA7121 are carried to realize external synchronous display control of airborne videos; according to the method, only a small part of registers of the SAA7121 need to be configured, display control logic software is flexibly upgraded to adapt to various picture scenes through a PAL external synchronous display control algorithm of the FPGA, the hardware circuit design cost is low, and both a main control chip and an encoder chip are provided with domestic benchmarking products.

Description

Technical Field

[0001] The present invention belongs to the field of development technology of logic gate arrays in aerospace and the like, and in particular to the field of display control algorithms for airborne pod image videos, and specifically relates to a control method for realizing external synchronous PAL format picture display based on FPGA. Background Art

[0002] The video image display of each onboard device is extremely important for the coordinated work of each device and the command instructions to the operator. The onboard operator determines the next operation instruction based on the background words displayed in the video and the movement of the center cursor block.

[0003] The encoding control of PAL video is divided into two types: internal synchronization (synchronization code) and external synchronization (depending on the line and field synchronization signals HSYNC, VSYNC). The internal synchronization method only needs to provide the encoder chip with a clock and 8-bit pixel data. However, in some airborne display and control situations, since this method does not refer to the synchronization signal of the onboard video source, it causes serious picture jitter and floating, and even makes it impossible to recognize the picture that was originally to be controlled and displayed. Therefore, the external synchronization display and control technology of PAL format is particularly important.

[0004] The traditional PAL external synchronization control solution is generally controlled by DSP, and the video decoding chip SAA7115 and the encoder SAA7121 are configured to work in external synchronization mode to complete the display control of specific pictures. The control process of this solution is complex and lacks flexibility, which poses many challenges to the coordination of software and hardware design. Summary of the invention

[0005] 1. Technical issues to be resolved

[0006] The technical problem to be solved by the present invention is to provide a control method for realizing external synchronous PAL standard picture display based on FPGA.

[0007] (II) Technical solution

[0008] In order to solve the above technical problems, the present invention provides a control method for realizing external synchronization PAL format picture display based on FPGA. The method is a PAL format video display control method based on an image processing main control chip FPGA equipped with a line-field separation chip EL1883 and an image encoder chip to realize external synchronization with an external input CVBS analog source signal. The FPGA is used to complete the configuration of the image encoder chip, the synchronization signal reception and processing of the line-field separation chip, and the implementation of the encoding algorithm. The line-field separation chip EL1883 is used to generate an external synchronization signal, and the image encoder chip adopts SAA7121 to realize DAC conversion of the encoded data.

[0009] Preferably, EL1883 separates the line synchronization control signal H and the field synchronization control signal V from the external input analog source signal CVBS and transmits them to FPGA, which uses them as a reference to implement the encoding algorithm. The EL1883 chip is powered by a single 5V power supply, and the input is the analog source signal CVBS. The timing configuration pin Rset is used to configure the PAL or NTSC format, and the Rf pin is used to perform pre-low-pass filtering on the analog source signal CVBS; EL11883 outputs the line synchronization signal HSYNC, the field synchronization signal VSYNC and the composite video synchronization signal CSYNC; the signal CSYNC is used to compare the phase period with the input analog source signal CVBS. When the phase difference between the two is constant and the period is consistent, it means that EL1883 has successfully separated the external synchronization signal required by the FPGA.

[0010] Preferably, FPGA completes the register configuration of the internal working mode of the image encoding chip SAA7121 by simulating the I2C communication timing. The specific registers that need to be configured include: 0x3A: configure the master-slave mode of the image encoding chip, configured as 13h master mode; 0x5B: for U component gain control, configured as 6Dh; 0x5C: for V component gain control, configured as 9Fh; 0x5D: for black level gain control, configured as 0x10; 0x61: for the image encoding chip output video format, configured as 06h, PAL format; 0x63~0x66: realize subcarrier frequency selection: configured as CBh, 8Ah, 09h, 2Ah; 0x6B: realize RCV port configuration, configured as 00h, the line field signal is output, and the input is not detected.

[0011] Preferably, EL11883 outputs a line synchronization signal HSYNC and a field synchronization signal VSYNC, i.e., external synchronization signals HSYNC and VSYNC, which are used to determine the starting point, break point and end point of the image currently being encoded by the external input analog source signal CVBS. The falling edge H_neg of the line synchronization signal HSYNC generated by EL1883 determines the starting pixel position START_PIXEL for encoding each line, and the time interval ΔT between the falling edge H_neg of HSYNC and the falling edge V_neg of VSYNC determines the even field or odd field of a frame of image currently being encoded.

[0012] Preferably, the encoding algorithm complies with the BT656 protocol, and the FPGA enables SAA7121 to complete reliable reception and achieve the expected encoding effect by issuing a timing consistent with the image encoding protocol, wherein the three variables START_PIXEL, LINE_2ND and LINE_314TH generated by external synchronization HSYNC and VSYNC and processed by the internal logic of the FPGA are used to determine the line start point, field start point, and their respective encoding end points of the encoder, and the image encoder chip SAA7121 is driven by counting in the form of synchronization codes.

[0013] Preferably, the FPGA sequentially provides the configuration data of each register in the SAA7121 via the I2C bus.

[0014] Preferably, the encoder implemented by FPGA, that is, the state machine needs to encode the following states:

[0015] (1) IDLE state: complete pixel row and column pointer initialization, default value initialization of all pixels of the image, SAA7121 configuration, and synchronization processing of HSYNC and VSYNC generated by EL1883;

[0016] (2) WORK state: detect the line coding starting point START_PIXEL, the second line coding mark LINE_2ND, and the line pointer increment trigger condition;

[0017] (3) EAV state: end synchronization code state, including:

[0018] Output even field blanking rear shoulder end synchronization code EAV1 = 8'hB6;

[0019] Output even field data end synchronization code EAV2 = 8'h9D;

[0020] Output even field blanking front shoulder end synchronization code EAV3 = 8'hB6;

[0021] Output odd field blanking after the shoulder synchronization code EAV4 = 8'hF1;

[0022] Output odd field data end synchronization code EAV5 = 8'hDA;

[0023] Output odd field blanking end front shoulder synchronization code EAV6 = 8'hF1;

[0024] (4) VBLANKING state: line blanking state, including:

[0025] Output line blanking area odd pixel position filling code BLANK_ODD = 8'h10;

[0026] Output line blanking area even pixel position filling code BLANK_EVEN = 8'h80;

[0027] (5) SAV state: start synchronization code state, including:

[0028] Even field blanking back shoulder start synchronization code SAV1 = 8'hAB;

[0029] Even field data start synchronization code SAV2 = 8'h80;

[0030] Even field blanking front shoulder start synchronization code SAV3 = 8'hAB;

[0031] Odd field blanking back shoulder start synchronization code SAV4 = 8'hEC;

[0032] Odd field data start synchronization code SAV5 = 8'hC7;

[0033] Odd field blanking front shoulder start synchronization code SAV6 = 8'hEC;

[0034] (6) DATA status: Picture data encoding status, including:

[0035] Chroma component Cb encoding state: EVEN;

[0036] Luminance component Y1 encoding status: Y_DATA1;

[0037] Chroma component Cr encoding status: ODD;

[0038] Luminance component Y2 encoding status: Y_DATA2;

[0039] (7) END state: The picture completes the scanning of 1 frame and 2 fields and then jumps back to the WORK state, continuously refreshing the encoded picture.

[0040] Preferably, when the 27M pixel clock pclk generated by the internal PLL of the FPGA has been locked and the I2C configuration timing of the SAA7121 has been completed, the START_ENCODING flag signal is pulled high to trigger the state machine to work. The specific process is as follows:

[0041] Step 1: The state machine is in the IDLE state, the pixel pointer Pixels = 0, the line pointer Lines = 0, the encoder data state defaults to the blanking end code state EAV, when START_ENCODING = 1, jump to step 2;

[0042] Step 2: The state machine is in the WORK state. When START_PIXEL=1 is detected, the pixel column pointer Pixels is set to 11'd1, and the first pixel data is printed at the same time: 8'hFF. In addition, the second line flag LINE_2ND is detected to be pulled high in the same clock cycle of pclk. If it is not pulled high, it means that the external analog source signal input state is abnormal or the EL1883 analysis is abnormal. At this time, the line pointer remains unchanged in the previous state, and the image encoder chip is driven to give the blanking black level data 8'h10. If LINE_2ND is already pulled high at this time, the line pointer is set to 2; the pixel pointer Pixels is continuously accumulated by 1 at the falling edge of pclk. When the EAV state is (Pixels<=4), the leading code is generated respectively: 8'hff, 8'h00, 8'h00, EAVx. When the pixel pointer Pixels>4, jump to step 3;

[0043] Step 3: The state machine enters the line blanking area. When the pixel pointer satisfies 5<=Pixels<=283, a fill code 8'h10 is generated when the value of the pixel pointer Pixels is an odd number, and a fill code 8'h80 is generated when the value of the pixel pointer Pixels is an even number. When the pixel pointer satisfies Pixels>=284, jump to step 4.

[0044] Step 4: The state machine enters the SAV state, and according to the number of lines currently encoded, enters the even field blanking start SAV1, even field data start SAV2, odd field blanking start SAV4, odd field data start SAV5 states respectively, and uses the method in step 2 to generate the leading code: 8'hff, 8'h00, 8'h00, SAVx. When the pixel pointer Pixels>288, jump to step 5;

[0045] Step 5: The state machine enters the data encoding DATA state. According to the encoding format of YCbCr422, it enters the EVEN state, Y_DATA1 state, ODD state, and Y_DATA2 state in sequence. When it is detected that the pixel pointer Pixels>=1728, the data state is transferred to EAV, the line index Lines is increased by 1, the pixel pointer Pixels is set to 1, and the process jumps to step 2. When it is detected that the current number of encoded lines is 625, the encoding of one frame of the image has been completed, the data state datadone is pulled high, and the process jumps to step 2 to determine whether the line pointer should be maintained or set to 2 in the next cycle.

[0046] The present invention also provides a system for implementing the method.

[0047] The invention also provides an application of the method in airborne pod image video display control.

[0048] (III) Beneficial effects

[0049] The processor of the present invention adopts EP4CE115F23I7 FPGA, and divides the 20M clock by 50 to 400KHz as the configuration clock of the I2C interface. At the same time, the 27M clock is generated by instantiating the internal PLL of the FPGA to implement the encoder protocol of BT656, thereby generating pixel control information and synchronous blanking control signal of the 7121 chip to realize the speed indication, direction indication, and wide and narrow field of view indication of the center cursor of the pod display screen.

[0050] The present invention adopts FPGA as the main control, and is equipped with a line-field separation chip EL1883 and an encoder chip SAA7121 to realize external synchronous display control of airborne video; the method only needs to configure a small part of the registers of SAA7121, and through the PAL external synchronous display control algorithm of FPGA, the display control logic software is flexibly upgraded to adapt to various picture scenes. The hardware circuit design cost is low, and the main control chip and the encoder chip have domestic counterparts. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] Figure 1 It is a scheme block diagram of a control method for realizing external synchronous PAL format picture display based on FPGA of the present invention;

[0052] Figure 2 The present invention is a flow chart of an encoder algorithm of a control method based on realizing external synchronous PAL standard picture display. DETAILED DESCRIPTION

[0053] In order to make the purpose, content and advantages of the present invention more clear, the specific implementation methods of the present invention are further described in detail below in conjunction with the drawings and examples.

[0054] The present invention provides a PAL video display control method based on the ALTERA EP4CE115F23I7 FPGA processor equipped with the line field separation chip EL1883 and the encoder DAC chip SAA7121 to achieve external synchronization with the external input CVBS source, and relates to the image transmission and video analysis field of the pod display control components such as aerospace. The method is applied to the field of aviation airborne display control equipment.

[0055] The present invention provides a control method for realizing external synchronous PAL format picture display based on FPGA. The key technical problems to be solved include: how to realize the hardware circuit configuration of EL1883 line field separation chip; how to realize the I2C protocol configuration of the image encoder chip SAA7121 working mode; how to realize the control algorithm of the encoder in the external synchronous mode based on FPGA. The specific solutions are as follows:

[0056] 1. Design of EL1883 circuit for line-field separation

[0057] The line-field separation is that the EL1883 chip of the present invention separates the line synchronization control signal H and the field synchronization control signal V from the external input CVBS analog source signal and transmits them to FPGA, which uses it as a reference to implement the encoding algorithm. The EL1883 chip is powered by a single 5V power supply, and the input is the analog source signal CVBS (voltage swing range: 0.5-2V). The timing configuration pin Rset (680KΩ ground resistance, accuracy 1%) is used to configure PAL or NTSC format; the Rf pin is used to perform pre-low-pass filtering of the CVBS analog source signal (analog video source); the EL11883 outputs the line synchronization signal HSYNC, the field synchronization signal VSYNC and the composite video synchronization signal CSYNC; the signal CSYNC can be compared with the input analog source signal CVBS for phase cycle. When the phase difference between the two is constant and the cycle is consistent, it proves that the EL1883 circuit has successfully separated the external synchronization signal required by the processor FPGA.

[0058] 2. I2C protocol configuration of image encoder chip SAA7121

[0059] The encoder configuration refers to the FPGA completing the register configuration of the internal working mode of the image encoding chip SAA7121 by simulating the I2C communication timing (baud rate 400K). The specific registers that need to be configured are: 0x3A (configure the master-slave mode of the image encoding chip, configured as: 13h master mode), 0x5B (for U component gain control, configured as: 6Dh), 0x5C (for V component gain control, configured as: 9Fh), 0x5D (for black level gain control, configured as: 0x10), 0x61 (for image encoding chip output video format, configured as 06h, PAL format), 0x63~0x66 (to achieve subcarrier frequency selection: configured as CBh, 8Ah, 09h, 2Ah), 0x6B (to achieve RCV port configuration, configured as 00h, line field signal is output, input is not detected), and the remaining registers are not critical registers and do not need to be configured.

[0060] 3. Externally synchronized BT656 encoder algorithm based on finite state machine

[0061] The EL11883 outputs a line synchronization signal HSYNC and a field synchronization signal VSYNC, namely, external synchronization signals HSYNC and VSYNC, which are mainly used to determine the starting point, discontinuity point and end point of the image currently being encoded by the external input analog source signal CVBS. In the present invention, since the internal D timing characteristics of the EL1883 chip are determined only by the hardware peripheral circuit and cannot be soft-configured, the encoder algorithm state machine should comply with the timing rules of EL1883. The falling edge (H_neg) of the line synchronization signal HSYNC generated by the EL1883 determines the starting pixel position START_PIXEL of each line of encoding, and the time interval ΔT between the falling edge (H_neg) of HSYNC and the falling edge (V_neg) of VSYNC determines the 2nd line (even field) or the 314th line (odd field) of a frame of image currently being encoded.

[0062] The BT656 protocol refers to that FPGA sends out a timing sequence consistent with the image coding protocol, namely the BT656 protocol, so that SAA7121 can complete reliable reception and achieve the expected coding effect. For the encoding of the standard definition PAL format, the resolution is 720*576. Since the YCbCr (4:2:2) encoding format is to be generated, that is, each pixel is described by two brightness components Y1, Y2 and a chrominance component CbCr, that is, a Cb-Y1-Cr-Y2 pixel group signal is generated within four pixel clock pclk cycles; therefore, each row needs to provide 1440 chrominance and brightness information, plus the time occupied by the line blanking, a total of 1728 pclk clock cycles are required to encode a row of images. The present invention uses the variable Pixels to count the sequence number of the pclk in the current row as the column index of the current encoding. The PAL standard refers to the phase inversion line by line: the number of scanning lines is 625, and the interlaced scanning mode is adopted, that is, the scanning of a frame of image is composed of: the number of scanning lines of the even field (288) + the number of scanning lines of the odd field (288) + the number of field blanking lines (49), so the variable Lines (maximum 625) is used as the line index of the current encoding in the present invention. The present invention adopts the three variables of START_PIXEL, LINE_2ND and LINE_314TH generated by the external synchronization HSYNC and VSYNC through the internal logic processing of the FPGA to determine the line starting point, field starting point and their respective encoding end points of the encoder, and at the same time drives the image encoder chip SAA7121 by counting in the form of synchronization code, that is, the idea of ​​"external synchronization shell, internal synchronization core" is adopted in the algorithm.

[0063] Reference Figure 1 , Figure 2 The present invention provides a control method based on realizing external synchronous PAL standard picture display as follows:

[0064] The system processor in this example uses TI's TMS320F28377, which is used to complete the upper computer reception of image and video instructions and the instruction control of the lower computer. The image processing main control chip FPGA uses ALTERA's EP4CE115F23I7 chip to complete the configuration of the image encoder chip, the synchronization signal reception and processing of the line and field chip, and the implementation of the BT656 algorithm (encoding algorithm). The line and field separation chip uses EL1883 to generate external synchronization signals, and the image encoder chip uses SAA7121 to realize DAC conversion of encoded data.

[0065] The I2C bus in this example complies with the Philips standard. It is a simple, bidirectional, two-wire synchronous serial bus SCL and SDA. The SDA data is updated during the low level of SCL, and can be reliably sampled during the high level of SCL. The interface circuit is an open-drain output. Both the master and slave devices have control over the bus. Generally, a write operation needs to go through three stages: (send the destination device address-send the device internal register address-write the register configuration content). Each stage takes 9 I2C clock cycles. In the 9th clock cycle of each stage, the host releases the bus control (high impedance state) and switches to the slave to generate an ACK response. In this example, the FPGA gives the configuration data of certain registers of SAA7121 in turn through the I2C bus.

[0066] The SAA7121 chip in this example is an encoder chip compatible with the BT656 transmission protocol. It integrates an I2C slave interface to obtain the host's configuration data to determine the working mode. The chip integrates 3 10b digital encoding input interfaces, supports RGB format, YUV422 format, YUV444 format, supports 2 analog output DAC interfaces, and supports both NTSC and PAL video image output. The SAA7121 chip output is usually paired with an SGM9111 video driver to enhance the driving capability of the DAC video signal output by the 7121 to the aviation plug connector.

[0067] like Figure 1 As shown, a block diagram of a control method for realizing external synchronous PAL format picture display based on FPGA.

[0068] In this example, the system processor uses the TMS320F28377 of Texas Instruments to complete the upper computer reception of image and video instructions and the display control of the lower computer. The main image processing chip selects the EP4CE115F23I7 chip of ALTERA to complete the configuration of the encoding chip, the reception and processing of the synchronization signal of the line and field chip EL1883, and the implementation of the bt656 algorithm. The line and field separation chip uses EL1883 to generate an external synchronization signal, and the encoder chip uses SAA7121 to implement the DAC conversion of the encoded data and amplify and drive the analog signal through SGM9111, so as to complete the flexible control of the pod display screen by the airborne upper computer device.

[0069] As Figure 2 shown, it is the BT656 algorithm flow chart of the encoder in a control method for realizing the display of an external synchronization PAL format picture based on FPGA according to the present invention.

[0070] Specifically, the states that the state machine of the encoder implemented by FPGA needs to encode are as follows:

[0071] (1) IDLE state: Initialize the pixel row and column pointers, initialize the default values of all pixels in the image, configure SAA7121, and perform synchronization processing on HSYNC and VSYNC generated by EL1883;

[0072] (2) WORK state: Detect the start point of line encoding START_PIXEL, the flag of the second line of encoding LINE_2ND, and the triggering condition for the increment of the line pointer;

[0073] (3) EAV state (pixel pointer Pixels <= 4): End (not started) sync code state, including:

[0074] Output the end sync code EAV1 = 8'hB6 after the even field blanking back porch;

[0075] Output the end sync code EAV2 = 8'h9D for the even field data;

[0076] Output the end sync code EAV3 = 8'hB6 before the even field blanking front porch;

[0077] Output the end sync code EAV4 = 8'hF1 for the odd field blanking back porch;

[0078] Output the end sync code EAV5 = 8'hDA for the odd field data;

[0079] Output the end sync code EAV6 = 8'hF1 before the odd field blanking front porch;

[0080] (4) VBLANKING state (4 < Pixels <= 284 for the pixel pointer): Line blanking state, including:

[0081] The filling code for odd pixel positions in the output line blanking area, BLANK_ODD = 8’h10;

[0082] The filling code for even pixel positions in the output line blanking area, BLANK_EVEN = 8’h80;

[0083] (5) SAV state (284 < Pixels <= 288): The start synchronization code state, including:

[0084] The start synchronization code of the post-porch of the even-field blanking, SAV1 = 8’hAB;

[0085] The start synchronization code of the even-field data, SAV2 = 8’h80;

[0086] The start synchronization code of the pre-porch of the even-field blanking, SAV3 = 8’hAB;

[0087] The start synchronization code of the post-porch of the odd-field blanking, SAV4 = 8’hEC;

[0088] The start synchronization code of the odd-field data, SAV5 = 8’hC7;

[0089] The start synchronization code of the pre-porch of the odd-field blanking, SAV6 = 8’hEC;

[0090] (6) DATA state (288 < Pixels <= 1728): The picture data encoding state, including:

[0091] The encoding state of the chrominance component Cb: EVEN;

[0092] The encoding state of the luminance component Y1: Y_DATA1;

[0093] The encoding state of the chrominance component Cr: ODD;

[0094] The encoding state of the luminance component Y2: Y_DATA2;

[0095] (7) END state: The end state of the scan for 1 frame and 2 fields of the picture, and it will jump back to the WORK state to continuously loop and refresh the encoded picture.

[0096] Reference Figure 2 , when the 27M pixel clock pclk generated by the internal PLL of the FPGA has been locked, and at this time the I2C configuration timing for the SAA7121 has been completed, then raise the START_ENCODING flag signal to trigger the operation of the state machine. The specific process is as follows:

[0097] Step 1: The state machine is in the IDLE state, the pixel pointer Pixels = 0, the line pointer Lines = 0, the encoder data state defaults to the blanking end code state EAV, when START_ENCODING = 1, jump to step 2;

[0098] Step 2: The state machine is in the WORK state. When START_PIXEL=1 is detected, the pixel column pointer Pixels is set to 11'd1, and the first pixel data is printed at the same time: 8'hFF. In addition, the second line flag LINE_2ND is detected to be pulled high in the same clock cycle of pclk. If it is not pulled high, it means that the external analog source signal input state is abnormal or the EL1883 analysis is abnormal. At this time, the line pointer remains unchanged in the previous state, and the image encoder chip is driven to give the blanking black level data 8'h10. If LINE_2ND is already pulled high at this time, the line pointer is set to 2; the pixel pointer Pixels is continuously accumulated by 1 at the falling edge of pclk. When the EAV state is (Pixels<=4), the leading code is generated respectively: 8'hff, 8'h00, 8'h00, EAVx. When the pixel pointer Pixels>4, jump to step 3;

[0099] Step 3: The state machine enters the line blanking area. When the pixel pointer satisfies 5<=Pixels<=283, a fill code 8'h10 is generated when the value of the pixel pointer Pixels is an odd number, and a fill code 8'h80 is generated when the value of the pixel pointer Pixels is an even number. When the pixel pointer satisfies Pixels>=284, jump to step 4.

[0100] Step 4: The state machine enters the SAV state, and according to the number of lines currently encoded, enters the even field blanking start SAV1, even field data start SAV2, odd field blanking start SAV4, odd field data start SAV5 states respectively, and uses a method similar to step 2 to generate the leading code: 8'hff, 8'h00, 8'h00, SAVx. When the pixel pointer Pixels>288, jump to step 5;

[0101] Step 5: The state machine enters the data encoding DATA state. According to the encoding format of YCbCr422, it enters the EVEN state, Y_DATA1 state, ODD state, and Y_DATA2 state in sequence. When it is detected that the pixel pointer Pixels>=1728, the data state is transferred to EAV, the line index Lines is increased by 1, the pixel pointer Pixels is set to 1, and the process jumps to step 2; when it is detected that the current number of encoded lines is 625, the encoding of one frame of the image has been completed, the data state datadone is pulled high, and the process jumps to step 2 to determine whether the line pointer should be maintained or set to 2 in the next cycle; this cycle is repeated continuously to continuously refresh the screen to produce a video effect.

[0102] It can be seen that the control method for realizing external synchronous PAL format picture display based on FPGA proposed in the present invention makes the display control of airborne equipment applicable to more different scenarios, the control is more flexible, the hardware cost is lower, and it can be fully replaced by domestic production.

[0103] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the technical principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A control method for realizing external synchronous PAL standard picture display based on FPGA, characterized in that: The method is a PAL video display control method based on an image processing main control chip FPGA equipped with a line-field separation chip EL1883 and an image encoder chip to realize external synchronization with an external input CVBS analog source signal. The FPGA is used to complete the configuration of the image encoder chip, the synchronization signal reception and processing of the line-field separation chip, and the implementation of the encoding algorithm. The line-field separation chip EL1883 is used to generate an external synchronization signal, and the image encoder chip uses SAA7121 to realize DAC conversion of the encoded data.

2. The control method according to claim 1, characterized in that: EL1883 separates the line synchronization control signal H and the field synchronization control signal V from the external analog source signal CVBS and transmits them to FPGA. FPGA uses it as a reference to implement the encoding algorithm. The EL1883 chip is powered by a single 5V power supply. The input is the analog source signal CVBS. The timing configuration pin Rset is used to configure the PAL or NTSC format, and the Rf pin is used to perform pre-low-pass filtering on the analog source signal CVBS. EL1883 outputs the line synchronization signal HSYNC, the field synchronization signal VSYNC and the composite video synchronization signal CSYNC. The signal CSYNC is used to compare the phase period with the input analog source signal CVBS. When the phase difference between the two is constant and the period is consistent, it means that EL1883 has successfully separated the external synchronization signal required by FPGA.

3. The control method according to claim 1, characterized in that: FPGA completes the register configuration of the internal working mode of the image encoding chip SAA7121 by simulating the I2C communication timing. The specific registers that need to be configured include: 0x3A: configure the master-slave mode of the image encoding chip, configured as 13h master mode; 0x5B: for U component gain control, configured as 6Dh; 0x5C: for V component gain control, configured as 9Fh; 0x5D: for black level gain control, configured as 0x10; 0x61: for the image encoding chip output video format, configured as 06h, PAL format; 0x63~0x66: realize subcarrier frequency selection: configured as CBh, 8Ah, 09h, 2Ah; 0x6B: realize RCV port configuration, configured as 00h, the line field signal is output, and the input is not detected.

4. The control method according to claim 2, characterized in that: EL11883 outputs the line synchronization signal HSYNC and the field synchronization signal VSYNC, namely the external synchronization signals HSYNC and VSYNC, which are used to determine the starting point, break point and end point of the image currently being encoded by the external input analog source signal CVBS. The falling edge H_neg of the line synchronization signal HSYNC generated by EL1883 determines the starting pixel position START_PIXEL for encoding each line, and the time interval ΔT between the falling edge H_neg of HSYNC and the falling edge V_neg of VSYNC determines the even field or odd field of the image currently being encoded.

5. The control method according to claim 1, characterized in that: The encoding algorithm complies with the BT656 protocol. The FPGA sends a timing consistent with the image encoding protocol to enable SAA7121 to complete reliable reception and achieve the expected encoding effect. The three variables START_PIXEL, LINE_2ND and LINE_314TH generated by the external synchronization HSYNC and VSYNC and processed by the internal logic of the FPGA are used to determine the line start point, field start point, and their respective encoding end points of the encoder. At the same time, the image encoder chip SAA7121 is driven by counting by means of synchronization code.

6. The control method according to claim 1, characterized in that: FPGA gives the configuration data of each register in SAA7121 in turn through the I2C bus.

7. The control method according to claim 1, characterized in that: The encoder implemented by FPGA, that is, the state machine needs to encode the following states: (1) IDLE state: complete pixel row and column pointer initialization, default value initialization of all pixels of the image, SAA7121 configuration, and synchronization processing of HSYNC and VSYNC generated by EL1883; (2) WORK state: detect the line coding starting point START_PIXEL, the second line coding mark LINE_2ND, and the line pointer increment trigger condition; (3) EAV state: end synchronization code state, including: Output even field blanking rear shoulder end synchronization code EAV1 = 8'hB6; Output even field data end synchronization code EAV2 = 8'h9D; Output even field blanking front shoulder end synchronization code EAV3 = 8'hB6; Output odd field blanking after the shoulder synchronization code EAV4 = 8'hF1; Output odd field data end synchronization code EAV5 = 8'hDA; Output odd field blanking end front shoulder synchronization code EAV6 = 8'hF1; (4) VBLANKING state: line blanking state, including: Output line blanking area odd pixel position filling code BLANK_ODD = 8'h10; Output line blanking area even pixel position filling code BLANK_EVEN = 8'h80; (5) SAV state: start synchronization code state, including: Even field blanking back shoulder start synchronization code SAV1 = 8'hAB; Even field data start synchronization code SAV2 = 8'h80; Even field blanking front shoulder start synchronization code SAV3 = 8'hAB; Odd field blanking back shoulder start synchronization code SAV4 = 8'hEC; Odd field data start synchronization code SAV5 = 8'hC7; Odd field blanking front shoulder start synchronization code SAV6 = 8'hEC; (6) DATA status: Picture data encoding status, including: Chroma component Cb encoding state: EVEN; Luminance component Y1 encoding status: Y_DATA1; Chroma component Cr encoding status: ODD; Luminance component Y2 encoding status: Y_DATA2; (7) END state: The picture completes the scanning of 1 frame and 2 fields and then jumps back to the WORK state, continuously refreshing the encoded picture.

8. The control method according to claim 7, characterized in that: When the 27M pixel clock pclk generated by the internal PLL of the FPGA has been locked and the I2C configuration timing of the SAA7121 has been completed, the START_ENCODING flag signal is pulled high to trigger the state machine to work. The specific process is as follows: Step 1: The state machine is in the IDLE state, the pixel pointer Pixels = 0, the line pointer Lines = 0, the encoder data state defaults to the blanking end code state EAV, when START_ENCODING = 1, jump to step 2; Step 2: The state machine is in the WORK state. When START_PIXEL=1 is detected, the pixel column pointer Pixels is set to 11'd1, and the first pixel data is printed at the same time: 8'hFF. In addition, the second line flag LINE_2ND is detected to be pulled high in the same clock cycle of pclk. If it is not pulled high, it means that the external analog source signal input state is abnormal or the EL1883 analysis is abnormal. At this time, the line pointer remains unchanged in the previous state, and the image encoder chip is driven to give the blanking black level data 8'h10. If LINE_2ND is already pulled high at this time, the line pointer is set to 2; the pixel pointer Pixels is continuously accumulated by 1 at the falling edge of pclk. When the EAV state is (Pixels<=4), the leading code is generated respectively: 8'hff, 8'h00, 8'h00, EAVx. When the pixel pointer Pixels>4, jump to step 3; Step 3: The state machine enters the line blanking area. When the pixel pointer satisfies 5<=Pixels<=283, a fill code 8'h10 is generated when the value of the pixel pointer Pixels is an odd number, and a fill code 8'h80 is generated when the value of the pixel pointer Pixels is an even number. When the pixel pointer satisfies Pixels>=284, jump to step 4. Step 4: The state machine enters the SAV state, and according to the number of lines currently encoded, enters the even field blanking start SAV1, even field data start SAV2, odd field blanking start SAV4, odd field data start SAV5 states respectively, and uses the method in step 2 to generate the leading code: 8'hff, 8'h00, 8'h00, SAVx. When the pixel pointer Pixels>288, jump to step 5; Step 5: The state machine enters the data encoding DATA state. According to the encoding format of YCbCr422, it enters the EVEN state, Y_DATA1 state, ODD state, and Y_DATA2 state in sequence. When it is detected that the pixel pointer Pixels>=1728, the data state is transferred to EAV, the line index Lines is increased by 1, the pixel pointer Pixels is set to 1, and the process jumps to step 2. When it is detected that the current number of encoded lines is 625, the encoding of one frame of the image has been completed, the data state datadone is pulled high, and the process jumps to step 2 to determine whether the line pointer should be maintained or set to 2 in the next cycle.

9. A system for implementing the method according to any one of claims 1 to 8.

10. Application of the method according to any one of claims 1 to 8 in the control of airborne pod image and video display.

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