Semiconductor structure and manufacturing method thereof

Abstract

The invention provides a semiconductor structure and a manufacturing method thereof, and relates to the technical field of semiconductor manufacturing processes. The method comprises the steps that a substrate is provided, a storage area is formed on the substrate, and a gate structure of a storage transistor is formed in the storage area; forming the source electrode of the storage transistor through a first preparation process for the upper part of the substrate corresponding to the storage region of the source electrode of the storage transistor; a drain contact and a source contact of the memory transistor are formed by a second fabrication process, where the first fabrication process is different from the second fabrication process. The size of the semiconductor structure storage unit can be effectively reduced.

Description

Technical Field

[0001] The present disclosure relates to the technical field of semiconductor manufacturing process, and in particular to a semiconductor structure and a manufacturing method thereof. Background Art

[0002] With the development of semiconductor manufacturing technology, the size of devices is getting smaller and smaller. For the demand of erasing and writing, it is impossible to simply reduce the channel length or width, which will cause a sharp drop in the erasing and writing performance of the storage unit in serious cases.

[0003] Therefore, how to reduce the device size while ensuring the erase and write performance of the storage unit has become a technical problem that needs to be solved urgently. Summary of the invention

[0004] The present disclosure discloses a semiconductor structure and a manufacturing method thereof, which can reduce the size of the device while ensuring the erasing and writing performance of the storage unit.

[0005] In order to achieve the above objectives, the present disclosure provides the following technical solutions:

[0006] According to one aspect of the present disclosure, a method for manufacturing a semiconductor structure is provided, comprising: providing a substrate, on which a storage area is formed, and the storage area forms a gate structure of a storage transistor; for an upper portion of the substrate of the storage area corresponding to the source of the storage transistor, forming the source of the storage transistor by a first preparation process; and forming a drain contact and a source contact of the storage transistor by a second preparation process; wherein the first preparation process is different from the second preparation process.

[0007] In the disclosed embodiment, the upper part of the substrate corresponding to the storage area of ​​the storage transistor source is used to form the source of the storage transistor through a first preparation process; and the upper part of the substrate corresponding to the storage area of ​​the storage transistor drain and drain is used to form the drain contact and source contact of the storage transistor through a second preparation process. In this way, the advantages of both preparation processes can be combined, the area of ​​the storage unit can be effectively reduced, and the erase and write performance of the storage unit will not be affected.

[0008] In one embodiment of the present disclosure, the second preparation process includes a drain preparation process and a self-aligned contact process; the formation of the drain contact and the source contact of the storage transistor by the second preparation process includes: forming the drain of the storage transistor by the drain preparation process; forming a drain contact hole and a source contact hole by the self-aligned contact process; filling a conductive layer in the drain contact hole and the source contact hole to obtain a self-aligned drain contact and a self-aligned source contact of the storage transistor.

[0009] In the embodiment of the present disclosure, a second preparation process is performed on the upper portion of the substrate corresponding to the storage area of ​​the storage transistor drain. The drain of the storage transistor is formed by a drain preparation process, and a drain / source contact hole is formed by a self-aligned contact process. The drain area can be reduced, thereby achieving the purpose of reducing the storage unit area.

[0010] In one embodiment of the present disclosure, the drain of the storage transistor is formed by the drain preparation process, including: forming a first barrier layer on a substrate having a gate structure of the storage transistor formed thereon; performing drain ion implantation and drain annealing processes on the drain region and source region of the storage transistor through the first barrier layer to form the drain of the storage transistor.

[0011] In the embodiment of the present disclosure, by performing drain ion implantation and drain annealing processes on the drain region and source region of the storage transistor, the doping concentration of the source is increased and the contact resistance of the source is reduced.

[0012] In one embodiment of the present disclosure, the formation of the drain contact hole and the source contact hole by the self-aligned contact process includes: forming an interlayer dielectric ILD film layer on a substrate on which the drain of the storage transistor is formed; and performing a self-aligned contact process on the ILD film layer at a preset position to form the drain contact hole and the source contact hole of the storage transistor.

[0013] In the embodiment of the present disclosure, an ILD film layer is formed on a substrate on which a drain of a storage transistor is formed to protect the gate sidewalls, thereby reducing silicon loss between gate structures with small pitches.

[0014] In one embodiment of the present disclosure, the drain contact hole includes a first contact hole and a second contact hole, the first contact hole is located between two adjacent gate structures of the storage transistor, the second contact hole is connected to the first contact hole away from the side of the substrate, and the second contact hole overlaps the two adjacent gate structures, and / or the source contact hole includes a third contact hole and a fourth contact hole, the third contact hole is located between two adjacent gate structures of the storage transistor, the fourth contact hole is connected to the third contact hole away from the side of the substrate, and the fourth contact hole overlaps the two adjacent gate structures.

[0015] In the disclosed embodiment, the drain contact hole and the source contact hole may overlap two adjacent gate structures, thereby reducing the area of ​​the drain contact hole and the source contact hole, thereby achieving the purpose of reducing the area of ​​the storage unit.

[0016] In one embodiment of the present disclosure, a peripheral region is also formed on the substrate, and a gate structure of a peripheral transistor is formed in the peripheral region; wherein, before an interlayer dielectric ILD film layer is formed on the substrate on which the drain of the storage transistor is formed, the method further includes: forming a second barrier layer on the substrate after the drain of the storage transistor is formed; etching the second barrier layer corresponding to the source position and the drain position of the peripheral transistor to form a source region and a drain region of the peripheral transistor; and performing ion implantation on the source region and the drain region of the peripheral transistor to form a source and a drain of the peripheral transistor.

[0017] In the embodiment of the present disclosure, a second barrier layer is formed on the substrate after the drain of the storage transistor is formed, and the source region and the drain region of the peripheral transistor are formed after etching. The source region and the drain region of the peripheral transistor are ion implanted to form the source and the drain of the peripheral transistor. On the one hand, the preparation process of the storage transistor and the peripheral transistor is integrated to shorten the process time. On the other hand, when performing ion implantation, the barrier layers of the peripheral transistor and the storage transistor are the same, which facilitates process control.

[0018] In one embodiment of the present disclosure, the method also includes: etching the ILD film layer corresponding to the source position and the drain position of the peripheral transistor to form a drain contact hole and a source contact hole of the peripheral transistor; etching the ILD film layer corresponding to the gate position of the storage transistor and the gate of the peripheral transistor to form a gate contact hole of the storage transistor and a gate contact hole of the peripheral transistor; filling a conductive layer in the gate contact hole of the storage transistor and the gate contact hole of the peripheral transistor to form a gate contact of the storage transistor and a gate contact of the peripheral transistor.

[0019] In the disclosed embodiment, the drain contact hole and the source contact hole of the storage transistor are formed simultaneously with the drain contact hole and the source contact hole of the peripheral transistor, and the gate contact hole of the storage transistor is formed simultaneously with the gate contact hole of the peripheral transistor. On the one hand, the process time can be shortened. On the other hand, there is a thickness difference between the etching depths of the drain / source and the gate. Using two etchings can reduce the difficulty of process control and improve the yield rate.

[0020] In one embodiment of the present disclosure, the first preparation process includes a self-aligned source process, and the self-aligned source process includes: forming a mask layer on a substrate having a gate structure of the storage transistor; performing self-aligned source etching on the mask layer corresponding to the source of the storage transistor to form a source region of the storage transistor; and performing self-aligned source ion implantation and self-aligned source annealing on the source region of the storage transistor to form a source of the storage transistor.

[0021] In the embodiment of the present disclosure, the source of the storage transistor is formed by a first preparation process on the upper portion of the substrate corresponding to the storage area of ​​the source of the storage transistor, which can reduce the area of ​​the source region, thereby achieving the purpose of reducing the area of ​​the storage unit.

[0022] In one embodiment of the present disclosure, providing a substrate, on which a storage area is formed, and the storage area forms a gate structure of a storage transistor, includes: providing a substrate with a stacked layer formed with a storage transistor; and etching the stacked layer to form the gate structure of the storage transistor.

[0023] In one embodiment of the present disclosure, providing a substrate having a stacked layer of storage transistors includes: forming a tunneling oxide layer, a floating gate layer, an interlayer dielectric layer, a control gate layer and a blocking material layer on the substrate in the storage area.

[0024] In the embodiment of the present disclosure, a barrier material layer is formed on the control gate layer to effectively prevent the drain or source from being short-circuited with the gate.

[0025] In one embodiment of the present disclosure, the etching selectivity of the barrier material layer is greater than the etching selectivity of the first barrier layer.

[0026] In the embodiment of the present disclosure, by selecting a material whose etching selectivity of the blocking material layer is greater than that of the first blocking layer, short circuit between the drain / source and the gate can be effectively prevented.

[0027] In another aspect of the present disclosure, a semiconductor structure is provided, comprising: a substrate having a storage area formed thereon, the storage area having a gate structure of a storage transistor formed thereon; the source of the storage transistor is formed on the substrate in the storage area corresponding to the source of the storage transistor through a first preparation process; the storage transistor also includes a drain contact and a source contact formed through a second preparation process; wherein the first preparation process is different from the second preparation process.

[0028] In one embodiment of the present disclosure, the semiconductor structure also includes: a drain of the storage transistor, formed by a drain preparation process; a drain contact hole and a source contact hole, formed by a self-aligned contact process; and a conductive layer filled in the drain contact hole and the source contact hole to obtain a self-aligned drain contact and a self-aligned source contact of the storage transistor.

[0029] In one embodiment of the present disclosure, the semiconductor structure further includes: a first blocking layer, located on a substrate having a gate structure of the storage transistor formed thereon, so as to perform a drain preparation process on the drain region and source region corresponding to the storage transistor through the first blocking layer to form a drain of the storage transistor.

[0030] In one embodiment of the present disclosure, the semiconductor structure further includes: an ILD film layer located on a substrate on which the drain of the storage transistor is formed; a drain contact hole and a source contact hole of the storage transistor are formed on the ILD film layer corresponding to preset positions through a self-aligned contact process.

[0031] In one embodiment of the present disclosure, the drain contact hole includes a first contact hole and a second contact hole, the first contact hole is located between two adjacent gate structures of the storage transistor, the second contact hole is connected to the first contact hole away from the side of the substrate, and the second contact hole overlaps the two adjacent gate structures; and / or the source contact hole includes a third contact hole and a fourth contact hole, the third contact hole is located between two adjacent gate structures of the storage transistor, the fourth contact hole is connected to the third contact hole away from the side of the substrate, and the fourth contact hole overlaps the two adjacent gate structures.

[0032] In one embodiment of the present disclosure, a peripheral region is also formed on the substrate, and a gate structure of a peripheral transistor is formed in the peripheral region; the semiconductor structure also includes: a second blocking layer, which is located on the substrate after the drain of the storage transistor is formed; a source region and a drain region of the peripheral transistor, which are on the second blocking layer corresponding to the source position and the drain position of the peripheral transistor, and are used to perform ion implantation on the source region and the drain region of the peripheral transistor to form the source and the drain of the peripheral transistor.

[0033] In one embodiment of the present disclosure, the semiconductor structure also includes: a drain contact hole and a source contact hole of the peripheral transistor, which are located in the ILD film layer corresponding to the source position and the drain position of the peripheral transistor; a gate contact hole, which is located in the ILD film layer corresponding to the gate position of the storage transistor and the gate position of the peripheral transistor; and a conductive layer, which is filled in the gate contact hole of the storage transistor and the gate contact hole of the peripheral transistor to form a gate contact of the storage transistor and a gate contact of the peripheral transistor.

[0034] In one embodiment of the present disclosure, the first barrier layer includes a first material layer and a second material layer sequentially formed on the substrate, wherein the first material layer includes a silicon dioxide layer, and the thickness of the first material layer is The second material layer includes a silicon nitride layer, and the thickness of the second material layer is between between.

[0035] In one embodiment of the present disclosure, the second barrier layer comprises a silicon dioxide layer, and the thickness of the second barrier layer is between.

[0036] In one embodiment of the present disclosure, the stacked layers of the storage region include a tunneling oxide layer, a floating gate layer, an interlayer dielectric layer, a control gate layer, and a blocking material layer formed on a substrate of the storage region.

[0037] In one embodiment of the present disclosure, the barrier material layer comprises a silicon nitride layer, the thickness of the silicon nitride layer is between.

[0038] The semiconductor structure and the manufacturing method thereof provided by the embodiments of the present disclosure provide a substrate, a storage area is formed on the substrate, and the storage area forms a gate structure of a storage transistor; the source of the storage transistor is formed by a first preparation process; the drain contact and the source contact of the storage transistor are formed by a second preparation process. The first preparation process is different from the second preparation process, and can effectively reduce the area of ​​the storage unit without affecting the erase and write performance of the storage unit. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 A schematic diagram of a semiconductor structure prepared by SAS in the related art is shown.

[0040] Figure 2 A schematic diagram of a semiconductor structure prepared by SAC in the related art is shown.

[0041] Figure 3 A schematic diagram of a semiconductor structure provided by an embodiment of the present disclosure is shown.

[0042] Figure 4 A flow chart of a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure is shown.

[0043] Figure 5 A cross-sectional view of a substrate having a gate structure of a storage transistor formed in a storage region provided by an embodiment of the present disclosure is shown.

[0044] Figure 6 A cross-sectional view of forming a drain and a source of a storage transistor provided by an embodiment of the present disclosure is shown.

[0045] Figure 7-Figure 8 A cross-sectional view of forming a drain and a source of a peripheral transistor provided by an embodiment of the present disclosure is shown.

[0046] Figures 9 to 13 A schematic diagram of forming contacts of a storage transistor and contacts of a peripheral transistor provided by an embodiment of the present disclosure is shown.

[0047] Figure 14~ Fig. 22 A cross-sectional view of a gate structure for forming a storage transistor and a peripheral transistor provided by an embodiment of the present disclosure is shown, wherein: Fig.14a A cross-sectional view of a substrate provided by an embodiment of the present disclosure and having a field oxide layer and a silicon nitride layer formed thereon is shown; Fig.14b A cross-sectional view of a substrate for forming shallow trench isolation according to an embodiment of the present disclosure is shown.

[0048] The numbers in the figure are as follows:

[0049] 110, gate structure; 120, source; 130, drain;

[0050] 111, tunneling oxide layer; 112, floating gate layer; 113, interlayer dielectric layer; 114, control gate layer; 115, barrier material layer;

[0051] 411, storage area; 4111, source area of ​​storage transistor; 4112, drain area of ​​storage transistor; 4113, drain contact hole of storage transistor; 4114, gate contact hole of storage transistor; 412, peripheral area; 4121, drain area of ​​peripheral transistor; 4122, drain contact hole of peripheral transistor; 4123, gate contact hole of peripheral transistor;

[0052] 510, first barrier layer; 511, first material layer; 512, second material layer; 513, second barrier layer; 514, ILD film layer;

[0053] 610, conductive layer; 611, contact;

[0054] 711, field oxide layer; 712, silicon nitride layer; 713, shallow channel oxide layer; 714, field oxide layer boss; 715, groove. DETAILED DESCRIPTION

[0055] Typical embodiments that embody the features and advantages of the present disclosure will be described in detail in the following description. It should be understood that the present disclosure can have various changes in different embodiments without departing from the scope of the present disclosure, and the descriptions and drawings therein are essentially for illustrative purposes rather than for limiting the present disclosure.

[0056] In the following description of different exemplary embodiments of the present disclosure, reference is made to the accompanying drawings, which form a part of the present disclosure and in which different exemplary structures, systems and steps that can implement multiple aspects of the present disclosure are shown by way of example. It should be understood that other specific schemes of components, structures, exemplary devices, systems and steps can be used, and structural and functional modifications can be made without departing from the scope of the present disclosure. Moreover, although the terms "above", "between", "within", etc. may be used in this specification to describe different exemplary features and elements of the present disclosure, these terms are used herein only for convenience, such as according to the direction of the examples in the accompanying drawings. Nothing in this specification should be construed as requiring a specific three-dimensional orientation of the structure to fall within the scope of the present disclosure.

[0057] In the related art, the non-volatile memory adopts a planar floating gate process, which is mainly implemented through a self-aligned source (SAS) process and a self-aligned contact (SAC) process.

[0058] The SAS process refers to the use of ion implantation (IMP) at the source end of the storage unit, and the source end is led out through the contact point (CT) at the SAS pick-up. Figure 1 As shown, in the semiconductor structure prepared by the SAS process, a plurality of memory cells are included, and the plurality of memory cells are arranged in a row / column array. Each memory cell includes a gate structure, a source and a drain, wherein the pick-up of the SAS is led out through the CT, and the drain of each memory cell is led out separately through the CT. However, the drain terminal size of the semiconductor structure prepared by the SAS process is large, resulting in a large area of ​​a single memory cell.

[0059] SAC process refers to the CT self-alignment process, such as Figure 2 As shown, the sources of multiple memory cells are electrically connected through a conductive layer to achieve a common source, and the drain of the SAC process is led out separately, and the drain contact is overlapped on the adjacent gate structures on both sides, so that the size of the drain contact point can be made small, and the size of the drain terminal can be made small. However, in the related art, the SAC process usually uses the same process to prepare the drain terminal and the source terminal, that is, both are prepared at the same time as a symmetrical structure, which will cause the size of the source terminal to be larger than that of the SAS process.

[0060] In order to solve the problem in the related art that the drain terminal size prepared by the SAS process is large, resulting in a large area of ​​a single memory cell, or the source terminal size is large relative to the SAS process by the SAC process, resulting in an increase in the area of ​​a single memory cell. Figure 3 As shown, the present disclosure combines the SAS process and the SAC process, the source terminal adopts the SAS process, and the drain CT and SASCT adopt the SAC process, so as to minimize the area of ​​the memory cell.

[0061] Based on this, the present disclosure provides a semiconductor structure and a manufacturing method thereof, providing a substrate, on which a storage area is formed, and the storage area forms a gate structure of a storage transistor; a first preparation process is performed on the upper part of the substrate corresponding to the storage area of ​​the source of the storage transistor to form the source of the storage transistor; a drain contact and a source contact of the storage transistor are formed by a second preparation process. The first preparation process is different from the second preparation process, and can effectively reduce the area of ​​the storage unit without affecting the erase and write performance of the storage unit.

[0062] In order to facilitate an overall understanding of the technical solution provided by the embodiment of the present disclosure, the manufacturing method of the semiconductor structure provided by the embodiment of the present disclosure is first described below.

[0063] Figure 4 A flow chart of a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure is shown. Figure 4 As shown, a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure includes:

[0064] S401, providing a substrate, a storage area formed on the substrate, and a gate structure of a storage transistor formed in the storage area.

[0065] like Figure 5 As shown, a storage region 411 and a peripheral region 412 are formed on a substrate 410. The gate structure 110 of a storage transistor formed in the storage region 411 may be a floating gate structure.

[0066] In a possible implementation, the floating gate structure preparation process includes a stacking layer preparation process and a stacking layer etching process.

[0067] In a possible implementation, the floating gate structure is obtained by the following method: S401A providing a substrate 410 having a stacked layer of storage transistors; and

[0068] S401B etches the stacked layer to form a gate structure 110 of the storage transistor.

[0069] In a possible implementation, a tunneling oxide layer 111, a floating gate layer 112, an interlayer dielectric layer 113, a control gate layer 114, and a barrier material layer 115 are sequentially formed from bottom to top on the substrate 410 of the storage area 411. It should be noted that other layers may be included between any two layers, which are not listed here one by one. At the same time, the order of the aforementioned layers may also be adaptively adjusted according to the needs of the process, and these adjustments should also be included in the protection scope of the claims of the present disclosure.

[0070] The tunneling oxide layer 111 is the field oxide layer 711 formed on the substrate 410 when preparing the field oxide layer boss 714, and is indicated by reference numeral 111 in the floating gate structure; Fig.17 As shown, when preparing the field oxide boss 714, it is indicated by the reference numeral 711; the tunnel oxide layer 111 and the field oxide layer 711 are the same layer, but are given different names in different manufacturing processes.

[0071] The tunnel oxide layer 111 may be formed by chemical vapor deposition or physical vapor deposition, or by other thin film preparation processes, which is not specifically limited in the present disclosure.

[0072] In a possible implementation, the material of the tunneling oxide layer 111 may be an oxide layer, such as a silicon dioxide layer, or a high-K dielectric material layer, or may be formed of other materials, which are not listed here one by one.

[0073] Those skilled in the art will appreciate that the aforementioned process can be simplified as needed to omit one or more steps, or to omit a portion of a step, and the embodiments of the present disclosure do not limit this. Of course, the field oxide layer boss can also be manufactured using other feasible processes or processes, and the embodiments of the present disclosure do not limit this.

[0074] In the embodiment of the present disclosure, for the convenience of explanation, the following is adopted: Figure 5 This is explained as an example. Figure 5 As shown, a storage region 411 is formed on one side of the substrate 410, and a peripheral region 412 is formed on the other side. The gate structure 110 of the storage transistor formed in the storage region 411 may be a floating gate structure.

[0075] The stacked layer in S401A can be prepared illustratively by the following preparation process:

[0076] like Fig.18 As shown, a floating gate layer 112 is formed on the tunneling oxide layer 111 ; in one implementation, the floating gate layer 112 may be formed of polysilicon or any appropriate material.

[0077] like Fig.19 As shown, a cell recess oxide etch (CRS) is performed on a position corresponding to the field oxide layer boss 714 in a region corresponding to the storage region 411 to form a recess 715 ; wherein the preparation process of the field oxide layer boss 714 is described in a subsequent example.

[0078] like Fig. 20 As shown, an interlayer dielectric layer 113 is formed on the surface; Fig. 20 As shown, the interlayer dielectric layer 113 covers the floating gate layer 112, the tunnel oxide layer 111, and the bottom and sidewall surfaces of the groove 715. The interlayer dielectric layer 113 may be an insulator, an ONO (Oxide-Nitride-Oxide, silicon dioxide-silicon nitride-silicon dioxide) stacked layer, or other stacked layers with insulating properties.

[0079] like Fig.21 As shown, a control gate layer 114 is formed in the storage region 411 and the peripheral region 412 , and the control gate layer 114 covers the interlayer dielectric layer 113 ; in one implementation, the control gate layer 114 may be formed of polysilicon.

[0080] like Fig. 22 As shown, a barrier material layer 115 is formed in the storage area 411 and the peripheral area 412, and the barrier material layer 115 covers the control gate layer 114 in the storage area 411 and the peripheral area 412; in one implementation, the barrier material layer 115 can be a dielectric material with a large etching selectivity. For example, the barrier material layer 115 can be made of silicon nitride; other dielectric materials with a larger etching selectivity than silicon dioxide can also be selected. In a possible implementation, the thickness of the barrier material layer 115 is about 1000 nm. between.

[0081] Those skilled in the art will appreciate that the manufacturing process of the aforementioned stacked layers can be simplified as needed to omit one or more steps or a portion of a step, and the embodiments of the present disclosure are not limited thereto. Of course, the stacked layers can also be manufactured using other feasible processes or manufacturing processes, and the embodiments of the present disclosure are not limited thereto.

[0082] In one possible implementation, after forming the control gate 114 or the gate layer, the control gate layer 114 of the storage area 411 may be processed by a control gate polysilicon etch back (CG Poly Etch Back, CGEB) process, thereby reducing the polysilicon height of the storage area 411, thereby reducing the overall height of the control gate layer 114 and the floating gate layer 112, and making ILD filling easier.

[0083] It should be noted that Figure 18-Figure 22 The structure shown is for illustration only. The preparation process of the stacked layer in the embodiment of the present disclosure is not limited to the following method. Figure 18-Figure 22 The structure shown in FIG. Figure 18-Figure 22 The preparation process of the stacked layer shown can be implemented separately, or can be applied in S401A in the embodiment of the present disclosure to form the stacked layer in the storage area 411, and the embodiment of the present disclosure is not limited to this.

[0084] S401B etches the stacked layer to form a Figure 5 The gate structure 110 shown, wherein the gate structure 110 of the storage area 411 may be a floating gate structure. The etching process may be wet etching or dry etching. In a possible implementation, the etching of the stacked layer may be exemplarily performed through the following preparation process, including:

[0085] A patterned mask layer is formed on the blocking material layer 115. The pattern on the photolithography mask plate is transferred to the mask layer by a photolithography process to form a patterned mask layer. For example, the mask layer can be formed on the blocking material layer 115 by a spin coating process. The mask layer can be a photoresist. The mask plate shields the mask layer, and the photoresist is exposed and developed to transfer the pattern on the mask plate to the mask layer to obtain a patterned mask layer; Figure 5 As shown, based on the patterned mask layer, the barrier material layer 115 , the control gate layer 114 , the interlayer dielectric layer 113 , and the floating gate layer 112 of the storage area are etched to obtain the floating gate structure of the storage area 411 .

[0086] Based on the patterned mask layer, the barrier material layer 115 and the gate layer in the peripheral region 412 are etched to form the gate structure 110 in the peripheral region 412 .

[0087] At this point, the gate structure 110 in the storage region 411 on the substrate 410 is obtained.

[0088] The stacked layers of the peripheral region 412 include a gate oxide layer, a gate layer, and a barrier material layer stacked in sequence from top to bottom, and the gate oxide layer covers the substrate 410 of the peripheral region 412. In a possible implementation, the gate oxide layer can be formed by a separate process, and its thickness is determined by MOS characteristics; in addition, the gate oxide layer of the peripheral region 412 can also be formed in the same step as the control gate layer 114 of the storage region 411.

[0089] In a possible implementation, the stacked layers in the peripheral region 412 may be prepared by the following steps:

[0090] When the field oxide layer boss 714 is subjected to a CRS process to form a groove 715, as shown in FIG. Fig.19 As shown, only the field oxide layer boss 714 of the storage area 411 is subjected to the CRS process; at this time, the film layer of the peripheral area 412 has a flat surface; Fig. 20 As shown, an interlayer dielectric layer 113 is formed in the peripheral region 412, and the interlayer dielectric layer 113 covers the floating gate layer 112 and the field oxide layer boss 714 in the peripheral region 412; Fig.21 As shown, the interlayer dielectric layer 113, the floating gate layer 112 and the field oxide layer boss 714 of the peripheral region 412 are etched using a photomask to form a gate oxide layer of the peripheral region 412, and a gate layer is formed on the gate oxide layer of the peripheral region 412; Fig. 22 As shown, a barrier material layer 115 is formed on the gate layer to obtain a stacked layer in the peripheral region 412 .

[0091] It should be noted that the stacked layers of the storage area 411 and the stacked layers of the peripheral area 412 can both be formed in the manner described above. Alternatively, the stacked layers of the storage area 411 can be formed in the manner described above, while the peripheral area 412 can be formed in other manners. Alternatively, the stacked layers of the storage area 411 can be formed in other manners, while the peripheral area 412 can be formed in the manner described above. The embodiments of the present disclosure are not limited to this.

[0092] In the embodiment of the present disclosure, no matter what processes are used for the stacking layers of the storage area 411 and the stacking layers of the peripheral area 412 respectively, the stacking layers of the storage area 411 and the stacking layers of the peripheral area 412 can be formed together.

[0093] S402 , forming the source of the storage transistor through a first manufacturing process on the upper portion of the substrate in the storage region corresponding to the source of the storage transistor.

[0094] In a possible implementation manner, the first preparation process includes a self-aligned source SAS process.

[0095] The self-aligned source process includes the steps of self-aligned source etching, self-aligned source ion implantation and self-aligned source annealing.

[0096] In one possible implementation, Figure 5 As shown, the SAS process may include:

[0097] A mask layer is formed on a substrate 410 having a gate structure 110 of a storage transistor; self-aligned source etching is performed on the mask layer corresponding to the source of the storage transistor to form a source region 4111 of the storage transistor; self-aligned source ion implantation and self-aligned source annealing are performed on the source region 4111 of the storage transistor to form a source of the storage transistor.

[0098] In a possible implementation, the self-aligned source etching of the mask layer may be performed by a dry etching process or a wet etching process. The mask layer may be a photoresist formed on the substrate 410, and the photoresist corresponding to the source of the storage transistor is exposed and developed, so as to transfer the pattern of the photoresist to the photoresist to form the source region 4111 of the storage transistor, and the patterned photoresist is used as a mask to perform self-aligned source ion implantation on the source region 4111 of the storage transistor, and the mask layer is removed to form the source of the storage transistor.

[0099] The source region 4111 of the storage transistor formed by self-aligned source etching is between the two gate structures 110, and the area of ​​the source region is larger than the area between two adjacent gate structures 110; for example, the source region overlaps half of the gate structure 110, and self-aligned source ion injection is performed on the source region 4111 of the storage transistor through the blocking of the gate structure 110, thereby reducing the size of the source terminal.

[0100] The relevant parameters of the self-aligned source ion implantation and self-aligned source annealing processes can be determined according to actual conditions, and are not specifically limited in the present disclosure.

[0101] It should be noted that Figure 6-Figure 12 The structure shown is for illustration only. The process for forming the source of the storage transistor in the embodiment of the present disclosure is not limited to the process of Figure 6-Figure 12 The structure shown in FIG. Figure 6-Figure 12 The process of preparing the source of the storage transistor shown can be implemented separately or together with S403 in the embodiment of the present disclosure, and the embodiment of the present disclosure is not limited to this.

[0102] S403 , forming a drain contact and a source contact of the storage transistor through a second preparation process; wherein the first preparation process is different from the second preparation process.

[0103] The second preparation process includes a drain preparation process and a self-aligned contact process, wherein the drain preparation process is used to form the drain of the storage transistor, and the self-aligned contact SAC process is used to form the drain contact and source contact of the storage transistor.

[0104] In one possible implementation, the second preparation process may include: performing a drain preparation process on the upper portion of the substrate 410 of the storage area 411 corresponding to the drain of the storage transistor to form the drain of the storage transistor; performing a self-aligned contact process on the substrate 410 of the storage area 411 corresponding to the drain and source of the storage transistor to form a drain contact hole and a source contact hole of the storage transistor; filling the drain contact hole 4113 and the source contact hole with a conductive layer 610 to obtain a contact 611 of the storage transistor, wherein the contact 611 of the storage transistor includes a self-aligned drain contact and a self-aligned source contact.

[0105] The drain preparation process may include the steps of drain etching, drain ion implantation and drain annealing.

[0106] In one possible implementation, reference Figure 6The drain preparation process may include: forming a first barrier layer 510 on a substrate 410 on which a source of a storage transistor is formed; performing drain ion implantation and drain annealing processes on a drain region 4112 and a source region of the storage transistor through the first barrier layer 510 to form a drain of the storage transistor. When ion implantation is performed on the drain region 4112 of the storage transistor, ion implantation is performed on the source region 4111 of the storage transistor simultaneously, thereby increasing the doping concentration of the source and reducing the contact resistance of the source.

[0107] In a possible implementation, the first barrier layer 510 includes a first material layer 511 and a second material layer 512 stacked in sequence from bottom to top. The first material layer 511 may be a silicon dioxide layer or a mixture layer containing other silicon dioxide. The thickness of the first material layer 511 may be 0.0443 W / m2. The second material layer 512 may be a silicon nitride layer or a mixture layer containing silicon nitride. The thickness of the second material layer 512 may be between between.

[0108] In one possible implementation, the SAC process may include: forming an interlayer dielectric (ILD) film layer 514 on a substrate 410 on which a drain of a storage transistor is formed; performing a self-aligned contact process on the ILD film layer 514 at a preset position to form a drain contact hole and a source contact hole of the storage transistor.

[0109] The drain contact hole 4113 of the storage transistor includes a first contact hole and a second contact hole, the first contact hole is located between two adjacent gate structures 110 of the storage transistor, the second contact hole is connected to the first contact hole on the side away from the substrate 410, and the second contact hole is overlapped on the two adjacent gate structures 110; and / or the source contact hole of the storage transistor includes a third contact hole and a fourth contact hole, the third contact hole is located between two adjacent gate structures 110 of the storage transistor, the fourth contact hole is connected to the third contact hole on the side away from the substrate 410, and the fourth contact hole is overlapped on the above-mentioned two adjacent gate structures 110, so that the area defined by the drain contact hole and the source contact hole is larger than the gap between the two adjacent gate structures 110, for example, the drain contact hole and / or the source contact hole are overlapped on half of the gate structure 110, thereby reducing the size of the drain terminal and the source terminal.

[0110] The above-mentioned preset positions are positions of contact holes corresponding to the source and drain of the storage transistor.

[0111] In one possible implementation, Fig.11As shown, the ILD film layer 514 corresponding to the gate of the storage transistor is etched to form a gate contact hole 4114 of the storage transistor. The gate contact hole 4114 penetrates the barrier material layer abc and extends to the control gate layer edf.

[0112] In a possible implementation, the barrier material layer abc may be exemplarily as follows: Fig. 22 The barrier material layer 115 is shown. Similarly, the control gate layer edf may be as shown. Fig. 22 A control gate layer 114 is shown.

[0113] In one possible implementation, Figure 11-Figure 12 As shown, a conductive layer 610 is formed in the drain contact hole 4113 and the source contact hole of the storage transistor and the gate contact hole 4114 of the storage transistor. The conductive layer 610 can be tungsten or other materials.

[0114] In a possible implementation, the ILD film layer 514 may be silicon dioxide, silicon nitride, or other silicides.

[0115] It should be noted that Figure 6-Figure 12 The structure shown is for illustration only. The process for forming the drain contact and the source contact of the storage transistor in the embodiment of the present disclosure is not limited to the process of forming the drain contact and the source contact of the storage transistor in the embodiment of the present disclosure. Figure 6-Figure 12 The structure shown in FIG. Figure 6-Figure 12 The preparation process of forming the drain contact and the source contact of the storage transistor shown can be implemented separately or together with S402 in the embodiment of the present disclosure, and the embodiment of the present disclosure is not limited to this.

[0116] In an embodiment of the present disclosure, a substrate is provided, on which a storage area is formed, and the storage area forms a gate structure of a storage transistor; a first preparation process is performed on an upper portion of the substrate corresponding to the storage area of ​​the storage transistor source to form the source of the storage transistor; a drain contact and a source contact of the storage transistor are formed by a second preparation process, and the first preparation process is different from the second preparation process, and can effectively reduce the area of ​​the storage unit without affecting the erase and write performance of the storage unit.

[0117] Continue to refer Figure 5 A peripheral region 412 is also formed on the substrate 410 , and a gate structure 110 of a peripheral transistor is formed in the peripheral region 412 .

[0118] The preparation process also includes ion implantation of a high-voltage lightly doped region of the peripheral transistor, ion implantation of a low-voltage lightly doped region of the peripheral transistor, and preparation of the source and drain of the peripheral transistor.

[0119] In a possible implementation, after the floating gate structure of the storage area 411 is formed and before the gate structure of the peripheral area 412 is formed, the method may further include: performing ion implantation of a lightly doped drain in the storage area 411. When performing ion implantation of the lightly doped drain in the storage area 411, the stacked layer of the peripheral area 412 is used as a barrier layer of the peripheral area 412, and there is no need to form a photoresist as a barrier layer, thereby saving a layer of a photomask and reducing manufacturing costs.

[0120] In a possible implementation, the process steps of high voltage lightly doped ion implantation of the peripheral transistor are as follows: after etching the gate structure of the peripheral region 412, high voltage lightly doped drain (HVLDD) ion implantation is performed in the peripheral region corresponding to the high voltage transistor. Exemplarily, the high voltage transistor can be a high voltage P-type MOS tube (HVPMOS), or a high voltage N-type MOS tube (HVNMOS), or any other component that can realize high voltage function.

[0121] In a possible implementation, the process of ion implantation of the low voltage lightly doped region of the peripheral transistor is as follows: after forming the source of the storage transistor, ion implantation of the low voltage lightly doped region (LVLDD) is performed in the peripheral region corresponding to the low voltage transistor. Exemplarily, the low voltage transistor can be a low voltage P-type MOS tube (LVPMOS), or a low voltage N-type MOS tube (LVNMOS), or any other component that can realize the low voltage function.

[0122] In a possible implementation, the source and drain of the peripheral transistor are prepared as follows:

[0123] like Figure 7 and Figure 8 As shown, before forming an ILD film layer 514 on the substrate 410 on which the drain of the storage transistor is formed, a second barrier layer 513 is formed on the substrate 410 after the drain of the storage transistor is formed; the second barrier layer 513 corresponding to the source position and the drain position of the peripheral transistor is etched to form a drain region 4121 and a source region of the peripheral transistor; and ion implantation is performed on the drain region 4121 and the source region of the peripheral transistor to form the source and drain of the peripheral transistor.

[0124] In a possible implementation, the second barrier layer 513 may be a silicon dioxide layer or a mixture layer containing other silicon dioxide. The thickness of the second barrier layer 513 is between 100 and 200 nm. between.

[0125] In a possible implementation, the method also includes: etching the ILD film layer 514 corresponding to the source position and the drain position of the peripheral transistor to form a drain contact hole 4122 and a source contact hole of the peripheral transistor; etching the ILD film layer 514 corresponding to the gate position of the storage transistor and the gate position of the peripheral transistor to form a gate contact hole 4114 of the storage transistor and a gate contact hole 4123 of the peripheral transistor; filling the gate contact hole 4114 of the storage transistor and the gate contact hole 4123 of the peripheral transistor with a conductive layer 610 to form a gate contact of the storage transistor and a gate contact of the peripheral transistor.

[0126] In the embodiment of the present disclosure, the order of step S402 and step S403 may be reversed, or step S402 and step S403 may be implemented together. The embodiment of the present disclosure does not limit this. Figure 4 In the example shown, the execution order of the three steps is drawn only for illustrative purposes. Those skilled in the art will understand that this order is merely illustrative and does not limit the scope of protection of the embodiments of the present disclosure.

[0127] In the above embodiment, the first preparation process includes a self-aligned source SAS process, and the second preparation process includes a drain preparation process and a self-aligned contact process, and the embodiment of the present disclosure is described in detail. However, those skilled in the art will understand that the scheme of the embodiment of the present disclosure can be: the first preparation process includes a self-aligned source SAS process, and the second preparation process is not limited; or it can be: the first preparation process is not limited, and the second preparation process includes a drain preparation process and a self-aligned contact process. It should also be noted that in the embodiment of the present disclosure, the source SAS process, the drain preparation process, and the self-aligned contact process are written in the same implementation for the purpose of exemplary description only. However, those skilled in the art will understand that it can be seen from the aforementioned description of the technical details that each of the source SAS process, the drain preparation process, and the self-aligned contact process can exist separately, and writing them together in this application does not limit these processes to be implemented simultaneously. Each of the above-mentioned processes should be considered as an independent technical solution for protection.

[0128] In order to facilitate the understanding of the manufacturing method of the semiconductor structure disclosed in the present invention, it is described below with reference to the accompanying drawings.

[0129] Figure 14 to Fig. 22 ,as well as Figure 5 Schematic diagram showing the simultaneous formation of a gate structure of a storage transistor and a gate structure of a peripheral transistor on a substrate. Figure 5 The structure of is taken as an example to illustrate. Figure 5As shown, a storage region 411 is formed on one side of the substrate 410, and a peripheral region 412 is formed on the other side. The gate structure 110 of the storage transistor formed in the storage region 411 may be a floating gate structure.

[0130] As shown in Figure 14 to Fig.17 As shown, a storage region 411 and a peripheral region 412 are formed on a substrate 410 . Figures 18 to 22 , Figure 5 The process of forming the gate structure 110 of the memory transistor and the gate structure 110 of the peripheral transistor.

[0131] A field oxide layer 711 is formed on the substrate 410, so that the substrate 410 is isolated from a storage area 411 and a peripheral area 412 by the field oxide layer 711, and the storage area 411 and the peripheral area 412 are respectively isolated from two or more active areas; in one implementation, a portion of the upper surface of each field oxide layer 711 is higher than the upper surface of the substrate 410, so as to form Fig.17 The field oxide layer protrusion 714 is shown. As mentioned above, the field oxide layer 711 is also the tunnel oxide layer 111.

[0132] The field oxide layer 711 is usually formed by a shallow trench isolation (STI) process.

[0133] In a possible implementation, the field oxide layer boss 714 can be prepared by the following steps:

[0134] like Fig.14a As shown, a field oxide layer 711 and a silicon nitride layer 712 are sequentially formed on the surface of the substrate 410; Fig.14b As shown, shallow trench etching is performed on the field oxide layer 711, the silicon nitride layer 712 and the substrate 410 using a photomask to form shallow trench isolation; Fig.15 As shown, the bottom and sidewalls of the shallow trench are oxidized, and an oxide layer dielectric is filled in the shallow trench to form a shallow channel oxide layer 713. The shallow channel oxide layer 713 extends into the substrate 410 at a predetermined position to form a shallow channel oxide layer 713. Fig.15 The structure shown; Fig.16 As shown, the shallow channel oxide layer 713 is planarized, and as Fig.17 As shown, the silicon nitride layer 712 is removed to form a field oxide layer boss 714.

[0135] In one possible implementation, reference Figure 3 , in the formation Fig.14b After the shallow trench isolation shown, ion implantation is performed on the inner wall of the shallow trench isolation adjacent to the source of the storage transistor to electrically connect the sources of the storage transistors in the same row, and then the source terminal is led out through the CT at the pick-up of the SAS.

[0136] In the preparation process of the field oxide layer boss 714, since only the silicon nitride layer 712 is removed, the field oxide layer 711 on the substrate 410 between the field oxide layer bosses 714 in the storage area 411 and the peripheral area 412 can be used as the tunneling oxide layer 111 of the floating gate structure, and can also be used as the gate oxide layer of the gate structure of the peripheral transistor. The tunneling oxide layer 111 of the floating gate structure is formed in the process of preparing the field oxide layer 711. Compared with the process of first preparing the field oxide layer and then forming the tunneling oxide layer on the substrate between the field oxide layer bosses, the tunneling oxide layer 111 formed in the present disclosure has better flatness. The above-mentioned field oxide layer 711 can be formed by chemical vapor deposition or physical vapor deposition process, and can also be formed by other thin film preparation processes, which are not specifically limited in the present disclosure.

[0137] In a possible implementation, the material of the field oxide layer 711 may be an oxide such as silicon dioxide, or a high-K dielectric material, or other materials or other dielectric materials, which is not specifically limited in the embodiments of the present disclosure.

[0138] Reference Figures 18 to 22 , Figure 5 The preparation process of the gate structure of the storage transistor and the gate structure of the peripheral transistor is described. Figures 18 to 22 The structure in can be referred to Figure 5 As shown in FIG. 4 , a storage region 411 is formed on one side of the substrate 410 , and a peripheral region 412 is formed on the other side.

[0139] like Fig.18 As shown, a floating gate layer 112 is formed on the tunneling oxide layer 112; wherein the floating gate layer 112 is filled in the groove between adjacent field oxide layer bosses 714; wherein the floating gate layer 112 can be formed of polysilicon exemplarily;

[0140] like Fig.19 As shown, the field oxide layer boss 714 in the storage area 411 is etched to form a recess 715; when the field oxide layer boss 714 is subjected to the CRS process to form a recess, only the field oxide layer boss 714 in the storage area 411 is subjected to the CRS process, and at this time, the film layer in the peripheral area 412 has a flat surface; wherein the field oxide layer boss 714 in the storage area 411 can be etched to form the recess 715 by a recess oxide etch (Cell Recess Oxide Etch, CRS) process;

[0141] like Fig. 20 As shown, in Fig.19An interlayer dielectric layer 113 is formed on the surface of the obtained process product; that is, an interlayer dielectric layer 113 is formed on the surface corresponding to the storage area 411, and an interlayer dielectric layer 113 is formed on the surface of the peripheral area 412. At this time, the interlayer dielectric layer 113 covers the floating gate layer 112, the tunneling oxide layer 111, and the surface of the bottom and sidewall of the groove 715. The interlayer dielectric layer 113 can be an insulator, an ONO (Oxide-Nitride-Oxide, silicon dioxide-silicon nitride-silicon dioxide) stacked layer, or a stacked layer formed by other insulators or other materials. At the same time, an interlayer dielectric layer 113 is also formed on the substrate 410 in the peripheral area 412. The interlayer dielectric layer 113 covers the covering floating gate layer 112 and the field oxide layer boss 714 in the peripheral area 412. The interlayer dielectric layer 113 and the field oxide layer boss 714 in the peripheral area 412 are etched using a photomask to retain the lower half of the tunneling oxide layer 111 in the peripheral area 412.

[0142] like Fig.21 As shown, a control gate layer 114 is formed on the substrate corresponding to the storage area 411, and the control gate layer 114 covers the interlayer dielectric layer 113. The control gate layer 114 can be formed of polysilicon; a gate layer is formed on the gate oxide layer corresponding to the peripheral area 412. In a possible implementation, the gate layer of the peripheral area 412 and the control gate layer 114 of the storage area 411 are formed in the same step.

[0143] like Fig. 22 As shown, a barrier material layer 115 is formed in the storage area 411 and the peripheral area 412. The barrier material layer 115 covers the control gate layer 114 in the storage area 411 and the gate layer in the peripheral area 412. In one implementation, the barrier material layer 115 can be a dielectric material with a large etching ratio. For example, the barrier material layer 115 can be a silicon nitride layer; in one possible implementation, the thickness of the silicon nitride layer is between.

[0144] Those skilled in the art will appreciate that the manufacturing process of the aforementioned stacked layers can be simplified as needed to omit one or more steps or a portion of a step, and the embodiments of the present disclosure are not limited thereto. Of course, the stacked layers can also be manufactured using other feasible processes or manufacturing processes, and the embodiments of the present disclosure are not limited thereto.

[0145] In one possible implementation, after forming the control gate 114 or the gate layer, the control gate 114 of the storage area 411 may be processed by a control gate polysilicon etch back (CG Poly Etch Back, CGEB) process, thereby reducing the polysilicon height of the storage area 411, thereby reducing the overall height of the control gate layer 114 and the floating gate layer 112, and making ILD filling easier.

[0146] like Figure 5 As shown, the stacked layers of the storage area 411 and the peripheral area 412 are etched to form a gate structure 110 of the storage transistor in the storage area 411 and a gate structure 110 of the peripheral transistor in the peripheral area 412; wherein the gate structure 110 of the storage transistor in the storage area 411 may be a floating gate structure. The etching process may be wet etching or dry etching.

[0147] The process of etching the stacked layer is as follows: a patterned mask layer is formed on the blocking material layer 115. The pattern on the photolithography mask template is transferred to the mask layer by a photolithography process to form a patterned mask layer. For example, a mask layer can be formed on the blocking material layer 115 by a spin coating process, and the mask layer can be a photoresist. The mask template shields the mask layer, and the photoresist is exposed and developed to transfer the pattern on the mask template to the mask layer to obtain a patterned mask layer; based on the patterned mask layer, the blocking material layer 115, the control gate layer 114, the interlayer dielectric layer 113, and the floating gate layer 112 of the storage area are etched to obtain a floating gate structure of the storage area, which serves as the gate structure 110 of the storage transistor in the storage area 411.

[0148] After the floating gate structure of the storage area 411 is formed, ion implantation of a lightly doped drain is performed in the storage area 411. When the ion implantation of the lightly doped drain of the storage area 411 is performed, the stacked layer of the peripheral area 412 is used as a barrier layer of the peripheral area 412, and there is no need to form a photoresist as a barrier layer, thereby saving a layer of a photomask and reducing manufacturing costs.

[0149] Based on the patterned mask layer, the barrier material layer 115 and the gate layer in the peripheral region 412 are etched to form the gate structure 110 in the peripheral region 412 .

[0150] After forming the gate structure 110 in the peripheral region 412 , HVLDD ion implantation is performed in the peripheral region corresponding to the high voltage transistor.

[0151] At this point, the gate structure of the storage transistor and the gate structure of the peripheral transistor are obtained.

[0152] Figures 6 to 8 A schematic diagram showing the process of preparing the source and drain of a transistor.

[0153] like Figure 6 As shown, the SAS process is performed on the storage region 411 corresponding to the source of the storage transistor to form the source of the storage transistor.

[0154] The SAS process includes the steps of self-aligned source etching, self-aligned source ion implantation and self-aligned source annealing.

[0155] The SAS process may include:

[0156] like Figure 5 As shown, a mask layer is formed on the substrate after ion implantation, and self-aligned source etching is performed on the mask layer of the storage area corresponding to the source of the storage transistor to form a source region 4111 of the storage transistor; self-aligned source ion implantation and self-aligned source annealing are performed on the above-mentioned source region to form the source of the storage transistor.

[0157] After forming the source of the memory transistor, LVLDD ion implantation is performed in the peripheral region 412 corresponding to the low voltage transistor, and the mask layer is removed.

[0158] refer to Figure 6 , a drain preparation process is performed on the storage region 411 corresponding to the source of the storage transistor to form the drain of the storage transistor. The drain preparation process may include the steps of drain etching, drain-source ion implantation and drain annealing.

[0159] The drain preparation process may include: forming a first barrier layer 510 on the substrate 410 forming the source of the storage transistor, and performing drain ion implantation and drain annealing on the drain region and the source region through the first barrier layer 510 to form the drain of the storage transistor.

[0160] When ion implantation is performed on the drain region 4112 of the storage transistor, ion implantation is performed on the source region 4111 of the storage transistor simultaneously, thereby increasing the doping concentration of the source and reducing the contact resistance of the source.

[0161] Exemplarily, the first barrier layer 510 may include: a first material layer 511 and a second material layer 512 stacked in sequence from bottom to top, wherein the first material layer 511 may be a silicon dioxide layer, and wherein the second material layer 512 may be a silicon nitride layer.

[0162] After forming the drain of the memory transistor, ion implantation is performed on the source and drain of the peripheral region 412 to form the source and drain of the peripheral transistor.

[0163] The ion implantation process for the peripheral region may include: Figure 7 As shown, a second barrier layer 513 is formed on the substrate 411 forming the drain of the storage transistor. Figure 8As shown, the second barrier layer 513 of the peripheral region 412 is etched to form a drain region 4121 and a source region of the peripheral region, and ions are implanted into the drain region 4121 and the source region of the peripheral region to form the source and drain of the peripheral transistor.

[0164] In a possible implementation, the second barrier layer 513 may be a silicon dioxide layer or a mixture layer containing other silicon dioxide. The thickness of the second barrier layer 513 is between 100 and 200 nm. between.

[0165] Figures 9 to 13 Schematic diagram of the process of forming electrical contacts for a transistor.

[0166] In order to protect the gate sidewall, Fig. 9 As shown, after the drain and source regions of the storage transistor and the peripheral transistor are formed, an ILD film layer 514 is formed on the surfaces of the storage region 411 and the peripheral region 412 , and the ILD film layer 514 covers the second barrier layer 513 of the storage region 411 and the peripheral region 412 .

[0167] like Fig.10 As shown, a self-aligned contact process is performed on the source and drain positions of the storage area 411 and the peripheral area 412 to form a drain contact hole 4113 and a source contact hole of the storage transistor, and a drain contact hole 4122 and a source contact hole of the peripheral transistor. The drain contact hole 4113 of the storage transistor and the drain contact hole 4122 of the peripheral transistor extend to the corresponding drain region, and correspondingly, the source contact hole extends to the corresponding source region.

[0168] like Fig.11 As shown, the ILD film layer 514 at the gate positions of the storage area 411 and the peripheral area 412 is etched to form a gate contact hole 4114 of the storage transistor and a gate contact hole 4122 of the peripheral transistor. The gate contact holes penetrate the barrier material layer 115 and extend to the corresponding control gate layer 114.

[0169] like Fig.12 As shown, a conductive layer 610 is formed in the drain contact hole, the source contact hole and the gate contact hole. The conductive layer 610 is made of metal such as tungsten.

[0170] like Fig.13 As shown, a planarization process, such as a chemical mechanical polishing (CMP) process, is performed on the conductive layer 610 to form contacts of the storage transistor and contacts of the peripheral transistor.

[0171] Since the etching depths of the gate and the source and drain are different, the present invention can ensure the reliability of the transistor through two etching processes. The surface of the device is covered with a silicon nitride layer. When the ILD film layer is etched, the silicon nitride layer can play an isolation role and protect the gate sidewall from being affected.

[0172] The present disclosure combines SAS and SAC, the source terminal adopts SAS process, and the contacts of the drain terminal and SAS source adopt SAC process, which can reduce the device area and miniaturize the semiconductor structure. The above scheme has at least one of the following beneficial effects:

[0173] 1. Highly integrated with existing floating gate process technology;

[0174] 2. The process is simple to implement, the storage unit area is further compressed, and the storage efficiency per unit area is higher.

[0175] 3. The layout and wiring are simple.

[0176] Next, the following part of the embodiment of the present disclosure will provide a detailed description of the semiconductor structure.

[0177] Fig.13 FIG. 2 shows a cross-sectional view of a semiconductor structure provided by an embodiment of the present disclosure. Fig.13 As shown, the embodiment of the present disclosure provides a semiconductor structure, including:

[0178] A substrate 410 , on which a storage region 411 is formed, and on which a gate structure 110 of a storage transistor is formed;

[0179] The source of the storage transistor is formed on the substrate 410 in a storage region 411 corresponding to the source of the storage transistor by a first manufacturing process;

[0180] The storage transistor further includes a drain contact and a source contact formed by a second fabrication process; wherein the first fabrication process is different from the second fabrication process.

[0181] In one possible embodiment, the semiconductor structure also includes: a drain of the storage transistor, formed by a drain preparation process; a drain contact hole and a source contact hole, formed by a self-aligned contact process; and a conductive layer filled in the drain contact hole and the source contact hole to obtain a self-aligned drain contact and a self-aligned source contact of the storage transistor.

[0182] In one embodiment of the present disclosure, the semiconductor structure also includes: a first barrier layer, located on a substrate having a gate structure of a storage transistor, so as to perform a drain preparation process on the drain region and source region corresponding to the storage transistor through the first barrier layer to form a drain of the storage transistor.

[0183] In one embodiment of the present disclosure, the semiconductor structure also includes: an ILD film layer located on a substrate on which a drain of a storage transistor is formed; a drain contact hole and a source contact hole of the storage transistor, corresponding to the ILD film layer at a certain position, formed by a self-aligned contact process.

[0184] In one embodiment of the present disclosure, the drain contact hole includes a first contact hole and a second contact hole, the first contact hole is located between two adjacent gate structures of the storage transistor, the second contact hole is connected to the first contact hole on the side away from the substrate, and the second contact hole overlaps the two adjacent gate structures; and / or the source contact hole includes a third contact hole and a fourth contact hole, the third contact hole is located between two adjacent gate structures of the storage transistor, the fourth contact hole is connected to the third contact hole on the side away from the substrate, and the fourth contact hole overlaps the two adjacent gate structures.

[0185] In one embodiment of the present disclosure, a peripheral region is also formed on the substrate, and a gate structure of a peripheral transistor is formed in the peripheral region; the semiconductor structure also includes: a second barrier layer, which is located on the substrate after the drain of the storage transistor is formed; the source region and the drain region of the peripheral transistor, which are on the second barrier layer corresponding to the source position and the drain position of the peripheral transistor, and are used to perform ion implantation on the source region and the drain region of the peripheral transistor to form the source and the drain of the peripheral transistor.

[0186] In one embodiment of the present disclosure, the semiconductor structure also includes: a drain contact hole and a source contact hole of the peripheral transistor, which are located in the ILD film layer corresponding to the source position and the drain position of the peripheral transistor; a gate contact hole, which is located in the ILD film layer corresponding to the gate position of the storage transistor and the gate position of the peripheral transistor; and a conductive layer, which is filled in the gate contact hole of the storage transistor and the gate contact hole of the peripheral transistor to form a gate contact of the storage transistor and a gate contact of the peripheral transistor.

[0187] In one embodiment of the present disclosure, the first barrier layer includes a first material layer and a second material layer sequentially formed on the substrate, wherein the first material layer includes a silicon dioxide layer, and the thickness of the first material layer is The second material layer includes a silicon nitride layer, and the thickness of the second material layer is between.

[0188] In one embodiment of the present disclosure, the second barrier layer includes a silicon dioxide layer, and the thickness of the second barrier layer is between.

[0189] In one embodiment of the present disclosure, the stacked layers of the storage region include a tunneling oxide layer, a floating gate layer, an interlayer dielectric layer, a control gate layer, and a blocking material layer formed on a substrate of the storage region.

[0190] In one embodiment of the present disclosure, the barrier material layer includes a silicon nitride layer, the thickness of the silicon nitride layer is between.

[0191] In a possible implementation, the semiconductor structure may also be prepared into other layer structures according to actual conditions and specific requirements, which is not specifically limited.

[0192] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. The present disclosure is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art that are not disclosed in the present disclosure. The specification and example embodiments are to be considered exemplary only, and the true scope and spirit of the present disclosure are indicated by the appended claims.

[0193] It should be understood that the present disclosure is not limited to the exact structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

Claims

1. A method for manufacturing a semiconductor structure, It is characterized in that include: Providing a substrate, on which a storage region is formed, and the storage region is formed with a gate structure of a storage transistor; Forming the source of the storage transistor by a first preparation process on the upper portion of the substrate in the storage region corresponding to the source of the storage transistor; forming a drain contact and a source contact of the storage transistor by a second fabrication process; Wherein, the first preparation process is different from the second preparation process.

2. The method for manufacturing a semiconductor structure according to claim 1, It is characterized in that The second preparation process includes a drain preparation process and a self-aligned contact process; The forming of the drain contact and the source contact of the storage transistor by the second preparation process comprises: forming a drain of the storage transistor by the drain preparation process; A drain contact hole and a source contact hole are formed by the self-aligned contact process; a conductive layer is filled in the drain contact hole and the source contact hole to obtain a self-aligned drain contact and a self-aligned source contact of the storage transistor.

3. The method for manufacturing a semiconductor structure according to claim 2, It is characterized in that The forming of the drain of the storage transistor by the drain preparation process includes: forming a first barrier layer on the substrate having the gate structure of the memory transistor formed thereon; A drain ion implantation and a drain annealing process are performed on the drain region and the source region of the storage transistor through the first barrier layer to form a drain of the storage transistor.

4. The method for manufacturing a semiconductor structure according to claim 2, It is characterized in that The forming of the drain contact hole and the source contact hole by the self-aligned contact process comprises: forming an interlayer dielectric ILD film layer on the substrate on which the drain of the storage transistor is formed; A self-aligned contact process is performed on the ILD film layer at a preset position to form the drain contact hole and the source contact hole of the storage transistor.

5. The method for manufacturing a semiconductor structure according to claim 4, It is characterized in that The drain contact hole includes a first contact hole and a second contact hole, the first contact hole is located between two adjacent gate structures of the storage transistor, the second contact hole is connected to the first contact hole away from the substrate, and the second contact hole overlaps the two adjacent gate structures; and / or The source contact hole includes a third contact hole and a fourth contact hole, the third contact hole is located between two adjacent gate structures of the storage transistor, the fourth contact hole is connected to the third contact hole away from the side of the substrate, and the fourth contact hole overlaps the two adjacent gate structures.

6. The method for manufacturing a semiconductor structure according to any one of claims 1 to 5, It is characterized in that A peripheral region is also formed on the substrate, and a gate structure of a peripheral transistor is formed in the peripheral region; Wherein, before forming an interlayer dielectric ILD film layer on the substrate on which the drain of the storage transistor is formed, the method further comprises: forming a second barrier layer on the substrate after forming the drain of the storage transistor; Etching the second barrier layer corresponding to the source position and the drain position of the peripheral transistor to form the source region and the drain region of the peripheral transistor; Ion implantation is performed on the source region and the drain region of the peripheral transistor to form the source and the drain of the peripheral transistor.

7. The method for manufacturing a semiconductor structure according to claim 6, It is characterized in that The method further comprises: Etching the ILD film layer corresponding to the source position and the drain position of the peripheral transistor to form a drain contact hole and a source contact hole of the peripheral transistor; Etching the ILD film layer corresponding to the gate position of the storage transistor and the gate position of the peripheral transistor to form a gate contact hole of the storage transistor and a gate contact hole of the peripheral transistor; A conductive layer is filled in the gate contact hole of the memory transistor and the gate contact hole of the peripheral transistor to form a gate contact of the memory transistor and a gate contact of the peripheral transistor.

8. The method for manufacturing a semiconductor structure according to any one of claims 1 to 7, It is characterized in that The first preparation process includes a self-aligned source process, and the self-aligned source process includes: forming a mask layer on the substrate having the gate structure of the storage transistor formed thereon; Performing self-aligned source etching on the mask layer corresponding to the source of the storage transistor to form a source region of the storage transistor; A self-aligned source ion implantation and a self-aligned source annealing are performed on the source region of the storage transistor to form the source of the storage transistor.

9. The method for manufacturing a semiconductor structure according to any one of claims 1 to 8, It is characterized in that The method of providing a substrate, wherein a storage region is formed on the substrate, and a gate structure of a storage transistor is formed in the storage region, including: providing a substrate on which a stacked layer of memory transistors is formed; and The stacked layer is etched to form a gate structure of the storage transistor.

10. The method for manufacturing a semiconductor structure according to claim 9, It is characterized in that The method of providing a substrate having a stacked layer of storage transistors formed thereon comprises: A tunneling oxide layer, a floating gate layer, an interlayer dielectric layer, a control gate layer and a barrier material layer are formed on the substrate of the storage area.

11. The method for manufacturing a semiconductor structure according to claim 10, It is characterized in that The etching selectivity of the barrier material layer is greater than the etching selectivity of the first barrier layer.

12. A semiconductor structure, It is characterized in that include: A substrate having a storage region formed thereon, wherein the storage region has a gate structure of a storage transistor formed therein; The source of the storage transistor is formed on a substrate in a storage region corresponding to the source of the storage transistor by a first manufacturing process; The storage transistor further includes a drain contact and a source contact formed by a second fabrication process; Wherein, the first preparation process is different from the second preparation process.

13. The semiconductor structure according to claim 12, It is characterized in that The semiconductor structure further comprises: The drain of the storage transistor is formed by a drain preparation process; The drain contact hole and the source contact hole are formed by a self-aligned contact process; A conductive layer is filled in the drain contact hole and the source contact hole to obtain a self-aligned drain contact and a self-aligned source contact of the storage transistor.

14. The semiconductor structure according to claim 13, It is characterized in that The semiconductor structure further comprises: The first barrier layer is located on the substrate formed with the gate structure of the storage transistor, so as to form the drain of the storage transistor by performing a drain preparation process corresponding to the drain region and the source region of the storage transistor through the first barrier layer.

15. The semiconductor structure according to claim 13, It is characterized in that The semiconductor structure further comprises: An ILD film layer is located on the substrate on which the drain of the storage transistor is formed; The drain contact hole and the source contact hole of the storage transistor correspond to the ILD film layer at a preset position and are formed by a self-aligned contact process.

16. The semiconductor structure according to claim 15, It is characterized in that The drain contact hole includes a first contact hole and a second contact hole, the first contact hole is located between two adjacent gate structures of the storage transistor, the second contact hole is connected to the first contact hole away from the substrate, and the second contact hole overlaps the two adjacent gate structures; and / or The source contact hole includes a third contact hole and a fourth contact hole, the third contact hole is located between two adjacent gate structures of the storage transistor, the fourth contact hole is connected to the third contact hole away from the side of the substrate, and the fourth contact hole overlaps the two adjacent gate structures.

17. The semiconductor structure according to claim 15, It is characterized in that A peripheral region is also formed on the substrate, and a gate structure of a peripheral transistor is formed in the peripheral region; The semiconductor structure further comprises: A second barrier layer is located on the substrate after forming the drain of the storage transistor; The source region and drain region of the peripheral transistor are on the second barrier layer corresponding to the source position and drain position of the peripheral transistor, and are used to perform ion implantation on the source region and drain region of the peripheral transistor to form the source and drain of the peripheral transistor.

18. The semiconductor structure according to claim 17, It is characterized in that The semiconductor structure further comprises: The drain contact hole and the source contact hole of the peripheral transistor are in the ILD film layer corresponding to the source position and the drain position of the peripheral transistor; A gate contact hole in the ILD film layer corresponding to the gate position of the storage transistor and the gate position of the peripheral transistor; A conductive layer is filled in the gate contact hole of the storage transistor and the gate contact hole of the peripheral transistor to form a gate contact of the storage transistor and a gate contact of the peripheral transistor.

19. The semiconductor structure according to claim 14, It is characterized in that The first barrier layer includes a first material layer and a second material layer sequentially formed on the substrate, wherein the first material layer includes a silicon dioxide layer, and the thickness of the first material layer is The second material layer includes a silicon nitride layer, and the thickness of the second material layer is between between.

20. The semiconductor structure according to claim 17, It is characterized in that The second barrier layer comprises a silicon dioxide layer, and the thickness of the second barrier layer is between.

21. The semiconductor structure according to any one of claims 12 to 20, It is characterized in that The stacked layers of the storage area include a tunneling oxide layer, a floating gate layer, an interlayer dielectric layer, a control gate layer and a blocking material layer formed on a substrate of the storage area.

22. The semiconductor structure according to claim 21, It is characterized in that The barrier material layer includes a silicon nitride layer having a thickness of between.

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