Clock management circuit of vehicle gauge MCU (Microprogrammed Control Unit)

Abstract

The invention relates to the technical field of vehicle gauge MCU clock management circuits, and particularly discloses a vehicle gauge MCU clock management circuit which comprises a chip external OSC module, a chip built-in OSC module, a chip external low-frequency clock module, a multiplexer, a configuration register, a system PLL, a standby PLL and a clock frequency division module. The clock management circuit is a double-PLL double-clock generation path, and the clock generation path can be flexibly switched by adding one PLL, one clock generation path and a partial logic circuit, so that when a clock generated by a certain path is abnormal, a system can be switched to another path to work normally, and when any PLL loses lock, the system can be switched to the other path to work normally. The chip source clock can be automatically switched to the osc clock, the stability of the system is improved by using two same clock channels at the same time, when the output clock of any channel is abnormal, the chip source clock can be switched to the other channel to output the clock, and the whole circuit is simple in structure, low in implementation difficulty and high in robustness.

Description

Technical Field

[0001] The present invention relates to the technical field of automotive MCU clock management circuits, and in particular to a clock management circuit for an automotive MCU. Background Art

[0002] ISO 26262 requires that automotive OEMs and their parts suppliers must follow and document the functional safety development process (from the initial specification development to mass production release) to qualify the vehicle for operation. By definition, functional safety is to significantly reduce the risk of failures, which can be divided into two categories: systematic failures and random failures. The former can only be eliminated by changing the manufacturing process, operating procedures, document design or other related factors. The latter are unpredictable failures that occur during the life cycle of the hardware. According to the probability distribution, these failures may be due to permanent or temporary interference environments, or they may be caused by the performance of internal technologies during the life cycle of the system.

[0003] As one of the important control elements of the car, MCU is classified as a special type element (SEooC, Safety Elements out of Context) in ISO 26262. Its functional safety must strictly follow ISO26262 from the definition to the mass production stage. SEooC requires the use of assumptions (AoU) to reflect the expected safety concepts, requirements and mechanisms to be used. The internal clock architecture of MCU is complex, and the frequency of the clock signal is critical to the correctness and performance of the chip. If the frequency exceeds the specified limit, it may cause performance, protocol and timing failures.

[0004] like Figure 1As shown in FIG. 1 , the general clock management circuit is mainly composed of a clock generation module, a power management module, a PLL and an oscillator. The clock management circuit is responsible for generating clock signals of various frequencies required by various modules (such as CPU, I / O interface, etc.) in the SoC chip, and at the same time completes the management function of these clocks, that is, closing or opening or even changing the working clock of some modules according to application requirements. The input of the clock management circuit is generally the external input clock of the chip or the output clock of the built-in oscillator. The usual design integrates a phase-locked loop (PLL) circuit in the SoC chip to multiply the input clock to obtain the high-frequency clock required inside the chip. The multiplied clock can be divided by different multiples according to the application configuration information to obtain the working clock of each module in the chip. Among them, the power management module has a set of control and status registers for the clock management logic, which are configured by the AHB bus interface. These registers include: clock selection control register, phase-locked loop control register, low power control register and clock gating status register. The chip generates the required clock control signal through these configurable registers. For example, the clock selection control register is used to select the off-chip clock or oscillator clock as the PLL multiplication input; the phase-locked loop multiplication coefficient is configured through the phase-locked loop control register to obtain the PLL multiplication output clock; the output clock of each module and the gate switch are controlled through the low-power control register.

[0005] In the prior art, there is usually a single PLL and a single clock generation path. Once an abnormality occurs in any part of the clock generation path, the generated clock will also be abnormal, and the system can only work under the abnormal clock. Based on this, the present invention proposes a clock management circuit for an automotive MCU to solve the above problem. Summary of the invention

[0006] 1. Technical issues to be resolved

[0007] In view of the shortcomings of the prior art, the present invention provides a clock management circuit for an automotive-grade MCU. The clock management circuit of the automotive-grade MCU is a dual-PLL dual-clock generation path. By adding a PLL, a clock generation path and some logic circuits, the clock generation path can be flexibly switched, so that when the clock generated by a certain path is abnormal, the system can switch to another path to work normally.

[0008] (II) Technical solution

[0009] To achieve the above-mentioned purpose, the present invention provides the following technical solutions: a clock management circuit of an automotive MCU, comprising: an external OSC module for generating the main source clock of the chip; an internal OSC module for generating the backup source clock of the chip; an external low-frequency clock module for generating the secondary backup source clock of the chip; a multiplexer, wherein the multiplexer 1 / 2 is a three-input single-output multiplexer, the multiplexer 3 / 4 is a two-input single-output multiplexer, and the multiplexer 5 / 6 is a four-input single-output multiplexer; a configuration register, which is a register module of the system for configuring control signals; a system PLL, which is a Phase-locked Loop (phase-locked loop), used to amplify the frequency of the output clock of multiplexer 1, generate a high-frequency clock, and then use it as the system clock after clock division; the backup PLL, which is the same PLL as the system PLL, is used to amplify the frequency of the output clock of multiplexer 2, generate a high-frequency clock, and then use it as the peripheral clock after clock division; the clock division module is used to divide the high-frequency clock output by the PLL according to the set division coefficient to obtain a low-frequency clock of a specific frequency required by the system.

[0010] Preferably, the chip external OSC module is an external oscillator (crystal oscillator), the chip external OSC module is input through a chip pin, and the chip internal OSC module is a internal oscillator (crystal oscillator).

[0011] Preferably, the chip external low-frequency clock module is a low-frequency clock signal, which is input through a chip pin.

[0012] The clock flow of the above circuit is as follows:

[0013] S1. After the chip is powered on and reset, the chip source clock defaults to the chip external OSC. At this time, the PLL is not started and the chip is in a low-frequency clock working state;

[0014] S2. After the system has configured the relevant registers (such as PLL configuration parameters, clock division coefficients, multiplexer selection signals, etc.), the system PLL and the standby PLL are turned on;

[0015] S3, after waiting for the two PLLs to lock, the input of the clock division will automatically switch to the high-frequency clock output by the PLL;

[0016] S4, the PLL output clock is then divided to obtain the clock frequency required for normal system operation.

[0017] (III) Beneficial effects

[0018] Compared with the prior art, the present invention provides a clock management circuit for an automotive MCU, which has the following beneficial effects:

[0019] The clock management circuit of the present invention is a dual-PLL dual-clock generation path. By adding a PLL, a clock generation path and some logic circuits, the clock generation path can be flexibly switched, so that when the clock generated by a certain path is abnormal, the system can switch to another path to work normally, thereby realizing that when any PLL loses lock, the chip source clock can be automatically switched to the OSC clock, and two identical clock paths are used to increase the stability of the system. When the output clock of any path is abnormal, it can be switched to the output clock of another path. The entire circuit structure is simple, the implementation difficulty is low, and the entire circuit structure has high robustness. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 A clock management circuit diagram in the prior art;

[0021] Figure 2 This is a clock management circuit diagram of an automotive MCU proposed in the present invention. DETAILED DESCRIPTION

[0022] The following will be combined with the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0023] The existing structure is usually a single PLL single clock generation path. Once any part of the clock generation path is abnormal, the generated clock will also be abnormal, and the system can only work under the abnormal clock. Figure 2 The clock management circuit of the present invention is a dual PLL dual clock generation path. By adding a PLL, a clock generation path and some logic circuits, the clock generation path can be flexibly switched, so that when the clock generated by a certain path is abnormal, the system can switch to another path to work normally.

[0024] Specifically, the clock management circuit of the automotive MCU includes: an external OSC module, which is the main source clock of the chip; an internal OSC module, which is the backup source clock of the chip; an external low-frequency clock module, which is the secondary backup source clock of the chip; a multiplexer, multiplexer 1 / 2 is a three-input single-output multiplexer, multiplexer 3 / 4 is a two-input single-output multiplexer, and multiplexer 5 / 6 is a four-input single-output multiplexer; a configuration register, which is a register module for configuring control signals of the system; a system PLL, which is a Phase-locked Loop (phase-locked loop), used to amplify the frequency of the output clock of multiplexer 1, generate a high-frequency clock, and then use it as the system clock after clock division; the backup PLL, which is the same PLL as the system PLL, is used to amplify the frequency of the output clock of multiplexer 2, generate a high-frequency clock, and then use it as the peripheral clock after clock division; the clock division module is used to divide the high-frequency clock output by the PLL according to the set division coefficient to obtain a low-frequency clock of a specific frequency required by the system.

[0025] Among them, the chip external OSC module is an external oscillator (crystal oscillator), the chip external OSC module is input through the chip pins, the chip built-in OSC module is the built-in oscillator (crystal oscillator), and the chip external low-frequency clock module is a low-frequency clock signal, which is input through the chip pins.

[0026] When working, after the chip is powered on and reset, the chip source clock defaults to the chip external OSC. At this time, the PLL is not started, and the chip is in a low-frequency clock working state. After the system configures the relevant registers (such as PLL configuration parameters, clock division coefficients, multiplexer selection signals, etc.), turn on the system PLL and the backup PLL, and wait for the two PLLs to lock. The input of the clock division will automatically switch to the high-frequency clock output by the PLL. The PLL output clock is then divided to obtain the clock frequency required for normal operation of the system.

[0027] In the scheme of the present invention, three clock source inputs are set: chip external OSC, chip built-in OSC, and chip external low-frequency clock. The function of the clock source is to provide a stable and accurate low-frequency source clock for the chip. The purpose of setting three clock source inputs is to improve the robustness of the system clock, wherein the chip external OSC is the working clock source when the chip is operating normally, and the accuracy requirement is the highest; the chip built-in OSC is a backup clock source, which can be switched to the clock source to allow the chip to continue working when the chip external OSC is abnormal, and the chip external low-frequency clock is a secondary backup clock source, which is used for the extreme case where both the chip external OSC and the chip built-in OSC are abnormal, and the accuracy requirement is the lowest. The three clock source inputs are output to the system PLL and the backup PLL respectively after passing through multiplexer 1 and multiplexer 2 at the same time, as the input clock of the PLL. The output of multiplexer 1 and multiplexer 2 is controlled by the selection signal, and the control signal is configured by the configuration register module. After the chip is powered on and reset, the default value of the control signal is 0 (that is, the output defaults to the chip external OSC).

[0028] In addition, the system PLL and the backup PLL are two identical PLLs, and the function of the PLL is to amplify the clock frequency of the clock source to obtain a high-frequency clock. There are two purposes for setting two PLLs. One is to use a redundant design. When the system PLL is abnormal, the output of the multiplexer 5 can be switched to the backup PLL; the other is that an additional backup PLL can provide more frequency clocks to meet the clock requirements of peripherals.

[0029] Multiplexer 5 and multiplexer 6 are two identical multiplexers with four inputs and one output. The purpose of setting a multiplexer with four inputs and one output is to increase the flexibility of clock selection. The inputs 0, 1, 2, and 3 of multiplexer 5 are respectively the chip external OSC, the system PLL output clock, the chip built-in OSC, and the backup PLL output clock. The inputs 0, 1, 2, and 3 of multiplexer 6 are respectively the chip external OSC, the backup PLL output clock, the chip built-in OSC, and the system PLL output clock. The outputs of multiplexers 5 and 6 are controlled by the selection signal. The control signals are the output signals of multiplexer 3 and multiplexer 4, respectively. After the chip is powered on and reset, the default value of the control signal is 0 (that is, the output defaults to the chip external OSC).

[0030] Multiplexers 3 and 4 are two identical multiplexers with two inputs and one output, and their function is to control the outputs of multiplexers 5 and 6. When the system PLL power switch signal and the standby PLL power switch signal are 1 (at this time, the two PLL power supplies are turned off), the outputs of multiplexers 3 and 4 are the selection signals of multiplexers 5 and 6 configured by the configuration register; when the system PLL power switch signal and the standby PLL power switch signal are 0 (at this time, the two PLL power supplies are turned on), the output of multiplexer 3 is the logical AND of the multiplexer 5 selection signal and the Lock signal output by the system PLL, and the output of multiplexer 4 is the logical AND of the multiplexer 6 selection signal and the Lock signal output by the standby PLL. The purpose of this is that when the PLL output clock is not stable, the lock signal output by the PLL is 2'b00, the result of the logic AND is 2'b00, and the selection signal of multiplexers 5 and 6 is 2'b00 (the system clock is the OSC external to the chip at this time); when the PLL output clock is stable, the lock signal output by the PLL is 2'b11, and the result of the logic AND is the selection signal of multiplexers 5 and 6, and the selection signal of multiplexers 5 and 6 is controlled by the configuration register (the system clock is the PLL output clock at this time). When the PLL is abnormal and lock lose occurs (the PLL output clock is unstable, and the lock signal will change from high level to low level at this time), the selection signal of multiplexers 5 and 6 jumps to 2'b00 (the system clock is the OSC external to the chip at this time).

[0031] The output clocks of multiplexers 5 and 6 are respectively divided by clocks (in actual use, due to different required clock frequencies, they will be divided differently to output clocks of different frequencies, not just one clock division module as shown in the figure) to obtain a clock of a specific frequency required by the system.

[0032] The clock management circuit of the present invention is a dual-PLL dual-clock generation path. By adding a PLL, a clock generation path and some logic circuits, the clock generation path can be flexibly switched, so that when the clock generated by a certain path is abnormal, the system can switch to another path to work normally, thereby realizing that when any PLL loses lock, the chip source clock can be automatically switched to the OSC clock, and two identical clock paths are used to increase the stability of the system. When the output clock of any path is abnormal, it can be switched to the output clock of another path. The entire circuit structure is simple, the implementation difficulty is low, and the entire circuit structure has high robustness.

[0033] Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. A clock management circuit for an automotive MCU, characterized in that: include: The chip is connected to an external OSC module, which is the main source clock for the chip; The chip has a built-in OSC module, which is used to generate the backup source clock of the chip; The chip is connected to a low-frequency clock module, which is the secondary backup source clock of the chip; Multiplexer, the multiplexer 1 / 2 is a multiplexer with three inputs and one output, the multiplexer 3 / 4 is a multiplexer with two inputs and one output, and the multiplexer 5 / 6 is a multiplexer with four inputs and one output; Configuration register, which is a register module of the system for configuring control signals; The system PLL is a phase-locked loop, which is used to amplify the frequency of the output clock of the multiplexer 1 to generate a high-frequency clock, which is then used as the system clock after clock frequency division; A standby PLL, which is the same as the system PLL, is used to amplify the frequency of the output clock of the multiplexer 2 to generate a high-frequency clock, which is then used as the peripheral clock after clock division; The clock frequency division module is used to divide the high-frequency clock output by the PLL according to the set frequency division coefficient to obtain a low-frequency clock of a specific frequency required by the system.

2. The clock management circuit of a vehicle-grade MCU according to claim 1, characterized in that: The chip external OSC module is an external oscillator (crystal oscillator), the chip external OSC module is input through the chip pin, and the chip internal OSC module is a internal oscillator (crystal oscillator).

3. The clock management circuit of a vehicle-grade MCU according to claim 2, characterized in that: The chip external low-frequency clock module is a low-frequency clock signal, which is input through the chip pins.

4. A clock flow of the circuit according to any one of claims 1 to 3, characterized in that: The following steps are involved: S1. After the chip is powered on and reset, the chip source clock defaults to the chip external OSC. At this time, the PLL is not started and the chip is in a low-frequency clock working state; S2. After the system has configured the relevant registers (such as PLL configuration parameters, clock division coefficients, multiplexer selection signals, etc.), the system PLL and the standby PLL are turned on; S3, after waiting for the two PLLs to lock, the input of the clock division will automatically switch to the high-frequency clock output by the PLL; S4, the PLL output clock is then divided to obtain the clock frequency required for normal system operation.

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