Method, system, medium and product for establishing hardware simulation environment by automated script
By automatically parsing and generating configuration files for hardware simulation environments, the problem of complexity and low efficiency of hardware simulation environment construction in large-scale chip design is solved, and the resource utilization rate and verification efficiency are improved.
Patent Information
- Application Number
- CN202411160857.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-22
- Publication Date
- 2024-12-27
AI Technical Summary
In large-scale chip design, the construction process of the hardware simulation environment is complex and prone to errors, resulting in waste of resources and inefficient verification, and it is difficult for the existing technology to effectively simplify this process.
Read and parse configuration information statistics data sets through automated scripts, generate configuration files required for hardware simulation environments, reduce manual errors and resource waste, and improve construction efficiency.
It simplifies the construction process of hardware simulation environment, improves the efficiency of chip verification, reduces confusion errors and resource waste, and is suitable for verification of large-scale chips such as billions to tens of billions of doors.
Smart Images
Figure CN119203868A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of chip verification technology, and in particular to a method, system, medium and product for automatically scripting a hardware simulation environment. Background Art
[0002] With the development of ultra-large-scale integrated circuits, the scale of chips is getting larger and larger, especially AI smart chips, and the chip design even reaches tens of billions of ASIC equivalent gates, which brings huge challenges to system verification. The reason is that after the chip design is completed and the tape-out is completed, no modifications can be made, and the chip product cycle is limited, so verification work cannot be carried out for a long time. Therefore, effective and complete verification work before tape-out is extremely necessary for chip development. The huge design scale has caused the time consumed by software simulation to be unbearable, and the FPGA platform also has problems such as split resources and difficult debugging. Hardware simulation accelerators combine the advantages of software simulation and hardware simulation, have flexible debugging, and are widely used in current chip verification.
[0003] Building a complex hardware simulation debugging environment usually requires a complex configuration process, which is a time-consuming and error-prone process. When using a hardware simulation accelerator for chip verification, it takes more than 20 hours to compile a design with billions of gates. A day has passed from the completion of compilation to the discovery of an information configuration error during the test run. Large designs have hundreds or dozens of signals configured, and the probability of confusion and error is extremely high when viewed in different files, resulting in a significant increase in the error rate of building a hardware simulation environment. The reason is that the configuration file is the foundation of building a hardware simulation environment. In the past, most hardware simulation environments were built by directly configuring them in various files. This method is feasible in small chips, with fast compilation speed and convenient error detection, but it is the key to getting stuck in designs with billions to tens of billions of gates. Summary of the invention
[0004] Technical problem to be solved by the present invention: In view of the above-mentioned problems in the prior art, a method, system, medium and product for building a hardware simulation environment with an automated script are provided. The present invention aims to simplify the process of building a hardware simulation environment for chip verification of large-scale chips with tens to hundreds of billions of gates, increase resource utilization, avoid time spent on repeated environment building due to confusion errors, and improve the efficiency of chip verification.
[0005] In order to solve the above technical problems, the technical solution adopted by the present invention is: A method for automatically scripting a hardware simulation environment comprises the following steps: S1, reading the configuration information statistical data set of the verified design DUT through an automated script; S2, identifying the information in each data subset in the configuration information statistical data set and parsing the corresponding variables through an automated script, thereby obtaining a variable group corresponding to each data subset in the information statistical data table; S3, generating configuration information for the variable groups corresponding to the data subsets according to the format of the configuration files required by the hardware simulation environment and writing the configuration information into various configuration files required by the hardware simulation environment.
[0006] Optionally, each data subset in the configuration information statistical data set includes a clock information configuration table, and the fields in the clock information configuration table include: actual clock, actual frequency, hard simulation frequency, identification and hardware clock. Before step S1, it includes sorting out the clock information for the verified design DUT and generating a clock information configuration table: collecting information on all clock signals in the verified design DUT, the information on the clock signals includes the actual clock, actual frequency and identification; allocating hardware clocks to the actual clocks, and merging actual clocks with the same actual frequency into the same hardware clock using the same hard simulation frequency, and merging actual clocks with modifiable frequencies into the same hardware clock using the same hard simulation frequency, so that the final allocated hardware clocks are less than the maximum number of clock generator configurations supported by the hardware simulation environment; generating a clock information configuration table based on the information of each actual clock and the hardware clocks allocated to the actual clocks and their hard simulation frequencies.
[0007] Optionally, each data subset in the configuration information statistical data set includes a reset information configuration table, and the fields in the reset information configuration table include: reset signal, reset value, flag, and reset start time; before step S1, the reset logic information is sorted out for the verified design DUT and a reset information configuration table is generated; in step S2, when the information in each data subset in the configuration information statistical data set is identified by an automated script and the corresponding variables are parsed, including for the reset logic that generates the same reset signal, the multiplexing reset logic is set by the assignment assign in the code to reduce the resource configuration of the additional reset logic.
[0008] Optionally, each data subset in the configuration information statistical data set includes a mandatory information configuration table, and the fields in the mandatory information configuration table include: signal name, type, value / correspondence and identifier, the signal name is the name of the mandatory signal, the type is the type of the mandatory signal, the value / correspondence records the value or correspondence of the mandatory signal and is allowed to be empty, and the identifier is noted with the required conditions for the mandatory signal; in step S2, when the information in each data subset in the configuration information statistical data set is identified by an automated script and the corresponding variables are parsed, the mandatory signal for which the required conditions are not met is not processed forcibly to save compilation resources.
[0009] Optionally, each data subset in the configuration information statistical data set includes a configuration component information configuration table, and the fields in the configuration component information configuration table include: module name, number and identifier, the module name is the name of the configuration component, the number is the number of configuration components, and the identifier is a note related to the number of configuration components; in step S2, when the information in each data subset in the configuration information statistical data set is respectively identified by an automated script and the corresponding variables are parsed, it includes reducing the number of configuration components used according to the minimum number of module names identified by the identifier to save compilation resources.
[0010] Optionally, each data subset in the configuration information statistical data set includes a top-level information configuration table, and the fields in the top-level information configuration table include: type and name / path, wherein type is the type of the top-level information, and name / path is the name or path of the top-level information. The top-level information configuration table is also used for the hardware simulation environment to reference the name / path of the top-level information when re-executing compilation to prevent input errors of the top-level information.
[0011] Optionally, the configuration information statistical data set in step S1 is an Excel file, each data subset in the configuration information statistical data set refers to each worksheet sheet in the Excel file, and the automation script is a Python script.
[0012] In addition, the present invention also provides a system for building a hardware simulation environment using an automated script, comprising a microprocessor and a memory connected to each other, wherein the microprocessor is programmed or configured to execute the method for building a hardware simulation environment using an automated script.
[0013] In addition, the present invention also provides a computer-readable storage medium, in which a computer program or instruction is stored. The computer program or instruction is programmed or configured to execute the method of building a hardware simulation environment by an automated script through a processor.
[0014] In addition, the present invention also provides a computer program product, including a computer program or instructions, which are programmed or configured to execute the method of building a hardware simulation environment by using an automated script through a processor.
[0015] Compared with the prior art, the present invention mainly has the following advantages: the present invention includes reading the configuration information statistical data set of the verified design DUT through an automated script, identifying the information in each data subset in the configuration information statistical data set and parsing the corresponding variables through the automated script, thereby obtaining the variable group corresponding to each data subset in the information statistical data table, generating configuration information for the variable group corresponding to each data subset in the format of the configuration file required by the hardware simulation environment and writing it into various configuration files required by the hardware simulation environment, thereby realizing chip verification for large-scale chips with tens of billions to hundreds of billions of gates to simplify the process of building the hardware simulation environment, increase resource utilization, avoid time consumed in repeatedly building the environment due to confusion errors, and improve the efficiency of chip verification. BRIEF DESCRIPTION OF THE DRAWINGS
[0016] Figure 1 Schematic diagram of the basic flow of the method of the embodiment of the present invention.
[0017] Figure 2 Schematic diagram of the principle of the method of the embodiment of the present invention.
[0018] Figure 3 It is a schematic diagram of compilation environment configuration information in an embodiment of the present invention.
[0019] Figure 4 This is a clock information configuration table in an embodiment of the present invention.
[0020] Figure 5 This is a reset information configuration table in an embodiment of the present invention.
[0021] Figure 6 This is a mandatory information configuration table in the embodiment of the present invention.
[0022] Figure 7 This is a component information configuration table in an embodiment of the present invention.
[0023] Figure 8 This is a top-level information configuration table in an embodiment of the present invention. DETAILED DESCRIPTION
[0024] The present invention aims to clearly organize configuration file information through a configuration information statistical data set, and at the same time fill the information into the configuration file through an automated script rather than manually, thereby greatly avoiding the possibility of manual and confusing errors and providing a guarantee for teamwork to build an environment. The present invention will be further described in detail below with reference to examples.
[0025] like Figure 1 As shown, the method for automating the scripting of the hardware simulation environment in this embodiment includes the following steps: S1, reading the configuration information statistical data set of the verified design DUT through an automated script; S2, identifying the information in each data subset in the configuration information statistical data set and parsing the corresponding variables through an automated script, thereby obtaining a variable group corresponding to each data subset in the information statistical data table; S3, generating configuration information for the variable groups corresponding to the data subsets according to the format of the configuration files required by the hardware simulation environment and writing the configuration information into various configuration files required by the hardware simulation environment.
[0026] As an optional implementation, Figure 2 As shown, the configuration information statistics data set in step S1 of this embodiment is an Excel file, and each data subset in the configuration information statistics data set refers to each worksheet sheet in the Excel file, and the automation script is a Python script. The configuration information is clearly organized through Excel, and the environment is built through Python script recognition. First, the required configuration information statistics are written into an Excel table. Excel can clearly display the configuration information, thereby avoiding the problem of searching in different files or docking errors between programmers. Then, the information in Excel is recognized by the Python script, and the data information is parsed and written into the configuration file (the format includes files with suffix formats such as *.tcl, *.file, *.v and *.c), thereby avoiding manual input errors or errors caused by confusion. In addition, the configuration information statistics data set can also be a relational database, other types of files or a collection of files (such as CSV, XML or JSON, etc.) as needed, and the automation script can also be an automation script program constructed using other types of scripting languages as needed.
[0027] In ultra-large-scale integrated designs, the clock structures used are becoming more and more complex, the reset control logic is gradually increasing, and the number of pin (PAD) signals that need to be controlled is increasing day by day. These signals play a key role in configuring the hardware simulation compilation environment. In order to maximize the resource utilization of the hardware simulator, when setting up the compilation environment, it is necessary to clarify the detailed structure of the DUT and allocate the best configuration file for the compilation. The compilation environment configuration file information is as follows: Figure 3As shown in the figure, the compilation environment configuration file includes: configuration file (Config File), configuration tcl script (Config.tcl), probe tcl script (Probe.tcl), hardware configuration top-level file (Hw_top.v), etc. In the compilation phase, the construction of the image file (Image File) is completed after analyzing RTL (Register Transfer Level), synthesis (Synthesis), layout and routing (Place and Route). In the compilation process, the configuration file (config file) is first completed. The file contains top-level information (top), design files (RTLfilelist), DW (DesignWare) library, memory (mem) and configuration-related tcl scripts, etc. The top-level information points to the hardware configuration top-level file (Hw_top). After the configuration information is entered, the tool automatically completes the subsequent analysis, synthesis, layout and routing, and finally completes the compilation. These configuration information usually require team cooperation and manual writing during the analysis and sorting process, which is very easy to cause confusion and errors.
[0028] In this embodiment, by counting the configuration information, i.e., clock, reset and other information, the DUT (Device Under Test) is accurately analyzed, and combined with the hardware resource situation, the DUT information and the information required by the final hardware simulation environment are written into Excel to achieve clear and clear operations. For example, multiple clocks are analyzed, some clocks are merged, and finally the situation of being realized in the hardware simulation environment is counted.
[0029] like Figure 4As shown, each data subset in the configuration information statistical data set of this embodiment includes a clock information configuration table, and the fields in the clock information configuration table include: actual clock (name), actual frequency (actualfrequency), hard emulation frequency (HW frequency), mark (note) and hardware clock (hw_clk). Before step S1, it includes arranging clock information for the verified design DUT and generating a clock information configuration table: collecting information of all clock signals in the verified design DUT, the information of the clock signal includes actual clock, actual frequency and mark; allocating hardware clocks to actual clocks, and merging actual clocks with the same actual frequency into the same hardware clock with the same hard emulation frequency, and merging actual clocks with modifiable frequencies into the same hardware clock with the same hard emulation frequency, so that the hardware clocks finally allocated are less than the maximum number of clock generator configurations supported by the hardware simulation environment; generating a clock information configuration table according to the information of each actual clock and the hardware clocks allocated to the actual clocks and their hard emulation frequencies. The current processing method is usually to merge clocks with the same clock frequency. This method not only merges clocks with the same clock frequency, but also analyzes the design function and merges clocks with modifiable frequencies, so as to reduce the number of clocks while ensuring the design function. The clock with modifiable frequency has a unique design. Generally, it is necessary to ensure that multiple components connected to the clock will not malfunction due to clock modification. This method uses an automated script to classify multiple clock relationships into a modifiable range, avoiding the possibility of failure due to modification. In this embodiment, the clock information of the clock information configuration table is filled in the first worksheet (Sheet1) of the excel file. The hardware simulation environment can generally only configure 16 clock generators (the maximum number of clock generator configurations supported by the hardware simulation environment is 16), and if the frequencies of multiple clocks differ greatly, such as low frequency 50M and high frequency 6.4G. Then, the slow clock sampling signal will slow down the simulation speed of the entire chip during the simulation process. Therefore, it is important that the clock information is clear and reasonable. For example, in Figure 4 In the example, the number of actual clocks exceeds 16. During the analysis, based on the premise of ensuring the design function, some clocks are merged to complete the clock analysis. Therefore, in order to optimize the utilization, all the adopted clocks will be found and listed in the actual clock (name) column. At the same time, this design will count the frequency and source of all clocks and list them in the corresponding column. As shown in the figure above, when the number of clocks is greater than 16, during the analysis, based on the premise of ensuring the design function, some clocks are merged, such as the actual clocks with the same frequency (clk1, clk2, clk3) are organized into hw_clk1, the actual clocks with modifiable frequency (clk4, clk5) are organized into hw_clk2, and the other clocks are analogous. This design can reduce the total number of clocks, thereby meeting the requirement of only configuring 16 clock generators, while reducing the utilization of hardware resources.
[0030] like Figure 5 As shown, each data subset in the configuration information statistical data set of this embodiment includes a reset information configuration table, and the fields in the reset information configuration table include: reset signal (name), reset value (worth), mark (note) and reset start time (time); before step S1, it includes sorting reset logic information for the verified design DUT and generating a reset information configuration table; in step S2, when the information in each data subset in the configuration information statistical data set is respectively identified by an automated script and the corresponding variables are parsed, it includes setting the reused reset logic for the reset logic that generates the same reset signal through the assignment assign in the code to reduce the resource configuration of the additional reset logic. The reset logic is the guarantee of the initial value of the design code and cannot be modified at will. Therefore, this method starts with analyzing the source of the reset logic, determining the reset source function, and merging the reset logic while ensuring the normal operation of the reset logic function. In this embodiment, the reset information of the reset information configuration table is filled in the second worksheet (Sheet2) of the excel file. The reset logic is related to whether the entire DUT design runs correctly. The setting of multiple resets will increase the difficulty of hardware accelerator compilation and increase the use of logic units (LUT). Therefore, the use of reset logic needs to be carefully considered (for example, whether to reuse). Figure 5 The reset logic reset_2, reset_3, and reset_4 can be reused through the assignment settings in the code without additionally resetting the reset-related resource configuration.
[0031] like Figure 6As shown, each data subset in the configuration information statistical data set of this embodiment includes a force information configuration table, and the fields in the force information configuration table include: signal name, type, value / correspondence and identification, the signal name is the name of the forced signal, the type is the type of the forced signal, the value / correspondence records the value or correspondence of the forced signal and is allowed to be empty, and the required conditions of the forced signal are noted in the identification; in step S2, when the information in each data subset in the configuration information statistical data set is identified by the automated script and the corresponding variables are parsed, the forced signal whose required conditions are not met is not processed forcibly to save compilation resources. In the usual processing, the forced signal will be listed unconditionally in the compilation stage to ensure that the signal in the operation stage can meet the use requirements. In this method, by clearly analyzing the force mechanism, the application of force in different situations is ensured, and the method of special treatment of special situations is adopted to classify the force mechanism. In order to ensure the running state, it is necessary to clearly list the force type in Excel, and at the same time, the automated script is used to simulate whether the same type of signal is comprehensive to ensure the normal operation of subsequent work. In this embodiment, fill in the information of the mandatory information configuration table in the fifth worksheet (Sheet5) of the Excel file. The force mechanism needs to be noted. If unnecessary PADs (pins) are forced to high, or the forced signals are too complicated, the resources occupied by the compilation will increase, resulting in a decrease in utilization. The force mechanism needs to be noted. Some signals used in targeted scenarios will save resources if they are not forced in other scenarios (such as Figure 6 The signals marked with a cross in the identification column), or forcing unnecessary pin PADs to high, or forcing signals to be too cumbersome, will increase the resources occupied by the compilation and reduce the utilization rate. During the design, do not force these signals to be processed unless there are special circumstances, which will save a lot of compilation resources. In this embodiment, in other sheets of the excel file, there are other configuration files, which are also necessary conditions for compilation settings and are the basis for the normal operation of the entire verification. They are not listed here one by one.
[0032] like Figure 7As shown, each data subset in the configuration information statistical data set of this embodiment includes a configuration component information configuration table, and the fields in the configuration component information configuration table include: module name, number and identifier, the module name is the name of the configuration component, the number is the number of configuration components, and the identifier is a note related to the number of configuration components; in step S2, when the information in each data subset in the configuration information statistical data set is respectively identified by an automated script and the corresponding variables are parsed, it includes reducing the number of configuration components used according to the minimum number of module names identified by the identifier to save compilation resources. Usually, the peripheral code is not distinguished by identifiers. When building a hardware simulation environment, all peripherals are introduced into the hardware simulation environment, resulting in a large amount of resource waste. This method not only clearly identifies the use environment of each component in Excel, but also uses automated scripts to control modules that are not needed to be used as empty modules to ensure that the hardware simulation environment meets various testing requirements. Fill in the information of the relevant components in the configuration component information configuration table, Figure 7 The module name, number and identification of the relevant components are listed in the table. The identification includes notes related to the number of configuration components. For example, although the number of configuration components PCIE is 2, it can be 1 at least. In this case, the number can be set to 1 to reduce the number of configuration components used to save compilation resources. In addition, the identification can also include the need to decide whether to add or not based on usage. In some scenarios, for example, DDR and CAN are not needed. Not configuring these two components will save a lot of compilation resources and simplify the configuration scheme. If all components are added in all scenarios, a lot of compilation resources will be occupied, resulting in low utilization and long compilation time.
[0033] like Figure 8 As shown, each data subset in the configuration information statistical data set of this embodiment includes a top-level information configuration table, and the fields in the top-level information configuration table include: type and name / path, wherein the type is the type of the top-level information, and the name / path is the name or path of the top-level information. The top-level information configuration table is also used for referencing the name / path of the top-level information when the hardware simulation environment re-executes compilation to prevent input errors of the top-level information. The name / path of the design top-level information will be referenced multiple times during compilation, and after being sorted out, it is convenient for subsequent configuration references to prevent manual input errors. It should be noted that parsing the corresponding variables in step S2 to obtain the variable groups corresponding to each data subset in the information statistical data table; and generating configuration information according to the format of the configuration file required by the hardware simulation environment for the variable groups corresponding to each data subset in step S3 and writing them into various configuration files required by the hardware simulation environment are all well-known methods, so their detailed implementation details will not be described in detail here.
[0034] In summary, the method of using an automated script to build a hardware simulation environment in this embodiment adopts Python to identify the configuration information in different worksheets (sheets) in Excel, and organize the configuration information according to different variable parameter groups, and finally fill the different variable information into the corresponding configuration file to complete the automated configuration, which can clearly plan the configuration problem files required for building a hardware simulation environment, avoiding the problem of multiple files searching for information and being easily confused; and the method of this embodiment adopts an automated script to implement file configuration, which greatly avoids manual input errors. The method of this embodiment includes reading the configuration information statistical data set of the verified design DUT through an automated script, identifying the information in each data subset in the configuration information statistical data set through an automated script and parsing the corresponding variables, thereby obtaining the variable groups corresponding to each data subset in the information statistical data table, generating configuration information according to the format of the configuration file required by the hardware simulation environment for the variable groups corresponding to each data subset and writing them into various configuration files required by the hardware simulation environment, thereby being able to realize chip verification for large-scale chips such as tens of billions to hundreds of billions of gates to simplify the construction process of the hardware simulation environment, increase resource utilization, avoid the time consumed by repeatedly building the environment due to confusion errors, and improve the efficiency of chip verification.
[0035] In addition, this embodiment also provides a system for building a hardware simulation environment using an automated script, including a microprocessor and a memory connected to each other, wherein the microprocessor is programmed or configured to execute the method for building a hardware simulation environment using an automated script.
[0036] In addition, this embodiment also provides a computer-readable storage medium, in which a computer program or instruction is stored. The computer program or instruction is programmed or configured to execute the method of building a hardware simulation environment by an automated script through a processor.
[0037] In addition, this embodiment also provides a computer program product, including a computer program or instructions, which are programmed or configured to execute the method of building a hardware simulation environment by using an automated script through a processor.
[0038] Those skilled in the art should understand that the technical solutions provided by the embodiments of the present application may be in the form of methods, systems, or computer program products. Therefore, the present application may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present application may take the form of a computer program product implemented on one or more computer-readable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes. The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the process Figure 1 A process or multiple processes and / or boxes Figure 1 These computer program instructions can also be stored in a computer-readable memory that can guide a computer or other programmable data processing device to work in a specific way, so that the instructions stored in the computer-readable memory produce a product including an instruction device, which implements the functions specified in the process. Figure 1 A process or multiple processes and / or boxes Figure 1 These computer program instructions can also be loaded onto a computer or other programmable data processing device, so that a series of operation steps are executed on the computer or other programmable device to produce a computer-implemented process, so that the instructions executed on the computer or other programmable device provide for implementing the process in the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.
[0039] The above is only a preferred embodiment of the present invention, and the protection scope of the present invention is not limited to the above embodiments. All technical solutions under the concept of the present invention belong to the protection scope of the present invention. It should be pointed out that for ordinary technicians in this technical field, some improvements and modifications without departing from the principle of the present invention should also be regarded as the protection scope of the present invention.
Claims
1. A method for building a hardware simulation environment using an automated script, characterized in that: The steps include: S1, reads the configuration information statistical data set of the verified design DUT through an automated script; S2, identifying the information in each data subset in the configuration information statistical data set and parsing the corresponding variables through an automated script, thereby obtaining a variable group corresponding to each data subset in the information statistical data table; S3, generating configuration information for the variable groups corresponding to the data subsets according to the format of the configuration files required by the hardware simulation environment and writing the configuration information into various configuration files required by the hardware simulation environment.
2. The method for building a hardware simulation environment using an automated script according to claim 1, wherein: Each data subset in the configuration information statistical data set includes a clock information configuration table, and the fields in the clock information configuration table include: actual clock, actual frequency, hard simulation frequency, identification and hardware clock. Before step S1, it includes collating clock information for the verified design DUT and generating a clock information configuration table: collecting information on all clock signals in the verified design DUT, the information on the clock signals includes actual clock, actual frequency and identification; allocating hardware clocks to actual clocks, and merging actual clocks with the same actual frequency into the same hardware clock using the same hard simulation frequency, and merging actual clocks with modifiable frequencies into the same hardware clock using the same hard simulation frequency, so that the final allocated hardware clocks are less than the maximum number of clock generator configurations supported by the hardware simulation environment; generating a clock information configuration table according to the information of each actual clock and the hardware clocks allocated to the actual clocks and their hard simulation frequencies.
3. The method for building a hardware simulation environment using an automated script according to claim 1, characterized in that: Each data subset in the configuration information statistical data set includes a reset information configuration table, and the fields in the reset information configuration table include: reset signal, reset value, identification, and reset start time; before step S1, the reset logic information is sorted out for the verified design DUT and a reset information configuration table is generated; in step S2, when the information in each data subset in the configuration information statistical data set is respectively identified by an automated script and the corresponding variables are parsed, including for the reset logic that generates the same reset signal, the multiplexing reset logic is set by the assignment assign in the code to reduce the resource configuration of the additional reset logic.
4. The method for building a hardware simulation environment using an automated script according to claim 1, wherein: Each data subset in the configuration information statistical data set includes a mandatory information configuration table, and the fields in the mandatory information configuration table include: signal name, type, value / correspondence and identifier, the signal name is the name of the mandatory signal, the type is the type of the mandatory signal, the value / correspondence records the value or correspondence of the mandatory signal and is allowed to be empty, and the identifier is noted with the required conditions for the mandatory signal; in step S2, when the information in each data subset in the configuration information statistical data set is identified by an automated script and the corresponding variables are parsed, the mandatory signal whose required conditions are not met is not processed forcibly to save compilation resources.
5. The method for building a hardware simulation environment using an automated script according to claim 1, characterized in that: Each data subset in the configuration information statistical data set includes a configuration component information configuration table, and the fields in the configuration component information configuration table include: module name, number and identifier, the module name is the name of the configuration component, the number is the number of configuration components, and the identifier is a note related to the number of configuration components; in step S2, when the information in each data subset in the configuration information statistical data set is respectively identified by an automated script and the corresponding variables are parsed, it includes reducing the number of configuration components used according to the minimum number of module names identified by the identifier to save compilation resources.
6. The method for building a hardware simulation environment using an automated script according to claim 1, characterized in that: Each data subset in the configuration information statistical data set includes a top-level information configuration table. The fields in the top-level information configuration table include: type and name / path, where type is the type of top-level information, and name / path is the name or path of the top-level information. The top-level information configuration table is also used for the hardware simulation environment to reference the name / path of the top-level information when re-executing compilation to prevent input errors of the top-level information.
7. The method for building a hardware simulation environment using an automated script according to claim 1, characterized in that: The configuration information statistical data set in step S1 is an Excel file, each data subset in the configuration information statistical data set refers to each worksheet sheet in the Excel file, and the automation script is a Python script.
8. A system for building a hardware simulation environment using an automated script, comprising a microprocessor and a memory connected to each other, characterized in that: The microprocessor is programmed or configured to execute the method for building a hardware simulation environment by an automated script as described in any one of claims 1 to 7.
9. A computer-readable storage medium having a computer program or instruction stored therein, characterized in that: The computer program or instruction is programmed or configured to execute the method of automatically scripting a hardware simulation environment as described in any one of claims 1 to 7 through a processor.
10. A computer program product comprising a computer program or instructions, characterized in that The computer program or instruction is programmed or configured to execute the method of automatically scripting a hardware simulation environment as described in any one of claims 1 to 7 through a processor.