Current sampling and protection circuit worst case analysis method, terminal and medium

Abstract

The invention discloses a worst case analysis method of a current sampling and protection circuit, a terminal and a medium. The analysis method comprises the following steps: acquiring at least two analysis indexes and acquiring a circuit simulation model corresponding to the current sampling and protection circuit; wherein the at least two analysis indexes are determined by at least two of a fault tree analysis method, a potential failure mode influence and consequence analysis method, a hazard analysis and risk assessment analysis method, an expert experience assessment method and fault library information; based on the at least two analysis indexes, carrying out circuit worst case analysis on the circuit simulation model to obtain an analysis result corresponding to each analysis index; and verifying the current sampling and protecting circuit according to the at least two analysis results. According to the scheme, the analysis indexes are determined by using different analysis methods, and the comprehensiveness of the worst case analysis of the current sampling and protection circuit is improved.

Description

Technical Field

[0001] The present application relates to the field of circuit simulation technology, and in particular to a worst-case analysis method, terminal and medium for current sampling and protection circuits. Background Art

[0002] In order to achieve accurate adjustment of the torque of new energy vehicles and avoid the possibility of overheating or even burning of the motor controller caused by excessive current, the motor controller of new energy vehicles is usually equipped with a current sampling and protection circuit. On the one hand, the current sampling and protection circuit is used to detect whether the current of the motor exceeds the alarm value when it is running. If so, the motor is shut down to protect it from overcurrent. On the other hand, the current sampling and protection circuit is also used to transmit the acquired current value to the control chip of the motor controller to accurately control the motor speed. The current sampling and protection circuit needs to maintain normal operation under different working environments. In order to determine the design result of the current sampling and protection circuit, that is, whether the designed circuit meets the requirements, it is necessary to perform corresponding tests on the designed circuit.

[0003] As an important part of circuit testing, worst-case analysis (WCCA) analyzes the designed circuit accordingly. On the one hand, it determines the main factors that affect the stress of components in the designed circuit, and on the other hand, it provides specific data of each parameter of the designed circuit under the worst case. On the other hand, it can also point out the improvement direction of the designed circuit and improve the reliability of the designed circuit. The related technology mainly adopts a single analysis method, which is not comprehensive enough. Summary of the invention

[0004] The present application provides a worst-case analysis method for a current sampling and protection circuit, a terminal device, and a computer storage medium.

[0005] A technical solution adopted by the present application is to provide a worst-case analysis method for a current sampling and protection circuit, the method comprising:

[0006] Obtain at least two analysis indicators and obtain a circuit simulation model corresponding to the current sampling and protection circuit; wherein the at least two analysis indicators are determined by at least two of a fault tree analysis method, a potential failure mode impact and consequence analysis method, a hazard analysis and risk assessment analysis method, an expert experience assessment method, and fault library information;

[0007] Based on the at least two analysis indicators, performing a circuit worst-case analysis on the circuit simulation model to obtain an analysis result corresponding to each analysis indicator;

[0008] The current sampling and protection circuit is verified according to at least two of the analysis results.

[0009] Optionally, at least two analysis indicators are obtained, including:

[0010] Obtaining performance analysis conditions of the current sampling and protection circuit;

[0011] Based on the performance analysis conditions, at least two analysis indicators are determined.

[0012] Optionally, based on the performance analysis conditions, at least two analysis indicators are determined, including:

[0013] Obtain at least two sets of candidate analysis results corresponding to the fault tree analysis method, the potential failure mode impact and consequence analysis method, the hazard analysis and risk assessment analysis method, the expert experience assessment method, and the fault library information in the performance analysis conditions; the candidate analysis results include candidate analysis indicators and candidate indicator scores corresponding to the candidate analysis indicators;

[0014] A weighted sum of the scores of at least two groups of candidate indicators is calculated to obtain an analysis indicator score, and the analysis indicator score is used to determine at least two analysis indicators from the at least two groups of candidate analysis indicators.

[0015] Optionally, based on at least two analysis indicators, a circuit worst-case analysis is performed on the circuit simulation model to obtain an analysis result corresponding to each analysis indicator, including:

[0016] Divide the circuit simulation model into components to obtain component models corresponding to several components;

[0017] Based on at least two analysis indicators, the circuit simulation model is subjected to a circuit worst-case analysis to obtain analysis results corresponding to each analysis indicator, including:

[0018] Based on at least two analysis indicators, a worst-case circuit analysis is performed on each component model to obtain a local analysis result corresponding to each component under each analysis indicator;

[0019] The analysis result is obtained by utilizing all local analysis results under the same analysis index.

[0020] Optionally, verifying the current sampling and protection circuit according to at least two analysis results includes:

[0021] Select at least some of the analysis indicators, and based on at least some of the analysis indicators, perform a circuit worst-case test on the current sampling and protection circuit to obtain an actual test result;

[0022] In response to the analysis result being within a preset range, the current sampling and protection circuit is verified according to at least two analysis results; the preset range is determined based on actual test results.

[0023] Optionally, after selecting at least some of the analysis indicators, and performing a circuit worst-case test on the current sampling and protection circuit based on at least some of the analysis indicators to obtain actual test results, the method further includes:

[0024] In response to the analysis result being outside a preset range, optimizing or redesigning the circuit simulation model;

[0025] Based on at least two analysis indicators, a circuit worst-case analysis is performed on the redesigned or optimized circuit simulation model to obtain an optimization analysis result corresponding to each analysis indicator;

[0026] The current sampling and protection circuit is verified based on at least two optimization analysis results.

[0027] Optionally, the circuit worst-case analysis includes at least one of sensitivity analysis, component thermal and electrical stress analysis, Monte Carlo analysis, and extreme value stress analysis.

[0028] Another technical solution adopted by the present application is to provide a terminal device, the terminal device comprising a memory and a processor connected to the memory;

[0029] The memory is used to store program data, and the processor is used to execute the program data to implement the worst-case analysis method for current sampling and protection circuit as described above.

[0030] Another technical solution adopted by the present application is to provide a computer storage medium, wherein the computer storage medium is used to store program data, and when the program data is executed by a computer, it is used to implement the worst-case analysis method for current sampling and protection circuit as described above.

[0031] The beneficial effects of the present application are: using at least two analysis methods, determining at least two analysis indicators, improving the comprehensiveness of the worst-case analysis of the circuit, further, based on at least two analysis indicators, performing the worst-case analysis of the circuit on the circuit simulation model, obtaining the analysis result corresponding to each analysis indicator, and further, using at least two analysis results to verify the current sampling and protection circuit. The worst-case analysis method for the current sampling and protection circuit provided by the present application determines the analysis indicators through different analysis methods, improving the comprehensiveness of the worst-case analysis of the current sampling and protection circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0033] Figure 1 It is a flow chart of an embodiment of a worst-case analysis method for a current sampling and protection circuit provided by the present application;

[0034] Figure 2 It is a flow chart of another embodiment of the worst-case analysis method for current sampling and protection circuit provided by the present application;

[0035] Figure 3 is a schematic diagram of an embodiment of a circuit simulation model provided by the present application;

[0036] Figure 4 It is a schematic diagram of an embodiment of component stress simulation analysis results provided by the present application;

[0037] Figure 5 is a schematic diagram of an embodiment of a DC gain analysis simulation result provided by the present application;

[0038] Figure 6 is a schematic diagram of another embodiment of the DC gain analysis simulation result provided by the present application;

[0039] Figure 7 is a schematic diagram of another embodiment of the DC gain analysis simulation result provided by the present application;

[0040] Figure 8 It is a schematic diagram of an embodiment of a sensitivity analysis simulation result provided by the present application;

[0041] Fig. 9 It is a schematic diagram of an embodiment of a worst-case analysis simulation result provided by the present application;

[0042] Fig.10 is a schematic diagram of an embodiment of a cutoff frequency analysis simulation result provided by the present application;

[0043] Fig.11 is a schematic diagram of another embodiment of the cut-off frequency analysis simulation result provided by the present application;

[0044] Fig.12 is a schematic diagram of another embodiment of the worst-case analysis simulation results provided by the present application;

[0045] Fig.13 is a schematic diagram of another embodiment of the worst-case analysis simulation results provided by the present application;

[0046] Fig.14 is a schematic diagram of another embodiment of the sensitivity analysis simulation results provided by the present application;

[0047] Fig.15 It is a schematic diagram of an embodiment of a 2kHz AC gain analysis simulation provided by the present application;

[0048] Fig.16 is a schematic diagram of another embodiment of 2kHz AC gain analysis simulation provided by the present application;

[0049] Fig.17 is a schematic diagram of another embodiment of the worst-case analysis simulation results provided by the present application;

[0050] Fig.18 is a schematic diagram of another embodiment of the worst-case analysis simulation results provided by the present application;

[0051] Fig.19 is a schematic diagram of another embodiment of the sensitivity analysis simulation results provided by the present application;

[0052] Fig. 20 It is a schematic diagram of an embodiment of a 2kHz sampling delay analysis simulation result provided by the present application;

[0053] Fig.21 is a schematic diagram of another embodiment of the 2kHz sampling delay analysis simulation results provided by the present application;

[0054] Fig. 22 is a schematic diagram of another embodiment of the worst-case analysis simulation results provided by the present application;

[0055] Fig.23 is a schematic diagram of another embodiment of the worst-case analysis simulation results provided by the present application;

[0056] Fig.24 is a schematic diagram of another embodiment of the sensitivity analysis simulation results provided by the present application;

[0057] Fig.25 It is a schematic diagram of an embodiment of a 2kHz sampling phase shift analysis simulation result provided by the present application;

[0058] Fig.26 is a schematic diagram of another embodiment of the 2kHz sampling phase shift analysis simulation results provided by the present application;

[0059] Fig. 27 is a schematic diagram of another embodiment of the worst-case analysis simulation results provided by the present application;

[0060] Fig.28 is a schematic diagram of another embodiment of the worst-case analysis simulation results provided by the present application;

[0061] Fig.29 is a schematic diagram of another embodiment of the sensitivity analysis simulation results provided by the present application;

[0062] Fig.30 It is a schematic diagram of an embodiment of a protection point threshold analysis simulation result provided by the present application;

[0063] Fig.31 It is a schematic diagram of another embodiment of the protection point threshold analysis simulation result provided by the present application;

[0064] Fig.32 is a schematic diagram of another embodiment of the sensitivity analysis simulation results provided by the present application;

[0065] Fig.33 It is a schematic diagram of another embodiment of the protection point threshold analysis simulation result provided by the present application;

[0066] Fig.34 It is a schematic diagram of another embodiment of the protection point threshold analysis simulation result provided by the present application;

[0067] Fig.35 is a schematic diagram of another embodiment of the sensitivity analysis simulation results provided by the present application;

[0068] Fig.36 It is a schematic diagram of an embodiment of a simulation result of over-current detection delay analysis of a sinusoidal input provided by the present application;

[0069] Fig.37 It is a schematic diagram of another embodiment of the simulation result of over-current detection delay analysis of sinusoidal input provided by the present application;

[0070] Fig.38 It is a schematic diagram of an embodiment of a worst-case analysis simulation result of over-current detection delay of a sinusoidal input provided by the present application;

[0071] Fig.39 It is a schematic diagram of another embodiment of the worst-case analysis simulation results of over-current detection delay of sinusoidal input provided by the present application;

[0072] Fig.40 It is a schematic diagram of an embodiment of a simulation result of over-current detection delay sensitivity analysis of a sinusoidal input provided by the present application;

[0073] Fig.41 It is a schematic diagram of another embodiment of the simulation results of over-current detection delay sensitivity analysis of sinusoidal input provided by the present application;

[0074] Fig.42 It is a schematic diagram of an embodiment of a simulation result of overcurrent detection delay analysis of a step input provided by the present application;

[0075] Fig.43 It is a schematic diagram of another embodiment of the simulation result of over-current detection delay analysis of step input provided by the present application;

[0076] Fig.44 It is a schematic diagram of an embodiment of a worst-case analysis simulation result of overcurrent detection delay of a step input provided by the present application;

[0077] Fig.45 It is a schematic diagram of another embodiment of the worst-case analysis simulation results of overcurrent detection delay of step input provided by the present application;

[0078] Fig.46 It is a schematic diagram of an embodiment of a simulation result of over-current detection delay sensitivity analysis of a step input provided by the present application;

[0079] Fig.47 It is a schematic diagram of another embodiment of the simulation results of over-current detection delay sensitivity analysis of step input provided by the present application;

[0080] Fig.48 is a schematic diagram of an embodiment of actual test results of step input overcurrent detection provided by the present application;

[0081] Fig.49 is a schematic diagram of an embodiment of actual test results of sinusoidal input overcurrent detection provided by the present application;

[0082] Fig.50 It is a structural diagram of an embodiment of a terminal device provided by the present application;

[0083] Fig.51 It is a structural diagram of an embodiment of a computer storage medium provided by the present application. DETAILED DESCRIPTION

[0084] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0085] The worst case of the current sampling and protection circuit refers to the situation when the most undesirable conditions are applied to the current sampling and protection circuit while considering the circuit working environment, circuit input, and component parameter value drift of the current sampling and protection circuit. The Worst Case Circuit Analysis (WCCA) of the current sampling and protection circuit is to evaluate whether the working performance of the current sampling and protection circuit under these worst case conditions still meets the design requirements.

[0086] The worst-case circuit analysis method (WCCA) provided by related technologies usually performs simple calculations (such as resistance and capacitance) in the early stages of research and development. In a specific circuit, there are many devices involved, many random combination categories, and a huge workload for theoretical calculations, which obviously cannot meet specific requirements (tolerance, parameter drift, etc.). In addition to simple theoretical calculations and formula derivations, it can also be carried out on certain simulation software. However, for complex devices in the circuit, it is necessary to obtain simulation models with specified properties, which largely depends on the support of the chip manufacturer, and the circuit construction is relatively complex, making it difficult to complete specific analysis.

[0087] Please refer to Figure 1 , Figure 1 It is a flow chart of an embodiment of a worst-case analysis method for a current sampling and protection circuit provided in the present application.

[0088] like Figure 1 As shown, the worst-case analysis method for the current sampling and protection circuit of the embodiment of the present application may specifically include the following steps:

[0089] S1, obtaining at least two analysis indicators and a circuit simulation model corresponding to a current sampling and protection circuit.

[0090] Among them, at least two analysis indicators are determined by at least two of the fault tree analysis method, the potential failure mode impact and consequence analysis method, the hazard analysis and risk assessment analysis method, the expert experience assessment method, and the fault library information.

[0091] The worst-case analysis method for current sampling and protection circuit provided in the present application is mainly performed by a circuit analysis device. In some embodiments, the circuit analysis device can be a device for monitoring images, a user equipment (UE), a mobile device, a user terminal, a terminal, a cellular phone, a cordless phone, a personal digital assistant (PDA), a handheld device, a computing device, a vehicle-mounted device, a wearable device, and an autonomous driving car, a robot, a security system, and any one or more products of glasses and helmets for augmented reality or virtual reality. In some possible implementations, the worst-case analysis method for current sampling and protection circuit can be implemented by a processor calling a computer-readable instruction stored in a memory.

[0092] In some embodiments, the current sampling and protection circuit may be a phase current sampling and protection circuit, which may be applied to a motor controller.

[0093] In some possible embodiments, the analysis index may be a parameter of the current sampling and protection circuit under different working conditions.

[0094] Exemplarily, the analysis index may be an index such as component stress analysis, DC gain analysis, cutoff frequency analysis, etc., which is not limited here.

[0095] In some possible embodiments, the circuit analysis device obtains the component composition of the current sampling and protection circuit, and constructs a simulation model based on the parameters of the components and the connection relationship between the components.

[0096] Among them, the analysis indicators are derived from some analysis methods and experience summaries. In some embodiments, the analysis indicators include fault tree analysis (FTA) from system level to component level failure. In some embodiments, the analysis indicators include potential failure mode effects and consequences analysis (FMEA) from device level to system. In some embodiments, the analysis indicators include hazard analysis and risk assessment (HARA) of the whole machine. In some embodiments, the analysis indicators also include the evaluation results of expert experience. In some possible embodiments, the analysis indicators also include existing fault library information.

[0097] In the related art, the analysis indicators are mainly derived from one of the above-mentioned analysis methods. Considering that a single analysis method may miss some analysis indicators, based on this, at least two of the above-mentioned analysis methods are adopted to improve the comprehensiveness and rationality of obtaining the analysis indicators.

[0098] S2, based on at least two analysis indicators, performing a circuit worst-case analysis on the circuit simulation model to obtain an analysis result corresponding to each analysis indicator.

[0099] Specifically, the circuit analysis device performs a circuit worst-case analysis on the circuit simulation model based on at least two analysis indicators to obtain an analysis result corresponding to each analysis indicator.

[0100] S3, verifying the current sampling and protection circuit according to at least two analysis results.

[0101] In some embodiments, the circuit analysis device compares the design requirements and analysis results of the current sampling and protection circuit. If the analysis results are outside the design requirements, the circuit analysis device redesigns or optimizes the design of the current sampling and protection circuit. For example, at least some components in the current sampling and protection circuit are replaced, and the worst-case analysis of the circuit is performed again.

[0102] In some embodiments, if the analysis result is within the design requirements, the circuit analysis device archives the analysis result.

[0103] The above scheme uses at least two analysis methods to determine at least two analysis indicators, improves the comprehensiveness of the worst-case analysis of the circuit, further, based on at least two analysis indicators, performs the worst-case analysis of the circuit on the circuit simulation model, obtains the analysis result corresponding to each analysis indicator, and further, uses at least two analysis results to verify the current sampling and protection circuit. The worst-case analysis method for the current sampling and protection circuit provided by the present application determines the analysis indicators through different analysis methods, and improves the comprehensiveness of the worst-case analysis of the current sampling and protection circuit.

[0104] Another embodiment of the worst-case analysis method for current sampling and protection circuit provided by the present application may specifically include the following steps:

[0105] S11, obtaining performance analysis conditions of current sampling and protection circuit.

[0106] Optionally, the performance analysis condition may be a design requirement of a current sampling and protection circuit, or may be certain functions corresponding to components of the circuit in a specification sheet.

[0107] Exemplarily, the performance analysis condition is any one of the supply voltage and the ambient temperature.

[0108] S12, determining at least two analysis indicators based on the performance analysis conditions.

[0109] In some possible embodiments, the circuit analysis device performs at least two methods of a fault tree analysis method, a potential failure mode impact and consequence analysis method, a hazard analysis and risk assessment analysis method, an expert experience assessment method, and fault library information on the performance analysis conditions to obtain at least two candidate analysis indicator lists. Further, the circuit analysis device determines at least two analysis indicators based on the two candidate analysis indicator lists.

[0110] S13, obtaining a circuit simulation model corresponding to the current sampling and protection circuit.

[0111] S14, based on at least two analysis indicators, performing a circuit worst-case analysis on the circuit simulation model to obtain an analysis result corresponding to each analysis indicator.

[0112] S15, verifying the current sampling and protection circuit according to at least two analysis results.

[0113] The above scheme uses at least two analysis methods to determine at least two analysis indicators, improves the comprehensiveness of the worst-case analysis of the circuit, further, based on at least two analysis indicators, performs the worst-case analysis of the circuit on the circuit simulation model, obtains the analysis result corresponding to each analysis indicator, and further, uses at least two analysis results to verify the current sampling and protection circuit. The worst-case analysis method for the current sampling and protection circuit provided by the present application determines the analysis indicators through different analysis methods, and improves the comprehensiveness of the worst-case analysis of the current sampling and protection circuit.

[0114] Another embodiment of the worst-case analysis method for current sampling and protection circuit provided by the present application may specifically include the following steps:

[0115] S21, obtaining current sampling and performance analysis conditions of the protection circuit.

[0116] S22, obtaining at least two sets of candidate analysis results corresponding to the fault tree analysis method, the potential failure mode impact and consequence analysis method, the hazard analysis and risk assessment analysis method, the expert experience assessment method, and the fault library information in the performance analysis condition.

[0117] The candidate analysis results include candidate analysis indicators and candidate indicator scores corresponding to the candidate analysis indicators. The candidate indicator scores are used to characterize the importance of the candidate analysis indicators. In some embodiments, the higher the candidate indicator score, the higher the importance of the corresponding candidate analysis indicator.

[0118] S23, calculating a weighted sum of the scores of at least two groups of candidate indicators to obtain an analysis indicator score, and using the analysis indicator score to determine at least two analysis indicators from the at least two groups of candidate analysis indicators.

[0119] Specifically, the circuit analysis device calculates a weighted sum of at least two groups of candidate index scores to obtain an analysis index score.

[0120] In some embodiments, the weight can be determined by the importance of the analysis method, and the higher the importance, the higher the weight. Optionally, the weight can be determined by an expert knowledge base, a neural network, or a machine learning method, which is not limited here.

[0121] Exemplarily, the circuit analysis device obtains the first candidate analysis result corresponding to the performance analysis condition under the fault tree analysis method, and the second candidate analysis result corresponding to the performance analysis condition under the potential failure mode effect and consequence analysis method. The first candidate analysis result includes the first candidate analysis indicator, and the first candidate indicator score corresponding to the first candidate analysis indicator. Similarly, the second candidate analysis result includes the second candidate analysis indicator, and the second candidate indicator score corresponding to the second candidate analysis indicator.

[0122] Furthermore, the circuit analysis device obtains a first weight corresponding to the fault tree analysis method and a second weight corresponding to the potential failure mode impact and consequence analysis method, calculates the weighted sum of the first candidate indicator score and the second candidate indicator score, and obtains the analysis indicator score. Furthermore, the circuit analysis device selects several candidate analysis indicators with the highest analysis indicator scores to obtain at least two analysis indicators.

[0123] In the related art, a step-by-step approach is mainly adopted, where the analysis results are screened using the first analysis method to obtain the first candidate analysis indicator, and then the first candidate analysis indicator is further analyzed using the second analysis method to determine the analysis indicator. Considering that the first candidate analysis indicator obtained may omit useful candidate indicator content, based on this, the present application adopts different analysis methods to determine multiple groups of candidate analysis indicators, and then performs weighted summation to improve the comprehensiveness of the analysis indicators.

[0124] S24, obtaining a circuit simulation model corresponding to the current sampling and protection circuit.

[0125] S25, based on at least two analysis indicators, performing a circuit worst-case analysis on the circuit simulation model to obtain an analysis result corresponding to each analysis indicator.

[0126] S26, verifying the current sampling and protection circuit according to at least two analysis results.

[0127] The above scheme uses at least two analysis methods to determine at least two analysis indicators, improves the comprehensiveness of the worst-case analysis of the circuit, further, based on at least two analysis indicators, performs the worst-case analysis of the circuit on the circuit simulation model, obtains the analysis result corresponding to each analysis indicator, and further, uses at least two analysis results to verify the current sampling and protection circuit. The worst-case analysis method for the current sampling and protection circuit provided by the present application determines the analysis indicators through different analysis methods, and improves the comprehensiveness of the worst-case analysis of the current sampling and protection circuit.

[0128] Furthermore, considering that different analysis methods have their own advantages and disadvantages, the present application simultaneously adopts at least two analysis methods to determine candidate analysis indicators, and then determines the analysis indicators from the candidate analysis indicators by weighted summation to avoid omission of important analysis indicators.

[0129] Another embodiment of the worst-case analysis method for current sampling and protection circuit provided by the present application may specifically include the following steps:

[0130] S31, dividing the circuit simulation model into components to obtain component models corresponding to a number of components.

[0131] In some embodiments, the circuit analysis device divides the components of the circuit simulation model according to the types and specific categories of the components to perform a worst-case analysis on each component to meet the needs of worst-case analysis of current sampling and protection circuits.

[0132] This application takes into account the large number of components involved in the design of the circuit, and the large number of categories that can be randomly combined. If the circuit simulation model is not divided into components, it will take a lot of time to build the circuit simulation model, and it will be difficult to meet the requirements under certain analysis indicators (such as tolerance, parameter drift, etc.). Based on this, by dividing the components of the circuit simulation, the efficiency of building the circuit simulation model can be reduced, and the efficiency and comprehensiveness of the worst-case analysis can be further improved.

[0133] The circuit modules in the current sampling and protection circuit hardware are divided into the smallest units as much as possible, and the smaller the module decomposition, the more conducive to analysis. In some embodiments, the circuit analysis device determines the major category to which the designed circuit belongs, and the major category to which the circuit belongs may include analog circuits, digital circuits, and mixed analog and digital circuits. Further, the circuit analysis device obtains the subcategory to which the circuit module belongs in the designed circuit, and specifically divides it into the smallest circuit unit. For example, the analog circuit includes any one or more of the bus voltage sampling unit, the phase current sampling unit, the temperature sampling unit, and the rotary transformer unit. The digital circuit has any one or more of the level conversion unit, the drive unit, the communication unit, the collision unit, and the interlocking unit; the mixed analog and digital circuit has any one or more of the minimum system unit and the power management unit.

[0134] Among them, each component model corresponds to a component in the current sampling and protection circuit, and each component model is used to simulate the operation of the corresponding component.

[0135] In some embodiments, the circuit analysis device obtains a component model corresponding to the target component from an existing component model library.

[0136] In some possible embodiments, in response to the simulation model library not containing a component model corresponding to the target component, the circuit analysis device obtains a candidate component model corresponding to a similar component similar to the target component from the simulation model library, modifies the specification parameters of the candidate component model, and uses the modified candidate component model as the target component model corresponding to the target component. Considering that the original manufacturer may not be able to provide detailed component models for some components in the design circuit, based on this, the present application searches for the component most similar to the target component in the existing component model library, and modifies the parameters of the simulation model of the component to obtain the target component model.

[0137] In the related art, for designing more complex components in the circuit, it is necessary to obtain the component simulation model provided by the original manufacturer. Without the component simulation model, it is difficult to conduct the worst-case analysis of the circuit for the component model.

[0138] The present application can further improve the extensiveness of worst-case analysis of components through the above method.

[0139] S32, based on at least two analysis indicators, performing a circuit worst-case analysis on each component model to obtain a local analysis result corresponding to each component under each analysis indicator.

[0140] Among them, at least two analysis indicators are determined by at least two of the fault tree analysis method, the potential failure mode impact and consequence analysis method, the hazard analysis and risk assessment analysis method, the expert experience assessment method, and the fault library information.

[0141] Specifically, the circuit analysis device performs a worst-case circuit analysis on each component model based on different analysis indicators, and obtains a local analysis result corresponding to each component under each analysis indicator.

[0142] In some possible embodiments, in response to the simulation model library not containing a component model corresponding to a target component and the simulation model library not containing a candidate component model, a worst-case circuit test is performed on the target component based on at least two analysis indicators to obtain a local analysis result corresponding to the target component under each analysis indicator.

[0143] It should be noted that for some target components that do not have their own simulation models, it is necessary to conduct comprehensive real boundary tests on the target components, that is, to conduct actual worst-case analysis tests on the target components according to the analysis indicators, and use the test results under each analysis indicator as the local analysis results. Through the above method, the performance input and output indicators of the target components are determined, thereby further improving the comprehensiveness of the worst-case analysis method provided in this application.

[0144] S33, using all local analysis results under the same analysis index to obtain an analysis result.

[0145] Specifically, the circuit analysis device aggregates the local analysis results of different components under the same analysis index to obtain the analysis result under the same analysis index. Further, the analysis result corresponding to each analysis index is obtained.

[0146] S34, verifying the current sampling and protection circuit according to at least two analysis results.

[0147] The above scheme uses at least two analysis methods to determine at least two analysis indicators, improves the comprehensiveness of the worst-case analysis of the circuit, further, based on at least two analysis indicators, performs the worst-case analysis of the circuit on the circuit simulation model, obtains the analysis result corresponding to each analysis indicator, and further, uses at least two analysis results to verify the current sampling and protection circuit. The worst-case analysis method for the current sampling and protection circuit provided by the present application determines the analysis indicators through different analysis methods, and improves the comprehensiveness of the worst-case analysis of the current sampling and protection circuit.

[0148] Furthermore, the circuit simulation model is split, and a divide-and-conquer approach is adopted to perform corresponding analysis on each component, taking into account the authenticity of the details. In addition, the worst-case analysis of the circuit can be completed without complex theoretical calculations.

[0149] Another embodiment of the worst-case analysis method for current sampling and protection circuit provided by the present application may specifically include the following steps:

[0150] S41, obtaining at least two analysis indicators and a circuit simulation model corresponding to the current sampling and protection circuit.

[0151] Among them, at least two analysis indicators are determined by at least two of the fault tree analysis method, the potential failure mode impact and consequence analysis method, the hazard analysis and risk assessment analysis method, the expert experience assessment method, and the fault library information.

[0152] S42, based on at least two analysis indicators, performing a circuit worst-case analysis on the circuit simulation model to obtain an analysis result corresponding to each analysis indicator.

[0153] In some embodiments, the circuit worst-case analysis method provided in the present application is performed using PSpice simulation software.

[0154] In some embodiments, the circuit worst-case analysis includes at least one of sensitivity analysis, component thermal and electrical stress analysis, Monte Carlo analysis, and extreme value stress analysis.

[0155] For sensitivity analysis, after the circuit analysis device sets the basic parameters of the components, it calls the relevant functions (such as maximum value, average value, rise time, etc.) to record and scan the circuit to obtain the most sensitive parameters that affect the circuit input and output, and record their relative sensitivity values, so as to understand the impact of the specific tolerance in the circuit on the circuit output and provide a basic reference for subsequent optimization design.

[0156] For thermoelectric stress analysis, the circuit analysis device can refer to the circuit reliability and derating design or the "GJB / Z35 Component Derating Guidelines", and in combination with the specification sheet in the circuit, compile a file library of rated voltage / rated current / peak power / maximum temperature, etc. while leaving a margin. Furthermore, in the thermoelectric stress analysis link, the circuit analysis device sets the boundary (maximum voltage, maximum load, maximum ambient temperature) conditions and calls the file library, and records the stress proportion of each device in the circuit. It is possible to predict the power consumption, junction temperature, secondary breakdown limit, breakdown voltage of the maximum current limiting device, etc. of the components, and obtain the risk situation of the circuit.

[0157] For example, before performing the thermal and electrical stress analysis, the circuit analysis device may also perform a basic design selection check on the components, and the check items may be as shown in the following table:

[0158]

[0159] For Monte Carlo analysis, under certain working conditions of the designed circuit, the circuit analysis device is set to simulate no less than 400 times. After the analysis is completed, the statistical indicators of the parameters are obtained and recorded to obtain the circuit characteristic values ​​obtained from each simulation and the statistical analysis of large quantities of circuit characteristic raw data.

[0160] For extreme stress analysis, the circuit analysis device determines the change direction of each component (increase / decrease) according to the requirements that cause the circuit characteristics to deteriorate, and then simulates these components in the corresponding worst direction according to their possible maximum range (that is, the set tolerance range), and finally outputs the parameters of the circuit parameter extreme value situation.

[0161] S43, selecting at least some of the analysis indicators, and performing a circuit worst-case test on the current sampling and protection circuit based on at least some of the analysis indicators to obtain actual test results.

[0162] Specifically, considering that the analysis results obtained based on the simulation model may be different from the actual results, the circuit analysis device randomly selects some analysis indicators, performs actual boundary tests and fault input tests based on some analysis indicators, and obtains actual test results.

[0163] S45, in response to the analysis result being within a preset range, verifying the current sampling and protection circuit according to at least two analysis results.

[0164] The preset range is determined based on actual test results.

[0165] It can be understood that the analysis result is within a preset range, and it is determined that the actual verification result is consistent with the simulation result. The circuit analysis device performs the steps of verifying the current sampling and protection circuit based on at least two analysis results.

[0166] The above scheme uses at least two analysis methods to determine at least two analysis indicators, improves the comprehensiveness of the worst-case analysis of the circuit, further, based on at least two analysis indicators, performs the worst-case analysis of the circuit on the circuit simulation model, obtains the analysis result corresponding to each analysis indicator, and further, uses at least two analysis results to verify the current sampling and protection circuit. The worst-case analysis method for the current sampling and protection circuit provided by the present application determines the analysis indicators through different analysis methods, and improves the comprehensiveness of the worst-case analysis of the current sampling and protection circuit.

[0167] Furthermore, the analysis results obtained from the simulation are used to carry out actual tests, and the test results are used to verify the analysis results to improve the confidence of the analysis.

[0168] Another embodiment of the worst-case analysis method for current sampling and protection circuit provided by the present application may specifically include the following steps:

[0169] S51, obtaining at least two analysis indicators and a circuit simulation model corresponding to a current sampling and protection circuit.

[0170] Among them, at least two analysis indicators are determined by at least two of the fault tree analysis method, the potential failure mode impact and consequence analysis method, the hazard analysis and risk assessment analysis method, the expert experience assessment method, and the fault library information.

[0171] S52, based on at least two analysis indicators, performing a circuit worst-case analysis on the circuit simulation model to obtain an analysis result corresponding to each analysis indicator.

[0172] S53, selecting at least some of the analysis indicators, and performing a circuit worst-case test on the current sampling and protection circuit based on at least some of the analysis indicators to obtain actual test results.

[0173] S54, selecting at least some of the analysis indicators, and performing a circuit worst-case test on the current sampling and protection circuit based on at least some of the analysis indicators to obtain actual test results.

[0174] S55, in response to the analysis result being outside a preset range, optimizing or redesigning the circuit simulation model.

[0175] It is understandable that if the analysis result is outside the preset range, it means that there may be a design problem in the circuit simulation model, so the circuit analysis device optimizes the design of the component model or the connection relationship between the component models in the circuit simulation model. Alternatively, the circuit analysis device redesigns the circuit simulation model.

[0176] S56, based on at least two analysis indicators, performing a circuit worst-case analysis on the redesigned or optimized circuit simulation model to obtain an optimization analysis result corresponding to each analysis indicator.

[0177] Similarly, the circuit analysis device performs a circuit worst-case analysis on the optimized or redesigned circuit simulation model based on at least two analysis indicators to obtain an optimized analysis result corresponding to each analysis indicator.

[0178] S57, verifying the current sampling and protection circuit according to at least two optimization analysis results.

[0179] The above scheme uses at least two analysis methods to determine at least two analysis indicators, improves the comprehensiveness of the worst-case analysis of the circuit, further, based on at least two analysis indicators, performs the worst-case analysis of the circuit on the circuit simulation model, obtains the analysis result corresponding to each analysis indicator, and further, uses at least two analysis results to verify the current sampling and protection circuit. The worst-case analysis method for the current sampling and protection circuit provided by the present application determines the analysis indicators through different analysis methods, and improves the comprehensiveness of the worst-case analysis of the current sampling and protection circuit.

[0180] Furthermore, the analysis results obtained from the simulation are used to carry out actual tests, and the test results are used to verify the analysis results to improve the confidence of the analysis.

[0181] See also Figure 2 , Figure 2 It is a flow chart of another embodiment of the worst-case analysis method for current sampling and protection circuit provided by the present application.

[0182] like Figure 2 As shown, another embodiment of the worst-case analysis method for current sampling and protection circuit provided by the present application may specifically include the following steps:

[0183] S101, obtaining performance analysis conditions.

[0184] S102, obtaining analysis indicators.

[0185] S103, dividing the circuit module.

[0186] S104, establishing a simulation circuit model and confirming whether analysis can be performed.

[0187] If the judgment result is yes, the process jumps to S105. If the judgment result is no, the process jumps to S110.

[0188] S105, selecting key circuit parameters.

[0189] S106, simulation analysis.

[0190] S107, output simulation results, and perform sampling test and verification.

[0191] S108: Are the two results consistent?

[0192] If the judgment result is yes, jump to S109. If the judgment result is no, jump to S111.

[0193] S109, whether the indicators are qualified.

[0194] If the judgment result is yes, jump to S112. If the judgment result is no, jump to S111.

[0195] S110, perform a comprehensive boundary test and jump to S109.

[0196] S111, optimize design or redesign. Jump to S101.

[0197] S112, end.

[0198] In this embodiment, it is first necessary to clarify the conditions for worst-case performance analysis, which is derived from the overall design requirements of the project or from certain functions defined in the electronic component specification.

[0199] Based on these analysis conditions, with the help of the worst-case analysis indicators to be obtained, the circuit modules are disassembled and segmented (such as analog circuits, digital circuits, digital-analog circuits, etc.). After the smallest unit of the circuit is extracted, the simulation circuit can be built with reference to the existing circuit modules, the key parameters to be tested can be selected, and the simulation can be run.

[0200] Finally, the simulation results of the circuit are verified with the results of the randomly selected boundary test and fault input test. If the difference is large, the circuit design is redesigned or optimized; if the results of the random selection verification are basically consistent with the simulation results, the experimental data is output and archived. If a specific simulation model in the circuit cannot be provided by the original manufacturer, it is obtained by finding the most similar device in the existing model library and modifying the parameters. For very few devices that do not have simulation models, comprehensive circuit parameter boundary tests, fault injection tests, etc. are carried out to confirm the input and output indicators of the performance, so as to obtain relevant data.

[0201] Refer to the worst-case performance analysis conditions of the project input requirements, and obtain the worst-case analysis conditions (i.e. the performance analysis conditions mentioned above) and analysis indicators through FMEA, HARA, FTA, expert evaluation, fault library information, etc., as shown in the following table:

[0202]

[0203] The worst-case analysis method for the current sampling and protection circuit provided in this embodiment uses a circuit simulation model such as Figure 3 As shown, Figure 3 U28 is an operational amplifier, and U29A and U29B are comparators. Pin 1 of U28 is the positive input terminal (+), pin 2 is the negative input terminal (-), pin 50 is grounded (GND), pin 45 is the output terminal (Vout), and pin 99 is the input terminal (VCC). Pin 1 of U29 is the negative input terminal (-), pin 2 is the positive input terminal (+), pin 30 is the output terminal (Vout), pin 55 is grounded (GND), and pin 44 is the input terminal (VCC).

[0204] Specifically, the circuit analysis device simulates different simulation requirements by setting different excitation source variables and related parameters.

[0205] In some embodiments, the parameters of V4 (DC Sweep) are set to perform simulation analysis on the DC gain.

[0206] In some embodiments, the parameters of V5 (AC Sweep) are set to simulate and analyze the cutoff frequency / AC gain / phase current sampling delay / phase current sampling phase shift excitation source.

[0207] In some embodiments, the parameters of V6 (Time Domain) are set to perform simulation analysis on stress analysis / current-overshoot threshold of normal sampling.

[0208] In some embodiments, the parameters of V2 are set to perform corresponding simulation analysis on the sinusoidal overcurrent.

[0209] In some embodiments, the parameters of V7 are set to perform corresponding simulation analysis on the step overcurrent.

[0210] In the component stress analysis phase, the circuit analysis device makes the following boundary agreements:

[0211] (1) Set the power supply of the op amp / comparator to 5±0.2V.

[0212] (2) High temperature is 105°C.

[0213] (3) The derating factors of resistors, capacitors, operational amplifiers and comparators are shown in the following table. For other parameters not mentioned above, the derating factor is doubled according to the GJB / Z35 standard.

[0214]

[0215] Furthermore, in the simulation parameter settings of the component stress analysis link, the +5VA / 5V network is set to 5V, the input source VOFF is 2.5V, VAMPL is 2.5V, FREQ is 1.2k, and AC / PHASE is 0. The simulation settings are Time Domain, high temperature 105℃; PSpice / Advanced Analysis / Smoke is used to run and display the component stress distribution of the circuit.

[0216] from Figure 4 It can be seen that after the circuit resistors and capacitors are set to the third-level derating factor and the op amp / comparator is set to the second-level derating factor, the temperature stress on the resistor components is the greatest under high temperature conditions, with a maximum temperature rise of 5°C, approaching 89% of the derating.

[0217] In the DC gain analysis phase, the following boundary conventions are made:

[0218] (1) ACI_W_IN input is 0~5V.

[0219] (2) Low temperature -40℃ / normal temperature 27℃ / high temperature 105℃.

[0220] (3) The DC gain of the current sampling circuit is 0db±1mdB.

[0221] Furthermore, the circuit analysis device is set up as follows and simulated:

[0222] (1) Set the resistance and capacitance tolerance.

[0223] (2) The simulation is set to DC Sweep, low temperature -40℃ / normal temperature 27℃ / high temperature 105℃. Monte Carlo analysis is selected and run. The simulation ends after several minutes and the processed data 1 is obtained;

[0224] (3) Select the worst-case analysis, set Fide to the maximum difference YMAX when running with the nominal value, set the tolerance change mode to DEV&LOT, and set the Worst-Case direction to the increasing direction Hi / decreasing direction Low respectively; the simulation ends after several minutes, and the processed data 2 is obtained.

[0225] (4) Sensitivity analysis (set 40 points) and Monte Carlo analysis (set 400 uniformly distributed points) in PSpice / Advanced Analysis.

[0226] (5) After calling the relevant functions, run the sensitivity analysis and Monte Carlo analysis again; the simulation ends after several minutes, and the processed data 3 and processed data 4 are obtained.

[0227] Furthermore, the Monte Carlo analysis results are as follows Figure 5 As shown, from Figure 5 It can be seen that temperature has little effect on DC gain, and DC gain G is constant at about -605udB. The square, diamond, inverted triangle, regular triangle, +, ×, herringbone, Y, and * in the figure represent the simulation results of the input signal (ACI_W_IN1) running 1, 2, 3, ... until the 400th time.

[0228] The worst-case analysis results are as follows: Figure 6 and Figure 7 As shown by Figure 6 and Figure 7 It can be seen that the temperature has little effect on the DC gain, and the DC gain is constant at -606u~-602udB. Therefore, the worst case is -606udB, and not less than -602udB. Among them, Figure 6 The six groups of data in the table represent the simulated output values ​​of the input signal (ACI_W_IN1) at -40℃(Hi), -40℃(Nom), 25℃(Hi), 25℃(Nom), 105℃(Hi), and 105℃(Nom) respectively. Figure 7 The 6 groups of data in the table represent the simulated output values ​​of the input signal (ACI_W_IN1) at -40℃(Low), -40℃(Nom), 25℃(Low), 25℃(Nom), 105℃(Low), and 105℃(Nom). Hi is the case where the resistance and capacitance parameter indicators shift upward, Nom is the case where the resistance and capacitance parameter indicators do not change, and Low is the case where the resistance and capacitance parameter indicators shift downward.

[0229] The sensitivity analysis results are as follows Figure 8 As shown, when all the resistance and capacitance parameter values ​​change by 1%, the relative sensitivity of R440 to DC gain is +44.2ndB, and the relative sensitivity of R439 to DC gain is +31.8ndB.

[0230] Furthermore, the circuit analysis device uses a signal generator to input a DC voltage with a stable voltage to the input end of the current sampling channel of the board under test, and uses a multimeter to measure and record the input and output voltages of the sampling circuit, respectively, to obtain the measured results in the following table.

[0231]

[0232] In some embodiments, in the AC overall waveform analysis phase, the following boundary conventions are adopted:

[0233] (1) The AC source is set as follows:

[0234] Output signal Peak-to-Peak DC bias Sweep range Frequency points Stepping method Sine Wave 5Vpp 2.5V 1Hz~1MHz 50 Log

[0235] (2) Low temperature -40℃ / normal temperature 27℃ / high temperature 105℃.

[0236] (3) The cut-off frequency does not exceed xx_kHz. xx_kHz can be adjusted according to actual conditions.

[0237] (4) The maximum gain of 2kHz AC does not exceed -xx_mdB. -xx_mdB can be adjusted according to actual conditions.

[0238] (5) The maximum delay of 2kHz AC does not exceed xx_us. xx_us can be adjusted according to actual conditions.

[0239] (6) The maximum phase shift of 2kHz AC does not exceed xx_°. Among them, xx_° can be adjusted according to actual conditions.

[0240] In some embodiments, during the AC overall waveform analysis simulation implementation process, the following operations are performed:

[0241] (1) Set the resistance and capacitance tolerance.

[0242] (2) Set the simulation to AC Sweep and select Monte Carlo / Worst-Case;

[0243] (3) Set the low temperature to -40℃ / normal temperature to 27℃ / high temperature to 105℃ and run;

[0244] (4) After the simulation is completed after several minutes, the data is processed.

[0245] The simulation results are as follows: Fig. 9 As shown. Among them, Fig. 9 The square, diamond, inverted triangle, regular triangle, circle, and + in the above table correspond to the simulation output values ​​of the delay signal (G) at -40℃(Hi), -40℃(Nom), 25℃(Hi), 25℃(Nom), 105℃(Hi), and 105℃(Nom), respectively. Fig.10 The square, diamond, inverted triangle, equilateral triangle, circle, and + in the table correspond to the simulated output values ​​of the phase shift signal (P) at -40℃(Hi), -40℃(Nom), 25℃(Hi), 25℃(Nom), 105℃(Hi), and 105℃(Nom), respectively. Fig. 9 The square, diamond, inverted triangle, regular triangle, circle, and + in the table below correspond to the simulated output values ​​of the gain signal (DB) at -40℃ (Hi), -40℃ (Nom), 25℃ (Hi), 25℃ (Nom), 105℃ (Hi), and 105℃ (Nom). Hi refers to the case where the RC parameter index shifts upward, Nom refers to the case where the RC parameter index does not change, and Low refers to the case where the RC parameter index shifts downward.

[0246] In some embodiments, in the cutoff frequency analysis simulation phase, the following boundary conventions are adopted:

[0247] (1) The AC source is set as follows:

[0248] Output signal Peak-to-Peak DC bias Sweep range Frequency points Stepping method Sine Wave 5Vpp 2.5V 1Hz~1MHz 50 Log

[0249] (2) Low temperature -40℃ / normal temperature 27℃ / high temperature 105℃.

[0250] (3) The cut-off frequency of the circuit does not exceed xx_kHz, where xx can be adjusted according to actual conditions.

[0251] In some embodiments, during the implementation of the cutoff frequency analysis simulation, the following operations are performed:

[0252] (1) Set the resistance and capacitance tolerance;

[0253] (2) The simulation settings are DC Sweep, low temperature -40℃ / normal temperature 27℃ / high temperature 105℃;

[0254] (3) Select Monte Carlo analysis and run it. After several minutes of simulation, the processed data 1 is obtained.

[0255] (4) Select the worst case analysis, set Fide to the maximum difference YMAX when running with the nominal value, set the tolerance change mode to DEV&LOT, and set the worst case analysis direction to increase direction Hi / decrease direction Low. The simulation ends after several minutes, and the processed data 2 is obtained.

[0256] (5) Sensitivity analysis (set 40 points) and Monte Carlo analysis (set 400 uniformly distributed points) in PSpice / Advanced Analysis.

[0257] (6) After Measurement calls the relevant functions, it runs the sensitivity analysis and Monte Carlo analysis again. After several minutes of simulation, processed data 3 and processed data 4 are obtained respectively.

[0258] The Monte Carlo analysis results are as follows Fig.10 and Fig.11 As shown, the minimum cutoff frequency appears at low temperature (the 101st point), which is 14.5kHz, and the maximum cutoff frequency appears at normal temperature (the 574th point), which is 18.2kHz. Fig.10 The inverted triangle, equilateral triangle, +, ×, herringbone, Y-shape, and * represent simulation diagrams in which the gain DB is run 1st, 2nd, 3rd, ... 400th times respectively.

[0259] The worst-case analysis results are as follows: Fig.12 and Fig.13 As shown, Fig.12 The square, diamond, inverted triangle, regular triangle, circle, and + in the figure represent the simulated output values ​​of the gain DB signal at -40℃(Hi), -40℃(Nom), 25℃(Hi), 25℃(Nom), 105℃(Hi), and 105℃(Nom), respectively. Fig.13 The square, diamond, inverted triangle, regular triangle, circle, and + in the figure represent the simulated output values ​​of the gain DB signal at 40℃(Low), -40℃(Nom), 25℃(Low), 25℃(Nom), 105℃(Low), and 105℃(Nom) respectively. Hi is the case where the resistance and capacitance parameter indicators shift upward, Nom is the case where the resistance and capacitance parameter indicators do not change, and Low is the case where the resistance and capacitance parameter indicators shift downward.

[0260] Depend on Fig.12 and Fig.13 It can be seen that the cutoff frequency is 14.4k~18.1kHz at low temperature, 14.5k~18.3kHz at normal temperature, and 14.5k~18.2kHz at high temperature. Therefore, the worst case occurs at low temperature, at which time it is 14.4kHz and does not exceed 18.3kHz.

[0261] The sensitivity analysis results are as follows Fig.14 As shown, the relative sensitivity of R436 to the cutoff frequency is -167.4835Hz / 1%, and the relative sensitivity of C500 to the cutoff frequency is -161.4162Hz / 1%. The tolerance parameters of other components can be ignored.

[0262] In some embodiments, in the 2kHz AC gain analysis phase, the following boundary convention is used:

[0263] (1) The AC source is set as follows:

[0264] Output signal Peak-to-Peak DC bias Sweep range Frequency points Stepping method Sine Wave 5Vpp 2.5V 1Hz~1MHz 50 Log

[0265] (2) Low temperature -40℃ / normal temperature 27℃ / high temperature 105℃.

[0266] (3) The maximum gain of 2kHz AC does not exceed -xx_mdB. Among them, xx can be adjusted according to actual conditions.

[0267] In some embodiments, during the 2kHz AC gain analysis simulation implementation process, the following operations are performed:

[0268] (1) RC tolerance setting;

[0269] (2) The simulation settings are AC Sweep, low temperature -40℃ / normal temperature 27℃ / high temperature 105℃.

[0270] (3) Select Monte Carlo analysis and run it. After several minutes of simulation, the processed data 1 is obtained.

[0271] (4) Select the worst-case analysis, set Fide to the maximum difference YMAX when running with the nominal value, set the tolerance change mode to DEV&LOT, and set the worst-case analysis direction to increase direction Hi / decrease direction Low respectively; the simulation ends after several minutes, and the processed data 2 is obtained.

[0272] (5) Sensitivity analysis (set 40 points) and Monte Carlo analysis (set 400 uniformly distributed points) in PSpice / Advanced Analysis.

[0273] (6) After Measurement calls the relevant functions, it runs the sensitivity analysis and Monte Carlo analysis again. After several minutes of simulation, processed data 3 and processed data 4 are obtained respectively.

[0274] The Monte Carlo analysis results are as follows Fig.15 and Fig.16 As shown, the minimum gain occurs at low temperature (point 26), which is -100.5mdB, and the maximum gain occurs at high temperature (point 1039), which is -205.5mdB. Fig.15 The inverted triangle, equilateral triangle, O, +, ×, herringbone, Y-shape, and * respectively represent the simulation results of the gain DB running 1, 2, 3, ... until the 400th time.

[0275] The worst-case analysis results are as follows: Fig.17 and Fig.18 As shown, Fig.17 The square, diamond, inverted triangle, equilateral triangle, circle, and + in the figure represent the simulated output values ​​of the gain DB signal at -40℃(Hi), -40℃(Nom), 25℃(Hi), 25℃(Nom), 105℃(Hi), and 105℃(Nom), respectively. Fig.18 The square, diamond, inverted triangle, regular triangle, circle, and + in the figure represent the simulated output values ​​of the gain DB signal at -40℃(Low), -40℃(Nom), 25℃(Low), 25℃(Nom), 105℃(Low), and 105℃(Nom) respectively. Hi is the case where the resistance and capacitance parameter indicators shift upward, Nom is the case where the resistance and capacitance parameter indicators do not change, and Low is the case where the resistance and capacitance parameter indicators shift downward.

[0276] Depend on Fig.17 and Fig.18It can be seen that the AC gain at 2k is -99m~-132mdB at low temperature, -142m~-175mdB at normal temperature, and -173m~-206mdB at high temperature. Therefore, the worst case occurs at high temperature, which is -206mdB and not less than -99mdB.

[0277] The sensitivity analysis results are as follows Fig.19 As shown, C500 / R436 has the largest relative sensitivity to AC gain. The relative sensitivity of C500 to AC gain is 1.37mdB / 1%, and the relative sensitivity of R436 to AC gain is 1.3467mdB / 1%. The tolerance parameters of other components can be ignored.

[0278] In some embodiments, in the 2kHz sampling delay analysis phase, the following boundary conventions are adopted:

[0279] (1) The AC source is set as follows:

[0280] Output signal Peak-to-Peak DC bias Sweep range Frequency points Stepping method Sine Wave 5Vpp 2.5V 1Hz~1MHz 50 Log

[0281] (2) Low temperature -40℃ / normal temperature 27℃ / high temperature 105℃.

[0282] (3) The 2kHz sampling delay does not exceed xx_us. Among them, xx can be adjusted according to the actual situation.

[0283] In some embodiments, the following operations are performed during the simulation implementation process of the 2kHz sampling delay analysis:

[0284] (1) Set the resistance and capacitance tolerance;

[0285] (2) The simulation settings are AC Sweep, low temperature -40℃ / normal temperature 27℃ / high temperature 105℃;

[0286] (3) Select Monte Carlo analysis and run it. After several minutes of simulation, the processed data 1 is obtained.

[0287] (4) Select the worst-case analysis, set Fide to the maximum difference YMAX when running with the nominal value, set the tolerance change mode to DEV&LOT, and set the worst-case analysis direction to increase direction Hi / decrease direction Low respectively; the simulation ends after several minutes, and the processed data 2 is obtained.

[0288] (5) Sensitivity analysis (set 40 points) and Monte Carlo analysis (set 400 uniformly distributed points) in PSpice / Advanced Analysis.

[0289] (6) After Measurement calls the relevant functions, it runs the sensitivity analysis and Monte Carlo analysis again. After several minutes of simulation, processed data 3 and processed data 4 are obtained respectively.

[0290] The Monte Carlo analysis results are as follows Fig. 20 and Fig.21 As shown, the minimum sampling delay occurs at low temperature (the 26th point), which is 10.8us; the maximum sampling delay occurs at high temperature (the 874th point), which is 14.2us. Fig.23 The diamond, inverted triangle, equilateral triangle, O, +, ×, herringbone, Y-shape, and * respectively represent the simulation results of delay G running 1 time, 2 times, 3 times... until the 1200th time.

[0291] The worst-case analysis results are as follows: Fig. 22 and Fig.23 As shown, Fig. 22 The square, diamond, inverted triangle, regular triangle, circle, and + in the figure represent the simulation output values ​​of the delayed G signal at -40℃(Hi), -40℃(Nom), 25℃(Hi), 25℃(Nom), 105℃(Hi), and 105℃(Nom), respectively. Fig.23 The square, diamond, inverted triangle, regular triangle, circle, and + in the figure represent the simulated output values ​​of the delayed G signal at -40℃(Low), -40℃(Nom), 25℃(Low), 25℃(Nom), 105℃(Low), and 105℃(Nom) respectively. Hi is the case where the resistance and capacitance parameter indicators shift upward, Nom is the case where the resistance and capacitance parameter indicators do not change, and Low is the case where the resistance and capacitance parameter indicators shift downward.

[0292] Depend on Fig. 22 and Fig.23 It can be seen that the 2k delay is 10.7u~13.2us at low temperature, 11.7u~13.7us at normal temperature, and 12.1u~14.2us at high temperature. Therefore, the worst case occurs at high temperature, which is 14.2us and not less than 10.7us.

[0293] The sensitivity analysis results are as follows Fig.24 As shown, it can be seen that the influence of component tolerance parameters on sampling delay can be ignored.

[0294] In some embodiments, in the 2kHz AC gain analysis phase, the following boundary convention is used:

[0295] (1) The AC source is set as follows:

[0296] Output signal Peak-to-Peak DC bias Sweep range Frequency points Stepping method Sine Wave 5Vpp 2.5V 1Hz~1MHz 50 Log

[0297] (2) Low temperature -40℃ / normal temperature 27℃ / high temperature 105℃.

[0298] (3) The maximum phase shift of 2kHz AC does not exceed -xx_°. Among them, xx can be adjusted according to actual conditions.

[0299] In some embodiments, during the 2kHz sampling phase shift analysis simulation implementation process, the following operations are performed:

[0300] (1) RC tolerance setting.

[0301] (2) The simulation settings are AC Sweep, low temperature -40℃ / normal temperature 27℃ / high temperature 105℃.

[0302] (3) Select Monte Carlo analysis and run it. After several minutes of simulation, the processed data 1 is obtained.

[0303] (4) Select the worst-case analysis, set Fide to the maximum difference YMAX when running with the nominal value, set the tolerance change mode to DEV&LOT, and set the worst-case analysis direction to increase direction Hi / decrease direction Low respectively; the simulation ends after several minutes, and the processed data 2 is obtained.

[0304] (5) Sensitivity analysis (set 40 points) and Monte Carlo analysis (set 400 uniformly distributed points) in PSpice / Advanced Analysis.

[0305] (6) After Measurement calls the relevant functions, it runs the sensitivity analysis and Monte Carlo analysis again. After several minutes of simulation, processed data 3 and processed data 4 are obtained respectively.

[0306] The Monte Carlo analysis results are as follows Fig.25 and Fig.26 As shown. Among them, Fig.25 The diamond, inverted triangle, equilateral triangle, O, +, ×, herringbone, Y-shape, and * respectively represent the simulation results of the phase-shifted P signal running 1 time, 2 times, 3 times, and so on until the 400th time.

[0307] from Fig.25 and Fig.26 It can be seen that the minimum phase shift occurs at a low temperature (the 26th point), which is 8.9°, and the maximum phase shift also occurs at a low temperature (the 74th point), which is 10.7°.

[0308] The worst-case analysis results are as follows: Fig. 27 and Fig.28 As shown. Among them, Fig. 27The square, diamond, inverted triangle, equilateral triangle, circle, and + in the figure represent the simulated output values ​​of the phase-shifted P signal at -40℃(Hi), -40℃(Nom), 25℃(Hi), 25℃(Nom), 105℃(Hi), and 105℃(Nom), respectively. Fig.28 The square, diamond, inverted triangle, regular triangle, circle, and + in the figure represent the simulated output values ​​of the phase shift P signal at -40℃(Low), -40℃(Nom), 25℃(Low), 25℃(Nom), 105℃(Low), and 105℃(Nom) respectively. Hi is the case where the RC parameter index shifts upward, Nom is the case where the RC parameter index does not change, and Low is the case where the RC parameter index shifts downward.

[0309] Depend on Fig. 27 and Fig.28 It can be seen that the phase shift at 2k is 8.1-9.9° at low temperature, 8.8-10.2° at room temperature, and 9.1-10.5° at high temperature. Therefore, the worst case occurs at high temperature, at which point it is 10.5° and not less than 8.1°.

[0310] The sensitivity analysis results are as follows Fig.29 As shown, the relative sensitivity of R436 to 2kHz phase shift is +70.7142m degrees / 1%, and the relative sensitivity of C500 to 2kHz phase shift is +70.6737m degrees / 1%. The tolerance parameters of other components can be ignored.

[0311] In some embodiments, in the protection point threshold analysis phase, the following boundary conventions are adopted:

[0312] (1) The AC source is set as follows:

[0313] Output signal Peak-to-Peak DC bias Sweep range Frequency points Stepping method Sine Wave 5Vpp 2.5V 1Hz~1MHz 50 Log

[0314] (2) Low temperature -40℃ / normal temperature 27℃ / high temperature 105℃.

[0315] (3) The ACI_L overcurrent protection point threshold does not exceed ±xx_mV. Among them, xx_mV can be adjusted according to actual conditions.

[0316] (4) The ACI_H overcurrent protection point threshold does not exceed ±xx_mV. Among them, xx_mV can be adjusted according to actual conditions.

[0317] In some embodiments, during the protection point threshold analysis simulation implementation process, the following operations are performed:

[0318] (1) RC tolerance setting;

[0319] (2) The simulation settings are AC Sweep, low temperature -40℃ / normal temperature 27℃ / high temperature 105℃.

[0320] (3) Select Monte Carlo analysis and run it. After several minutes of simulation, the processed data 1 is obtained.

[0321] (4) Select the worst-case analysis, set Fide to the maximum difference YMAX when running with the nominal value, set the tolerance change mode to DEV&LOT, and set the worst-case analysis direction to increase direction Hi / decrease direction Low respectively; the simulation ends after several minutes, and the processed data 2 is obtained.

[0322] (5) Sensitivity analysis (set 40 points) and Monte Carlo analysis (set 400 uniformly distributed points) in PSpice / Advanced Analysis.

[0323] (6) After Measurement calls the relevant functions, it runs the sensitivity analysis and Monte Carlo analysis again. After several minutes of simulation, processed data 3 and processed data 4 are obtained respectively.

[0324] The Monte Carlo analysis results corresponding to ACI_L are as follows Fig.30 and Fig.31 As shown, Fig.30 The diamond, inverted triangle, equilateral triangle, O, +, ×, herringbone, Y, and * respectively represent the simulation results of V(ACI_L) running 1, 2, 3, ... until the 400th time.

[0325] Depend on Fig.30 and Fig.31 It can be seen that the minimum ACI_L deviation occurs at low temperature (point 113), which is -4.1 mV. The maximum ACI_L deviation also occurs at low temperature (point 292), which is 7.5 mV.

[0326] The sensitivity analysis results corresponding to ACI_L are as follows Fig.32 As shown in the figure, the relative sensitivity of R432 / R429 / R430 to ACI_L deviation is +3.5289mV / 1%, -1.8219mV / 1%, -1.4581mV / 1%, respectively. The tolerance parameters of other components can be ignored.

[0327] The Monte Carlo analysis results corresponding to ACI_H are as follows Fig.33 and Fig.34 As shown, Fig.33 The diamond, inverted triangle, equilateral triangle, O, +, ×, herringbone, Y-shape, and * respectively represent the simulation results of V(ACI_H) running 1, 2, 3, ... until the 400th time.

[0328] Depend on Fig.33 and Fig.34 It can be seen that the minimum ACI_H deviation occurs at low temperature (point 266), which is -18.3 mV, and the maximum ACI_H deviation also occurs at low temperature (point 140), which is 23.5 mV.

[0329] The sensitivity analysis results corresponding to ACI_H are as follows Fig.35 As shown in the figure, the relative sensitivity of R429 / R430 to ACI_H deviation is -12.4510mV / 1% and +9.1142mV / 1% respectively. The tolerance parameters of other components can be ignored.

[0330] In the actual measurement phase, the circuit simulation device uses a network analyzer to test the AC gain, circuit delay, and phase characteristics of the sampling channel to be tested and records them. The test is performed three times in a row and the average value of the three times is taken.

[0331] The network analyzer uses the following parameter settings:

[0332] Output signal Peak-to-Peak DC bias Sweep range Frequency step Stepping method Sine 5Vpp 2.5V 50Hz~2kHz 50Hz Log

[0333] The test data shown in the following table are obtained. These test data are the measured results of the above AC overall ripple diagram analysis, cutoff frequency analysis, 2kHz AC gain analysis, 2kHz sampling delay analysis, 2kHz sampling phase shift analysis, and protection point threshold.

[0334] Frequency / Hz Gain / dB Phase / ° Delay / us Frequency / Hz Gain / dB Phase / ° Delay / us 50 -0.141 -0.236 13.13 1050 -0.146 -4.231 11.19 100 -0.125 -0.429 11.91 1100 -0.155 -4.465 11.09 150 -0.124 -0.631 11.68 1150 -0.156 -4.659 11.25 200 -0.127 -0.83 11.53 1200 -0.158 -4.856 11.24 250 -0.126 -1.034 11.49 1250 -0.149 -4.991 11.09 300 -0.123 -1.23 11.39 1300 -0.157 -5.222 11.16 350 -0.122 -1.433 11.37 1350 -0.155 -5.39 11.09 400 -0.117 -1.63 11.32 1400 -0.15 -5.541 10.99 450 -0.119 -1.822 11.25 1450 -0.151 -5.724 10.97 500 -0.13 -2.021 11.23 1500 -0.152 -5.906 11.07 550 -0.133 -2.248 11.35 1550 -0.167 -6.179 11.16 600 -0.129 -2.453 11.36 1600 -0.178 -6.426 11.07 650 -0.132 -2.636 11.27 1650 -0.175 -6.578 11.07 700 -0.127 -2.84 11.27 1700 -0.178 -6.773 11.03 750 -0.132 -3.018 11.18 1750 -0.179 -6.951 11.01 800 -0.131 -3.23 11.22 1800 -0.18 -7.135 11.07 850 -0.143 -3.418 11.17 1850 -0.189 -7.371 11.07 900 -0.143 -3.656 11.29 1900 -0.193 -7.571 11.04 950 -0.149 -3.867 11.31 1950 -0.194 -7.752 11.04 1000 -0.144 -4.035 11.21 2000 -0.202 -7.982 11.09

[0335] In some embodiments, in the overcurrent detection delay analysis phase, the following boundary conventions are adopted:

[0336] (1) The AC source is set as follows:

[0337] Output signal Peak-to-Peak DC bias Sweep range Frequency points Stepping method Sine Wave 5Vpp 2.5V 1Hz~1MHz 50 Log

[0338] (2) Low temperature -40℃ / normal temperature 27℃ / high temperature 105℃.

[0339] (3) The delay of the sinusoidal signal does not exceed xx_ns. xx_ns can be set according to actual needs.

[0340] (4) The step signal delay does not exceed xx_ns. xx_ns can be set according to actual needs.

[0341] In some embodiments, during the overcurrent detection delay analysis simulation implementation process, the following operations are performed:

[0342] (1) RC tolerance setting;

[0343] (2) The simulation settings are AC Sweep, low temperature -40℃ / normal temperature 27℃ / high temperature 105℃.

[0344] (3) Select Monte Carlo analysis and run it. After several minutes of simulation, the processed data 1 is obtained.

[0345] (4) Select the worst-case analysis, set Fide to the maximum difference YMAX when running with the nominal value, set the tolerance change mode to DEV&LOT, and set the worst-case analysis direction to increase direction Hi / decrease direction Low respectively; the simulation ends after several minutes, and the processed data 2 is obtained.

[0346] (5) Sensitivity analysis (set 40 points) and Monte Carlo analysis (set 400 uniformly distributed points) in PSpice / Advanced Analysis.

[0347] (6) After Measurement calls the relevant functions, it runs the sensitivity analysis and Monte Carlo analysis again. After several minutes of simulation, processed data 3 and processed data 4 are obtained respectively.

[0348] The Monte Carlo analysis results for sinusoidal input signals can be found in Fig.36 and Fig.37 .like Fig.36 As shown in the figure, the maximum delay between the overcurrent and the output falling edge in the rising phase of the positive half cycle at low temperature (point 140) is 1.99us. Fig.43 As shown, the maximum delay between the negative half cycle falling phase and the output rising phase at low temperature (325th point) is 2.35us.

[0349] The worst-case analysis results for a sinusoidal input signal can be found in Fig.38 and Fig.39 .like Fig.38 As shown in the figure, the overcurrent and output falling edge delay in the rising stage of the normal / high / low temperature positive half cycle are all 0.7u~2.3us. Fig.39 As shown, the delay between the negative half cycle falling stage and the output rising stage at low temperature is 0.13u~0.41us, and 0.41u~2.2us at normal temperature. Therefore, the worst case occurs at low temperature, which is 2.3us, and not less than 0.13us.

[0350] The sensitivity analysis results for sinusoidal input signals can be found in Fig.40 and Fig.41 .like Fig.40 As shown in the figure, R429 / R430 has a delay of -822.452ns / 1% and +608.6195ns / 1% for the overcurrent and output falling edge of the positive half-cycle rising stage. Fig.41As shown in the figure, R429 / R430 have a negative half-cycle falling phase overcurrent and output rising edge delay of -57.2452ns / 1% and 1.1574us / 1% respectively. The tolerance parameters of other components can be ignored.

[0351] The Monte Carlo analysis results for the step input signal can be found in Fig.42 and Fig.43 .like Fig.42 As shown in the figure, the maximum delay between overcurrent and output falling edge in the rising stage at normal temperature (point 540) is 323ns. Fig.43 As shown, the maximum delay between the low temperature (32nd point) falling stage and the output rising stage is 360ns.

[0352] The worst-case analysis results for a step input signal can be found in Fig.44 and Fig.45 .like Fig.44 As shown, the delay between overcurrent and output falling edge in the rising stage is 273.7n~319.1ns at low temperature and 313.6n~325.1ns at normal temperature. Fig.45 As shown, the delay between the falling stage and the output rising stage is 314.1n~324.6ns at low temperature and 313.2n~324.5ns at normal temperature. Therefore, the worst case occurs at normal temperature, which is 324.5ns and not less than 273.7ns.

[0353] The sensitivity analysis results corresponding to the step input signal can be found in Fig.46 and Fig.47 .like Fig.46 As shown in the figure, the relative sensitivity of R441 to overcurrent in the rising stage and output falling edge delay is +762.0111fs / 1%. Fig.47 As shown, the delay of the falling phase and the output rising phase of R429 / R430 are -2.7636ns / 1% and +2.0893ns / 1% respectively.

[0354] Before the test, use a signal generator to input a 2.5V±0.1V DC voltage signal to the ACI_OC_W_IN port (DC output mode of the signal generator). After the test starts, manually change the output voltage of the signal generator to make it jump to 4.5V±0.05V (positive current overcurrent) or 0V±0.05V (negative current overcurrent). The time difference between the input signal edge and the signal level jump edge is the circuit step delay. Fig.48 As shown, the step signal delay is 174ns.

[0355] Furthermore, manually change the signal generator ACI_OC_W_IN to input a sine wave. At this time, the circuit outputs a rectangular wave. Use the oscilloscope cursor function to test the minimum time difference between the jump edge of the output rectangular wave and the moment when the positive half-cycle voltage of the input waveform reaches the "input voltage corresponding to the overcurrent point" in the previous test item, and the minimum time difference between the jump edge of the rectangular wave and the moment when the negative half-cycle voltage of the input waveform reaches the "input voltage corresponding to the overcurrent point" in the previous test item, which is the overcurrent detection delay time. Fig.49 As shown, the sinusoidal signal is delayed by 761ns.

[0356] The above scheme uses at least two analysis methods to determine at least two analysis indicators, improves the comprehensiveness of the worst-case analysis of the circuit, further, based on at least two analysis indicators, performs the worst-case analysis of the circuit on the circuit simulation model, obtains the analysis result corresponding to each analysis indicator, and further, uses at least two analysis results to verify the current sampling and protection circuit. The worst-case analysis method for the current sampling and protection circuit provided by the present application determines the analysis indicators through different analysis methods, and improves the comprehensiveness of the worst-case analysis of the current sampling and protection circuit.

[0357] Furthermore, the analysis results obtained from the simulation are used to carry out actual tests, and the test results are used to verify the analysis results to improve the confidence of the analysis.

[0358] Please continue to see Fig.50 , Fig.50 The terminal device 500 of the embodiment of the present application includes a processor 51 and a memory 52 .

[0359] The processor 51 and the memory 52 are connected to the bus. The memory 52 stores program data. The processor 51 is used to execute the program data to implement the current sampling and worst-case analysis method for the protection circuit described in the above embodiment.

[0360] In the embodiment of the present application, the processor 51 may also be referred to as a CPU (Central Processing Unit). The processor 51 may be an integrated circuit chip having the ability to process signals. The processor 51 may also be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), or other programmable logic devices, discrete gates or transistor logic devices, or discrete hardware components. A general-purpose processor may be a microprocessor or the processor 51 may also be any conventional processor, etc.

[0361] This application also provides a computer storage medium, please continue to refer to Fig.51 , Fig.51 It is a structural diagram of an embodiment of a computer storage medium provided in the present application. The computer storage medium 600 stores program data 61. When the program data 61 is executed by the processor, it is used to implement the worst-case analysis method for current sampling and protection circuit of the above embodiment.

[0362] When the embodiments of the present application are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including several instructions to enable a computer device (which can be a personal computer, a server, or a network device, etc.) or a processor to perform all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a disk or an optical disk.

Claims

1. A worst-case analysis method for current sampling and protection circuit, characterized in that: The method comprises: Obtain at least two analysis indicators and obtain a circuit simulation model corresponding to the current sampling and protection circuit; wherein the at least two analysis indicators are determined by at least two of a fault tree analysis method, a potential failure mode impact and consequence analysis method, a hazard analysis and risk assessment analysis method, an expert experience assessment method, and fault library information; Based on the at least two analysis indicators, performing a circuit worst-case analysis on the circuit simulation model to obtain an analysis result corresponding to each analysis indicator; The current sampling and protection circuit is verified according to at least two of the analysis results.

2. The method according to claim 1, characterized in that The obtaining of at least two analysis indicators includes: Obtaining performance analysis conditions of the current sampling and protection circuit; Based on the performance analysis conditions, the at least two analysis indicators are determined.

3. The method according to claim 2, characterized in that The determining of the at least two analysis indicators based on the performance analysis condition includes: Obtaining at least two groups of candidate analysis results corresponding to the fault tree analysis method, the potential failure mode impact and consequence analysis method, the hazard analysis and risk assessment analysis method, the expert experience assessment method, and the fault library information in the performance analysis conditions; the candidate analysis results include candidate analysis indicators and candidate indicator scores corresponding to the candidate analysis indicators; A weighted sum of the scores of the at least two groups of candidate indicators is calculated to obtain an analysis indicator score, and the at least two analysis indicators are determined from the at least two groups of candidate analysis indicators using the analysis indicator score.

4. The method according to claim 1, characterized in that The performing of a circuit worst-case analysis on the circuit simulation model based on the at least two analysis indicators to obtain an analysis result corresponding to each analysis indicator includes: Dividing the circuit simulation model into components to obtain component models corresponding to a number of components; Based on the at least two analysis indicators, a circuit worst-case analysis is performed on each of the component models to obtain a local analysis result corresponding to each component under each analysis indicator; The analysis result is obtained by utilizing all the local analysis results under the same analysis index.

5. The method according to claim 4, characterized in that After the step of dividing the circuit simulation model into components to obtain component models corresponding to a number of components, the method further comprises: In response to the fact that the simulation model library does not contain a component model corresponding to the target component, a candidate component model corresponding to a similar component similar to the target component is obtained in the simulation model library, the specification parameters of the candidate component model are modified, and the modified candidate component model is used as the target component model corresponding to the target component.

6. The method according to claim 1, characterized in that The verifying the current sampling and protection circuit according to at least two of the analysis results comprises: Selecting at least some of the analysis indicators, and performing a circuit worst-case test on the current sampling and protection circuit based on the at least some of the analysis indicators to obtain an actual test result; In response to the analysis result being within a preset range, the current sampling and protection circuit is verified according to at least two of the analysis results; the preset range is determined based on the actual test result.

7. The method according to claim 6, characterized in that After the step of selecting at least part of the analysis indicators, and performing a circuit worst-case test on the current sampling and protection circuit based on at least part of the analysis indicators to obtain actual test results, the method further comprises: In response to the analysis result being outside the preset range, optimizing or redesigning the circuit simulation model; Based on the at least two analysis indicators, a circuit worst-case analysis is performed on the redesigned or optimized circuit simulation model to obtain an optimization analysis result corresponding to each analysis indicator; The current sampling and protection circuit is verified according to at least two of the optimization analysis results.

8. The method according to claim 1, characterized in that The circuit worst-case analysis includes at least one of sensitivity analysis, component thermal and electrical stress analysis, Monte Carlo analysis, and extreme value stress analysis.

9. A terminal device, characterized in that: The terminal device includes a processor and a memory connected to the processor, wherein: The memory stores program instructions; The processor is configured to execute program instructions stored in the memory to implement the method according to any one of claims 1 to 8.

10. A computer-readable storage medium, characterized in that: The storage medium stores program instructions, and when the program instructions are executed, the method according to any one of claims 1 to 8 is implemented.

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