Manufacturing method of patch type fuse and patch type fuse

Abstract

The invention provides a manufacturing method of a patch type fuse and the patch type fuse, and the manufacturing method of the patch type fuse comprises the steps: obtaining a substrate, and enabling the surface of at least one side of the substrate to be covered with a metal layer in a preset shape; pressing another substrate on one side, with the metal layer in the preset shape, of the substrate to form a laminated plate, and slotting two sides of the laminated plate to expose the metal layer in the preset shape; heat-resistant sheet layers are laminated on the end faces of the two sides of the laminated plate to form a whole plate; and performing trepanning treatment on the whole plate in an area outside the metal layer in the preset shape so as to form a plurality of uniformly distributed through holes in the whole plate. By means of the mode, the situations of hole wall breakage and alignment deviation are effectively reduced, the layer deviation risk of the patch type fuse is avoided, and the preparation efficiency of the patch type fuse is improved.

Description

Technical Field

[0001] The present application is applied to the technical field of fuses, and in particular relates to a method for manufacturing a chip fuse and the chip fuse. Background Art

[0002] With the rapid development of the electronics industry, electronic products have made rapid progress in miniaturization and integration, which has put forward higher requirements for the design of electronic devices. Among them, SMD fuses have the advantages of rich specifications, small size, and convenient assembly. Fuses play an important role in preventing electrical disasters. Their main function is to prevent excessive current from flowing through electronic circuits. Therefore, they are widely used in electronic power products.

[0003] However, in the prior art, when producing chip fuses, multiple layers of copper clad laminates are mostly used for alignment and pressing, and the fuse alloy wires are buried between the multiple layers of copper clad laminates manually or by equipment. That is, when producing chip fuses, poor hole wall continuity, high risk of breakage, and alignment deviation are prone to occur. In addition, the use of equipment or manual wire embedding greatly increases the preparation cost of the chip fuse, and the preparation efficiency is low. Summary of the invention

[0004] The present application provides a method for manufacturing a chip fuse to solve the problem that the risk of layer deviation is prone to occur in the existing manufacturing of chip fuses.

[0005] To solve the above technical problems, the first aspect of the present application provides a method for manufacturing a chip fuse, comprising: obtaining a substrate, at least one side of which is covered with a metal layer of a preset shape; pressing another substrate on the side of the substrate with the metal layer of the preset shape to form a stacked plate, and slotting both sides of the stacked plate to expose the metal layer of the preset shape; laminating heat-resistant sheet layers on both side end surfaces of the stacked plate to form a whole plate; and performing a hole opening process on the whole plate outside the area of ​​the metal layer of the preset shape to form a plurality of evenly arranged through holes on the whole plate.

[0006] Among them, the step of obtaining a substrate, wherein at least one side surface of the substrate is covered with a metal layer of a preset shape includes: forming a metal layer on the substrate; etching the metal layer on the substrate to form a metal layer of a preset shape on the substrate.

[0007] The steps before laminating the heat-resistant sheet layers on both side end surfaces of the stacked plate to form the whole plate include: tinning on the metal layer of the preset shape to form a tin layer on the metal layer of the preset shape.

[0008] Among them, after the step of performing hole opening processing on the entire board in the area outside the preset shape metal layer to form a number of evenly arranged through holes on the entire board, it includes: copper plating the entire board to form a copper layer on the through holes and the entire board; etching the end surfaces on both sides of the entire board to form a preset layer on the entire board; tinning the preset layer to form a soldering pad.

[0009] Among them, the steps of pressing another substrate on one side of the substrate with a preset shape metal layer to form a stacked plate, and grooving both sides of the stacked plate to expose the preset shape metal layer include: grooving the end faces of both sides of the stacked plate in the area corresponding to the preset shape metal layer to form a notch on the stacked plate, wherein the planar size of the notch is larger than the planar size of the preset shape metal layer.

[0010] Among them, the steps after performing hole opening processing on the entire plate outside the preset shape metal layer to form a number of evenly arranged through holes on the entire plate include: forming a mark on at least one side end surface of the heat-resistant sheet layer, wherein the mark corresponds to the preset shape metal layer.

[0011] Among them, the steps after performing hole opening processing on the entire plate outside the area of ​​the preset shape metal layer to form a number of evenly arranged through holes on the entire plate include: cutting the entire plate along the axial direction of the opening to form a single fuse, wherein the preset shape metal layer is sealed in the entire plate.

[0012] The opening is located in the extension direction of the metal layer of the preset shape.

[0013] Wherein, the substrate is a semi-cured sheet.

[0014] In order to solve the above problem, the second aspect of the present application provides a chip fuse, wherein the chip fuse is prepared by any of the above methods for preparing a chip fuse.

[0015] The beneficial effects of the present application are as follows: different from the prior art, the present application forms a laminate by covering a preset-shaped metal layer on a substrate, and pressing another substrate on one side of the substrate with the preset-shaped metal layer, slotting the laminate, and then laminating heat-resistant sheet layers on both side end surfaces of the laminate, and drilling holes in areas outside the preset-shaped metal layer, so that the hole wall of the through hole formed between the preset-shaped metal layer and the substrate is continuous, effectively reducing the occurrence of hole wall fracture and alignment offset, so that the chip fuse has no risk of layer deviation, and improves the preparation efficiency of the chip fuse. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 It is a flow chart of an embodiment of a method for manufacturing a chip fuse of the present application;

[0017] Figure 2 This application Figure 1 S11 is a flow chart of an embodiment;

[0018] Figure 3 This application Figure 1 A schematic diagram of a process flow of an embodiment after step S14;

[0019] Figure 4 This application Figure 1 A schematic diagram of the cross-sectional structure after step S11 is completed;

[0020] Figure 5 This application Figure 1 A schematic diagram of the top view of the structure after step S11 is completed;

[0021] Figure 6 This application Figure 1 A schematic diagram of the cross-sectional structure of the stacked plates after step S12 is completed;

[0022] Figure 7 It is a schematic diagram of the cross-sectional structure of the stacked plate of the present application with a notch;

[0023] Figure 8 It is a schematic diagram of a top view of the structure in which a notch is provided on the stacked plate of the present application;

[0024] Fig. 9 It is a schematic diagram of the cross-sectional structure of a nickel layer disposed on a metal layer of a preset shape in the present application;

[0025] Fig.10 This application Figure 1 Schematic diagram of the cross-sectional structure of the whole board after step S13 is completed;

[0026] Fig.11 This application Figure 1 Schematic diagram of the cross-sectional structure of the whole board after step S14 is completed;

[0027] Fig.12 This application Figure 1 A schematic diagram of the top view of the entire board after step S14 is completed;

[0028] Fig.13 This application Figure 3 Schematic diagram of the cross-sectional structure of the whole board after step S15 is completed;

[0029] Fig.14 This application Figure 3 Schematic diagram of the cross-sectional structure of the whole board after step S16 is completed;

[0030] Fig.15 It is a schematic diagram of the cross-sectional structure of the entire board of this application where the logo is set;

[0031] Fig.16 This application Figure 3Schematic diagram of the cross-sectional structure of the whole board after step S17 is completed;

[0032] Fig.17 It is a schematic diagram of the cross-sectional structure of the chip fuse of the present application;

[0033] Fig.18 It is a schematic diagram of the top view of the chip fuse of the present application. DETAILED DESCRIPTION

[0034] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0035] It should be noted that if the embodiments of the present application involve directional indications (such as up, down, left, right, front, back...), the directional indications are only used to explain the relative position relationship, movement status, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0036] In addition, if there are descriptions involving "first", "second", etc. in the embodiments of the present application, the descriptions of "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or suggesting their relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In addition, the technical solutions between the various embodiments can be combined with each other, but they must be based on the ability of ordinary technicians in the field to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such combination of technical solutions does not exist and is not within the scope of protection required by this application.

[0037] See also Figure 1 , Figure 1 1 is a flow chart of an embodiment of a method for manufacturing a SMD fuse provided by the present application. It should be noted that if there is substantially the same result, the method of the present invention is not limited to Figure 1 The process sequence shown is limited. Figure 1 As shown, the method comprises the following steps:

[0038] S11: obtaining a substrate 10 , wherein at least one surface of the substrate 10 is covered with a metal layer 20 of a preset shape.

[0039] In an optional embodiment, if Figure 4 As shown, Figure 4 yes Figure 1The schematic diagram of the cross-sectional structure after step S11 is completed, and combined with Figure 5 As shown, Figure 5 yes Figure 1 A schematic diagram of the cross-sectional structure after step S11 is completed. A substrate 10 is obtained, and a metal layer 20 of a preset shape is formed on at least one side surface of the substrate 10. Specifically, the substrate 10 can be covered with a metal layer 20 of a preset shape on at least one side surface of the substrate 10 by an electroplating process. The thickness of the metal layer 20 of the preset shape can be set according to the actual situation according to customer requirements by electroplating the metal to a preset thickness through an electroplating process, and this application does not make specific limitations here.

[0040] In this embodiment, the preset shape metal layer 20 covered on the substrate 10 can be specifically a plurality of uniformly parallel strip-shaped metal layers, and the plurality of preset shape metal layers 20 are arranged at intervals, that is, the plurality of strip-shaped metal layers are arranged in a matrix, and each strip-shaped metal layer is arranged at intervals, so that a plurality of SMD fuses are prepared on one substrate 10, which is convenient for the subsequent direct division of the substrate 10 to realize the preparation of a plurality of SMD fuses. In other embodiments, the preset shape metal layers 20 can be arranged continuously along the length direction of the substrate 10, and arranged in parallel along the width direction of the substrate 10, and the intervals between the preset shape metal layers 20 can be set according to specific process requirements, and can also be set according to user requirements, and this application does not make specific limitations here.

[0041] The substrate 10 may be a prepreg sheet or a resin material. The reinforcing material is impregnated with a resin adhesive and is made by drying, cutting, laminating, and other processes. The material of the preset shape metal layer 20 may include, but is not limited to, copper, aluminum, magnesium, tin, zinc, or other alloys, and the present application does not make specific limitations here.

[0042] S12 : Laminating another substrate 10 on the side of the substrate 10 with the metal layer 20 of the preset shape to form a laminate 30 , and slotting two sides of the laminate 30 to expose the metal layer 20 of the preset shape.

[0043] In an optional embodiment, if Figure 6 As shown, Figure 6 yes Figure 1 After the metal layer 20 of the preset shape is formed on the substrate 10, another substrate 10 is laminated on the side of the substrate 10 with the metal layer 20 of the preset shape, thereby forming a stacked plate 30, the specific structure of which is "substrate-metal layer-substrate". Figure 7 and Figure 8 As shown, Figure 7 It is a schematic diagram of the cross-sectional structure of the notch on the stacked plate. Figure 81 is a schematic diagram of a top view of a structure in which a notch is formed on a stack. That is, after the stack 30 is formed by lamination, the stack 30 is notched. Specifically, the two side end surfaces of the stack 30 are notched by laser ablation, so that the metal layer 20 of a preset shape is exposed on both side end surfaces of the stack 30 through the substrate 10 on both sides, so as to form a notch 101 on the stack 30.

[0044] In this embodiment, grooves are formed on the end faces of the stacking plate 30 on both sides of the area corresponding to the preset shape metal layer 20 to form a notch 101 on the stacking plate 30, so that the preset shape metal layer 20 is perpendicular to the axial direction of the notch 101. The plane size of the notch 101 is larger than the plane size of the preset shape metal layer 20, that is, a notch 101 is opened on the substrate 10 to penetrate the substrates 10 on both sides, and the number of notches 101 opened corresponds to the number of the preset shape metal layers 20, that is, one preset shape metal layer corresponds to one notch 101, and several notches 101 are not connected, and several notches 101 are evenly spaced, and the plane size of the notch 101 is larger than the plane size of the preset shape metal layer 20, for example, the preset shape metal layer 20 is evenly arranged along the length direction of the substrate 10. For example, at this time, there are several preset shape metal layers 20, and the notches 101 correspond to the number of metal layers of the preset shape metal layers 20. When the notches 101 are opened, the size of the notches 101 in the width direction of the substrate 10 is larger than the size of the preset shape metal layer 20, so that the two sides of the preset shape metal layer 20 are not connected to the side walls of the notches 101, and in the length direction, the preset shape metal layer 20 is connected to the side walls of the notches 101, and the preset shape metal layer 20 is laminated between the two layers of the substrate 10 in the length direction, so as to clamp and fix the preset shape metal layer 20.

[0045] The method of performing grooving on the substrate 10 is not limited to laser ablation, and may also be laser cutting, ion cutting or water jet cutting, etc., which is not specifically limited in the present application.

[0046] S13: Laminating the heat-resistant sheet layer 40 on both side end surfaces of the stacked plate 30 to form a whole plate 50 .

[0047] Specifically, Fig.10 As shown, Fig.10 yes Figure 1Schematic diagram of the cross-sectional structure of the whole plate after step S13 is completed. After a plurality of notches 101 are opened in the area corresponding to the preset shape metal layer 20 of the stack 30, a heat-resistant sheet layer 40 is laminated on both side end surfaces of the substrate 10, wherein the size of the heat-resistant sheet layer 40 is the same as that of the substrate 10, so that the heat-resistant sheet layer 40 completely covers the substrate 10, thereby sealing the plurality of notches 101 opened on the substrate 10, thereby completely sealing the preset shape metal layer 20 inside the notch 101. The heat-resistant sheet layer 40 is laminated on both side end surfaces of the stack 30 to form a whole plate 50.

[0048] In an optional embodiment, if Fig. 9 As shown, before laminating the heat-resistant sheet layer 40 on both side end surfaces of the stacked plate 30 , tin plating is required on the preset shape metal layer 20 to form a tin layer 201 on the preset shape metal layer 20 . Thus, the preset shape metal layer 20 is wrapped by the tin layer 201 .

[0049] S14 : performing a hole opening process on the entire board 50 in the area outside the metal layer 20 of the preset shape, so as to form a plurality of evenly arranged through holes 102 on the entire board 50 .

[0050] like Fig.11 and Fig.12 As shown, Fig.11 yes Figure 1 Schematic diagram of the cross-sectional structure of the entire board after step S14 is completed. Fig.12 This application Figure 1 Schematic diagram of the top view of the whole board after step S14 is completed. In an optional embodiment, after the whole board 50 is formed, a hole is opened in the area outside the preset shape metal layer 20 on the whole board 50, so as to form a plurality of through holes 102 arranged in a plurality of ways on the whole board 50, so as to connect external devices after the subsequent preparation of the surface mount fuse, and by drilling directly on the whole board 50, there will be no offset between the preset shape metal layer 20 and the substrate 10, that is, one-time drilling is used to make the hole wall between the preset shape metal layer 20 and the substrate 10 continuous, which effectively reduces the occurrence of hole wall breakage and alignment offset.

[0051] In this embodiment, drilling is performed in an area outside the preset shape metal layer 20 on the whole plate 50, wherein the preset shape metal layer 20 is uniformly arranged along the length direction of the substrate 10 as an example, and a groove 101 is formed in the area corresponding to the preset shape metal layer 20, and the through hole 102 opened on the whole plate 50 is located in the area outside the preset shape metal layer 20, and is located in the area outside the groove 101, and the specific opening is located in the extension direction of the preset shape metal layer 20, so that when drilling, the preset shape metal layer 20 is connected to the hole wall of the through hole 102, the through hole 102 is not connected to the groove 101, and the preset shape metal layer 20 corresponds to the through hole 102.

[0052] Through the above method, by covering the preset shape metal layer 20 on the substrate 10, and pressing another substrate 10 on the side of the substrate 10 with the preset shape metal layer 20 to form a stacked plate 30, the stacked plate 30 is grooved and then the heat-resistant sheet layer 40 is laminated on the end surfaces of both sides of the stacked plate 30, and drilling is performed in the area outside the preset shape metal layer 20, so that the hole wall of the through hole 102 formed between the preset shape metal layer 20 and the substrate 10 is continuous, which effectively reduces the occurrence of hole wall fracture and alignment offset, so that the chip fuse has no risk of layer deviation and improves the preparation efficiency of the chip fuse.

[0053] Please refer to Figure 2 , Figure 2 yes Figure 1 Specifically, the above S11 may further include the following steps:

[0054] S111 : forming a metal layer on the substrate 10 .

[0055] In this embodiment, a substrate 10 is obtained, and a metal layer is laminated on at least one side of the substrate 10. The area of ​​the metal layer is the same as the area of ​​the substrate 10, that is, at least one side of the substrate 10 is completely covered with a metal layer.

[0056] S112 : etching the metal layer on the substrate 10 to form a metal layer 20 with a preset shape on the substrate 10 .

[0057] In an optional embodiment, a photodevelopment and etching method may be used. For example, a resist dry film is applied to the metal layer of the substrate 10, and the resist dry film is exposed and developed, thereby exposing the metal layer in the area outside the preset shape metal layer 20. On this basis, the metal layer in the area outside the exposed preset shape metal layer 20 is etched, thereby forming the preset shape metal layer 20 on the substrate 10. Specifically, a layer of resist dry film is covered on the surface of the substrate 10 with the metal layer, and the resist dry film is exposed and developed, that is, the resist dry film that has not undergone polymerization reaction after exposure is washed away by a developer, thereby exposing the metal layer in the area outside the preset shape metal layer 20, and then the metal layer in the area outside the exposed preset shape metal layer 20 is completely etched and removed by an etching solution. In other embodiments, the metal layer on the substrate 10 may also be prepared into the preset shape metal layer 20 by mechanical processing, which is not specifically limited in this application.

[0058] Please refer to Figure 3 , Figure 3 yes Figure 1Specifically, the above step S14 may further include the following steps:

[0059] S15 : copper plating is performed on the entire board 50 to form a copper layer 60 on the through hole 102 and the entire board 50 .

[0060] like Fig.13 As shown, Fig.13 yes Figure 3 Schematic diagram of the cross-sectional structure of the whole board after the step S15 is completed. In this embodiment, after executing step S14, that is, after drilling a hole 102 in an area other than the preset shape metal layer 20 on the whole board 50, a copper layer 60 can be plated on the surface of the opposite sides of the whole board 50 and the inner wall of the through hole 102 by electroplating or evaporation. In other embodiments, the copper layer 60 can also be plated on the whole board 50 or the inner wall of the through hole 102 by chemical deposition or black shadow heating, which is not specifically limited in this application. Among them, the thickness of the copper layer 60 formed on the whole board 50 can be controlled by controlling the processing parameters of chemical deposition, evaporation, electroplating and other processing methods.

[0061] S16 : etching is performed on both side end surfaces of the entire plate 50 to form a preset layer 601 on the entire plate 50 .

[0062] like Fig.14 As shown, Fig.14 yes Figure 3 After forming the copper layer 60 on the whole board 50 and the inner wall of the through hole 102, etching is performed on both side surfaces of the whole board 50 to form a preset layer 601, which is the same as the above step S112 and will not be described in detail here.

[0063] In this embodiment, before etching, the through holes 102 on the entire board 50 can be plugged with resin, and the resin on the entire board 50 can be leveled to remove excess resin on the surface of the entire board 50, so that the entire board 50 has flatness, thereby preventing the copper layer 60 inside the through holes 102 from being removed when etching the end surfaces on both sides of the entire board 50, and also facilitating the formation of a preset layer 601 on the entire board 50.

[0064] S17 : Tinning is performed on the preset layer 601 to form a soldering pad 80 .

[0065] Specifically, Fig.16 As shown, Fig.16 yes Figure 3 After forming the preset layer 601 on the whole board 50, the whole board 50 is tinned to form a pad 80, so that the prepared SMD fuse can be connected to an external device.

[0066] In this embodiment, if Fig.15 As shown, after forming the preset layer 601, that is, before tinning the preset layer 601 to form the solder pad 80, a mark 70 can be formed on at least one side end surface of the heat-resistant sheet layer 40 to correspond to the numbered chip fuse, wherein the mark 70 corresponds to the preset shape metal layer 20.

[0067] In an optional embodiment, if Fig.17 and Fig.18 As shown, Fig.17 It is a schematic diagram of the cross-sectional structure of a chip fuse. Fig.18 : is a schematic diagram of the top view of the structure of the chip fuse. After the pad 80 is formed on the preset layer 601, the whole plate 50 can be cut along the axial direction of the opening to form a single fuse, and the whole plate 50 can be cut perpendicularly to the axial direction of the preset shape metal layer 20, and cut along the axial direction of the preset shape metal layer 20 at the symmetrical positions of the two spaced notches 101, so as to cut out a number of chip fuses 90. Specifically, taking the method of uniformly arranging the preset shape metal layer 20 along the length direction of the substrate 10 as an example, the cutting is performed in the axial direction of the axial through hole 102 and perpendicular to the axial direction of the preset shape metal layer 20, and the cutting is performed in the same direction parallel to the length direction of the substrate 10 at the symmetrical positions of the two preset shape metal layers 20, wherein the preset shape metal layer 20 is sealed in the whole plate 50.

[0068] Based on the general inventive concept, Fig.17 and Fig.18 As shown, the present application further provides a chip fuse 90, wherein the chip fuse 90 is prepared by the manufacturing method of the chip fuse as described in any one of the above items.

[0069] Different from the prior art, the manufacturing method of the chip fuse 90 in the present application includes: obtaining a substrate 10 with a preset-shaped metal layer 20, and pressing another substrate 10 on one side of the substrate 10 with the preset-shaped metal layer 20 to form a laminate 30, slotting the laminate 30 to expose the preset-shaped metal layer 20, and laminating a heat-resistant sheet layer 40 on both side end surfaces of the laminate 30 to form a whole plate 50, on this basis, opening a hole on the whole plate 50 in the area outside the preset-shaped metal layer 20, and cutting the whole plate 50 along the axial direction of the opening, so as to cut out a number of chip fuses 90. The hole wall of the through hole 102 formed between the preset-shaped metal layer 20 and the substrate 10 can be made continuous, effectively reducing the occurrence of hole wall fracture and alignment offset, so that the chip fuse 90 has no layer deviation risk, and improves the production efficiency of the chip fuse 90.

[0070] The above description is only an implementation method of the present application, and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly used in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A method for manufacturing a chip fuse, characterized in that: The manufacturing method of the chip fuse comprises: Obtaining a substrate, wherein at least one side surface of the substrate is covered with a metal layer of a preset shape; Laminating another substrate on one side of the substrate with the metal layer of the preset shape to form a stacked plate, and slotting two sides of the stacked plate to expose the metal layer of the preset shape; Laminating heat-resistant sheets on both side end surfaces of the stacked plate to form a whole plate; A hole opening process is performed on the entire board in areas outside the preset shape metal layer to form a plurality of evenly arranged through holes on the entire board.

2. The method for manufacturing a chip fuse according to claim 1, characterized in that: The step of obtaining a substrate, wherein at least one side of the substrate is covered with a metal layer of a preset shape comprises: forming a metal layer on the substrate; The metal layer on the substrate is etched to form the metal layer with a preset shape on the substrate.

3. The method for manufacturing a chip fuse according to claim 1, characterized in that: The steps before laminating the heat-resistant sheet layers on both side end surfaces of the stacked plate to form a whole plate include: Tin plating is performed on the metal layer of the preset shape to form a tin layer on the metal layer of the preset shape.

4. The method for manufacturing a chip fuse according to claim 1, characterized in that: After the step of performing a hole opening process on the entire board in the area outside the preset shape metal layer to form a plurality of evenly arranged through holes on the entire board, the step includes: Copper plating the entire board to form a copper layer on the through hole and the entire board; Etching is performed on both side end surfaces of the whole plate to form a preset layer on the whole plate; Tinning is performed on the preset layer to form a soldering pad.

5. The method for manufacturing a chip fuse according to claim 1, characterized in that: The step of pressing another substrate on one side of the substrate with the metal layer of the preset shape to form a laminate, and grooving both sides of the laminate to expose the metal layer of the preset shape comprises: Grooving is performed on both side end surfaces of the stacked plate in the area corresponding to the preset shape metal layer to form a notch on the stacked plate, wherein the plane size of the notch is larger than the plane size of the preset shape metal layer.

6. The method for manufacturing a chip fuse according to claim 1, characterized in that: The step after performing hole opening processing on the entire board in the area outside the preset shape metal layer to form a plurality of evenly arranged through holes on the entire board includes: A mark is formed on at least one end surface of the heat-resistant sheet layer, wherein the mark corresponds to the metal layer of the preset shape.

7. The method for manufacturing a chip fuse according to claim 1, characterized in that: The step after performing hole opening processing on the entire board in the area outside the preset shape metal layer to form a plurality of evenly arranged through holes on the entire board includes: The whole plate is cut along the axial direction of the opening to form a single fuse, wherein the metal layer of the preset shape is sealed in the whole plate.

8. The method for manufacturing a chip fuse according to claim 1, characterized in that: The opening is located in an extension direction of the metal layer of the preset shape.

9. The method for manufacturing a chip fuse according to claim 1, characterized in that: The substrate is a prepreg sheet.

10. A chip fuse, characterized in that: The chip fuse is prepared by the manufacturing method of the chip fuse according to any one of claims 1 to 9.

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