Power device and preparation method thereof, power module, power conversion circuit and vehicle

Abstract

The invention discloses a power device and a preparation method thereof, a power module, a power conversion circuit and a vehicle. The power device comprises the following steps: providing a silicon carbide substrate; forming a silicon carbide epitaxial layer on one side of the silicon carbide substrate; growing at least one silicon film layer on one side, far away from the silicon carbide substrate, of the silicon carbide epitaxial layer; forming a planar tubular gate structure on one side, far away from the silicon carbide epitaxial layer, of the at least one silicon film layer; forming a planar source electrode structure on one side, far away from the silicon carbide epitaxial layer, of the at least one silicon film layer; and forming a drain on one side of the silicon carbide substrate away from the silicon carbide epitaxial layer. According to the technical scheme provided by the embodiment of the invention, the electron mobility of the planar power device is improved, and the on-resistance of the planar power device is reduced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a power device and a preparation method thereof, a power module, a power conversion circuit and a vehicle. Background Art

[0002] Compared with silicon power devices, planar silicon carbide metal-oxide field-effect transistor (SiC MOSFET) power devices have the advantages of large bandgap, high critical breakdown electric field, and high temperature resistance.

[0003] However, the process of planar silicon carbide metal-oxide field effect transistor power devices is still unstable, resulting in excessively large on-resistance of the power devices. Summary of the invention

[0004] The present invention provides a power device and a preparation method thereof, a power module, a power conversion circuit and a vehicle, so as to reduce the on-resistance of a planar power device.

[0005] According to one aspect of the present invention, there is provided a method for preparing a power device, comprising:

[0006] Providing a silicon carbide substrate;

[0007] forming a silicon carbide epitaxial layer on one side of the silicon carbide substrate;

[0008] Growing at least one silicon film layer on a side of the silicon carbide epitaxial layer away from the silicon carbide substrate;

[0009] Forming a planar gate structure on a side of the at least one silicon film layer away from the silicon carbide epitaxial layer;

[0010] Forming a planar source structure on a side of the at least one silicon film layer away from the silicon carbide epitaxial layer;

[0011] A drain is formed on a side of the silicon carbide substrate away from the silicon carbide epitaxial layer.

[0012] According to another aspect of the present invention, there is provided a power device, comprising:

[0013] Silicon carbide substrate;

[0014] A silicon carbide epitaxial layer, wherein the silicon carbide epitaxial layer is located on one side of the silicon carbide substrate;

[0015] At least one silicon film layer, wherein the at least one silicon film layer is grown on a side of the silicon carbide epitaxial layer away from the silicon carbide substrate;

[0016] A planar gate structure, wherein the planar gate structure is located on a side of the at least one silicon film layer away from the silicon carbide epitaxial layer;

[0017] A planar source structure, wherein the planar source structure is located on a side of the at least one silicon film layer away from the silicon carbide epitaxial layer;

[0018] A drain electrode is located on a side of the silicon carbide substrate away from the silicon carbide epitaxial layer.

[0019] According to another aspect of the present invention, a power module is provided, which adopts the power device described in any one of the embodiments of the present invention, and the substrate is used for carrying the power device.

[0020] According to another aspect of the present invention, there is provided a power conversion circuit, the power conversion circuit being used for one or more of current conversion, voltage conversion, and power factor correction;

[0021] The power conversion circuit includes a circuit board and at least one power device as described in any one of the embodiments of the present invention, and the power device is electrically connected to the circuit board.

[0022] According to another aspect of the present invention, a vehicle is provided, comprising a load and a power conversion circuit according to any one of the embodiments of the present invention, wherein the power conversion circuit is used to convert alternating current and / or direct current into alternating current and / or direct current and input the converted alternating current and / or direct current into the load.

[0023] In the preparation process of the planar silicon carbide metal-oxide field effect transistor power device provided by the embodiment of the present invention, before forming the planar gate structure, the planar source structure and the drain, at least one silicon film layer is grown on the side of the silicon carbide epitaxial layer away from the silicon carbide substrate. Since the silicon film layer is directly grown on the side of the silicon carbide epitaxial layer away from the silicon carbide substrate to form a Si / SiC heterojunction composed of the silicon film layer and the silicon carbide epitaxial layer, it is not necessary to form it through a wafer bonding process, which simplifies the preparation process of the Si / SiC heterojunction and reduces the preparation cost. In addition, the Si / SiC heterojunction can have ideal diode rectification characteristics and space charge modulation effects, which improves the carrier mobility of the planar silicon carbide metal-oxide field effect transistor power device and reduces the on-resistance of the planar power device.

[0024] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0026] Figure 1 is a flow chart of a method for preparing a power device provided by an embodiment of the present invention;

[0027] Figure 2-Figure 6 yes Figure 1 A schematic diagram of the structure corresponding to each step of the method for preparing a medium power device;

[0028] Figure 7 is a flow chart of another method for preparing a power device provided by an embodiment of the present invention;

[0029] Figure 8 is a flow chart of another method for preparing a power device provided by an embodiment of the present invention;

[0030] Fig. 9 is a flow chart of another method for preparing a power device provided by an embodiment of the present invention;

[0031] Figure 10-Figure 14 yes Fig. 9 A schematic diagram of the structure corresponding to each step of the method for preparing a medium power device;

[0032] Fig.15 is a flow chart of another method for preparing a power device provided by an embodiment of the present invention;

[0033] Figure 16-Figure 19 yes Fig.15 Schematic diagram of the structures corresponding to each step of the method for preparing a medium-power device. DETAILED DESCRIPTION

[0034] In order to enable those skilled in the art to better understand the solution of the present invention, the technical solution in the embodiment of the present invention will be described clearly and completely in conjunction with the drawings in the embodiment of the present invention. Obviously, the described embodiment is only a part of the embodiment of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0035] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or devices is not necessarily limited to those steps or devices that are clearly listed, but may include other steps or devices that are not clearly listed or inherent to these processes, methods, products or devices.

[0036] As described in the above background technology, the process of planar silicon carbide metal-oxide field effect transistor power devices is still unstable, resulting in excessive on-resistance of the planar power device. After careful study, the inventor found that a silicon wafer is bonded on the surface of the silicon carbide epitaxial layer of the planar silicon carbide metal-oxide field effect transistor power device to form a Si / SiC heterojunction. The Si / SiC heterojunction can improve the carrier mobility of the planar silicon carbide metal-oxide field effect transistor power device, so that the planar power device has better conduction characteristics, and the on-resistance of the planar power device can be reduced. However, the silicon wafer needs to be prepared in advance to bond the silicon wafer on the surface of the silicon carbide epitaxial layer of the planar silicon carbide metal-oxide field effect transistor power device through the bonding process, and after the Si / SiC heterojunction is formed through the wafer bonding process, high temperature annealing, cutting of the silicon wafer and other processes are required, and finally, the surface of the Si / SiC heterojunction needs to be chemically polished to reduce surface damage. The above process is cumbersome and time-consuming.

[0037] In view of the above technical problems, the present invention provides a novel method for preparing a power device. Figure 1 As shown, Figure 1 1 is a flow chart of a method for preparing a power device provided by an embodiment of the present invention, and the method for preparing a power device comprises the following steps:

[0038] S110 . Provide a silicon carbide substrate.

[0039] See also Figure 2 , a silicon carbide substrate 100 is provided.

[0040] S120 , forming a silicon carbide epitaxial layer on one side of the silicon carbide substrate.

[0041] See also Figure 2A silicon carbide epitaxial layer 101 is formed on one side of the silicon carbide substrate 100 through an epitaxial process. The preparation method of the silicon carbide epitaxial layer 101 mainly includes at least one of evaporation growth method, liquid phase epitaxy (LPE), molecular beam epitaxy (MBE) and chemical vapor deposition (CVD).

[0042] S130, growing at least one silicon film layer on a side of the silicon carbide epitaxial layer away from the silicon carbide substrate.

[0043] See also Figure 2 , at least one silicon film layer 102 is grown on the side of the silicon carbide epitaxial layer 101 away from the silicon carbide substrate 100. In this embodiment, the silicon film layer 102 is directly grown on the side of the silicon carbide epitaxial layer 101 away from the silicon carbide substrate 100 to form a Si / SiC heterojunction composed of the silicon film layer 102 and the silicon carbide epitaxial layer 101, which does not need to be formed by a wafer bonding process, thereby simplifying the preparation process of the Si / SiC heterojunction and reducing the preparation cost. In addition, the Si / SiC heterojunction can have ideal diode rectification characteristics and space charge modulation effects, thereby improving the carrier mobility of the planar silicon carbide metal-oxide field effect transistor power device and reducing the on-resistance of the planar power device.

[0044] Alternatively, if Figure 3 As shown, a body region 103 and an active region 104 are formed in a planar SiC metal-oxide field effect transistor power device by an ion implantation process, and the planar power device also includes a drift region 105. Exemplarily, the active region 104 includes a first conductivity type active region 106 and a second conductivity type active region 107.

[0045] Optionally, a silicon oxide layer can be formed on the surface of the silicon film layer 102 through an oxidation process, and then the silicon oxide layer can be removed to remove defects in the silicon film layer 102 and form a silicon film layer 102 with better conductivity, which helps to further improve the carrier efficiency of the power device.

[0046] S140, forming a planar gate structure on a side of at least one silicon film layer away from the silicon carbide epitaxial layer.

[0047] like Figure 4 As shown, a planar gate structure 108 is formed on a side of at least one silicon film layer 102 away from the silicon carbide epitaxial layer 101, and the planar gate structure 108 includes a gate dielectric layer 109 and a polysilicon gate 110. The gate dielectric layer 109 can be prepared by an atomic layer deposition (ALD) process, and the polysilicon gate 110 can be prepared by a low pressure chemical vapor deposition (LPCVD) process.

[0048] S150, forming a planar source structure on a side of at least one silicon film layer away from the silicon carbide epitaxial layer.

[0049] See also Figure 5 A planar source structure 111 is formed on a side of at least one silicon film layer 102 away from the silicon carbide epitaxial layer 101. The planar source structure 111 is composed of a source metal electrode and is connected to the active area 104. The source metal electrode can be formed by a sputtering process.

[0050] S160, forming a drain on a side of the silicon carbide substrate away from the silicon carbide epitaxial layer.

[0051] See also Figure 6 , a drain 112 is formed on a side of the silicon carbide substrate 100 away from the silicon carbide epitaxial layer 101 by a sputtering process. Exemplarily, the drain 112 includes a stack of Ti / Ni / Ag. Optionally, the silicon carbide substrate 100 may be thinned before forming the drain 112 to improve the heat dissipation performance of the power device.

[0052] In the preparation process of the planar silicon carbide metal-oxide field effect transistor power device provided by the embodiment of the present invention, before forming the planar gate structure 108, the planar source structure 111 and the drain 112, at least one silicon film layer 102 is grown on the side of the silicon carbide epitaxial layer 101 away from the silicon carbide substrate 100. Since the silicon film layer 102 is directly grown on the side of the silicon carbide epitaxial layer 101 away from the silicon carbide substrate 100 to form a Si / SiC heterojunction composed of the silicon film layer 102 and the silicon carbide epitaxial layer 101, it is not necessary to form it through a wafer bonding process, which simplifies the preparation process of the Si / SiC heterojunction and reduces the preparation cost. In addition, the Si / SiC heterojunction can have ideal diode rectification characteristics and space charge modulation effects, which improves the carrier mobility of the planar silicon carbide metal-oxide field effect transistor power device and reduces the on-resistance of the planar power device.

[0053] It should be noted that the planar silicon carbide metal-oxide field effect transistor power device provided in the embodiment of the present invention includes an N-channel planar silicon carbide metal-oxide field effect transistor power device or a P-channel planar silicon carbide metal-oxide field effect transistor power device. For the N-channel planar silicon carbide metal-oxide field effect transistor power device, the Si / SiC heterojunction improves the electron mobility of the planar silicon carbide metal-oxide field effect transistor power device and reduces the on-resistance of the planar power device. For the P-channel planar silicon carbide metal-oxide field effect transistor power device, the Si / SiC heterojunction improves the hole mobility of the planar silicon carbide metal-oxide field effect transistor power device and reduces the on-resistance of the planar power device. Exemplarily, for an N-channel planar silicon carbide metal-oxide field effect transistor power device, the silicon carbide substrate 100 is an N+ silicon carbide substrate, the silicon carbide epitaxial layer 101 is an N-silicon carbide epitaxial layer, the drift region 105 is an N-drift region, the body region 103 is a P-type body region, the first conductivity type active region 106 in the active region 104 is an N+ active region or an N++ active region, and the second conductivity type active region 107 is a P+ active region or a P++ active region. It should be particularly noted that in other embodiments, the active region 104 may also include only the first conductivity type active region 106.

[0054] Optionally, based on the above technical solution, Figure 7 As shown, Figure 7 is a flow chart of another method for preparing a power device provided by an embodiment of the present invention, wherein Figure 1 Based on the preparation method of the power device shown, Figure 7 Will Figure 1 The step S130 is further defined. Specifically, S130 growing at least one silicon film layer on a side of the silicon carbide epitaxial layer away from the silicon carbide substrate includes:

[0055] S1301, performing a heat treatment on a side of the silicon carbide epitaxial layer away from the silicon carbide substrate, so that silicon atoms in the silicon carbide epitaxial layer sublimate and re-condense to grow at least one silicon film layer on the surface of the silicon carbide epitaxial layer away from the silicon carbide substrate.

[0056] See also Figure 2, a heat treatment is performed on the side of the silicon carbide epitaxial layer 101 away from the silicon carbide substrate 100, so that the silicon atoms in the silicon carbide epitaxial layer 101 sublimate and re-condense and grow at least one silicon film layer 102 on the surface of the silicon carbide epitaxial layer 101 away from the silicon carbide substrate 100. Optionally, the side of the silicon carbide epitaxial layer 101 away from the silicon carbide substrate 100 is heated to a high temperature of 1000°C-1600°C to complete the heat treatment. In the high temperature range of 1000°C-1600°C, the silicon atoms in the silicon carbide epitaxial layer 101 sublimate and re-condense and grow at least one silicon film layer 102 on the surface of the silicon carbide epitaxial layer 101 away from the silicon carbide substrate 100. And by adjusting the heating temperature and heating time, the thickness of the silicon film layer 102 precipitated on the silicon carbide epitaxial layer 101 can be controlled, thereby meeting the planar silicon carbide metal-oxide field effect transistor power devices with different requirements.

[0057] Specifically, a heat treatment is performed on the side of the silicon carbide epitaxial layer 101 away from the silicon carbide substrate 100, so that the silicon atoms in the silicon carbide epitaxial layer 101 sublimate and re-condense and grow at least one silicon film layer 102 on the surface of the silicon carbide epitaxial layer 101 away from the silicon carbide substrate 100, so as to form a Si / SiC heterojunction consisting of the silicon film layer 102 and the silicon carbide epitaxial layer 101 in the planar silicon carbide metal-oxide field effect transistor power device, which does not need to be formed by a wafer bonding process, simplifies the preparation process of the Si / SiC heterojunction, and reduces the preparation cost. In addition, the Si / SiC heterojunction can have ideal diode rectification characteristics and space charge modulation effects, improves the carrier mobility of the planar silicon carbide metal-oxide field effect transistor power device, and reduces the on-resistance of the planar power device.

[0058] Optionally, based on the above technical solution, Figure 8 As shown, Figure 8 is a flow chart of another method for preparing a power device provided by an embodiment of the present invention, wherein Figure 1 Based on the preparation method of the power device shown, Figure 8 Will Figure 1 The step S130 is further defined. Specifically, S130 grows at least one silicon film layer on a side of the silicon carbide epitaxial layer away from the silicon carbide substrate through a film forming process, including:

[0059] S1302. Grow at least one silicon film layer on a side of the silicon carbide epitaxial layer away from the silicon carbide substrate by a film forming process, wherein the film forming process includes at least one of an atomic layer deposition process, a plasma enhanced chemical vapor deposition process, and a low pressure chemical vapor deposition process.

[0060] See also Figure 2, at least one silicon film layer 102 is grown on the side of the silicon carbide epitaxial layer 101 away from the silicon carbide substrate 100 by a film forming process. The film forming process includes at least one of an atomic layer deposition process, a plasma enhanced chemical vapor deposition (PECVD) and a low pressure chemical vapor deposition (LPCVD). Among them, the atomic layer deposition technology is a thin film preparation technology that grows layer by layer at the atomic level. The number of layers or thickness of the silicon film layer 102 can be simply determined by setting the number of continuous pulses to form a Si / SiC heterojunction consisting of a silicon film layer 102 and a silicon carbide epitaxial layer 101 in a planar silicon carbide metal-oxide field effect transistor power device, without the need for a wafer bonding process to form, thereby simplifying the preparation process of the Si / SiC heterojunction and reducing the preparation cost. In addition, the Si / SiC heterojunction can have ideal diode rectification characteristics and a space charge modulation effect, thereby improving the carrier mobility of the planar silicon carbide metal-oxide field effect transistor power device and reducing the on-resistance of the planar power device.

[0061] Optionally, based on the above technical solution, Fig. 9 As shown, Fig. 9 is a flow chart of another method for preparing a power device provided by an embodiment of the present invention, wherein Figure 1 Based on the preparation method of the power device shown, Fig. 9 Will Figure 1 The step S130 is further defined. Specifically, S130 growing at least one silicon film layer on a side of the silicon carbide epitaxial layer away from the silicon carbide substrate includes:

[0062] S1303, performing a heat treatment on a side of the silicon carbide epitaxial layer away from the silicon carbide substrate, so that silicon atoms in the silicon carbide epitaxial layer sublime and re-condense to grow a first silicon film layer on a surface of the silicon carbide epitaxial layer away from the silicon carbide substrate.

[0063] See also Fig.10 , a heat treatment is performed on the side of the silicon carbide epitaxial layer 101 away from the silicon carbide substrate 100, so that the silicon atoms in the silicon carbide epitaxial layer 101 sublime and re-condense to grow the first silicon film layer 113 on the surface of the silicon carbide epitaxial layer 101 away from the silicon carbide substrate 100. Optionally, the side of the silicon carbide epitaxial layer 101 away from the silicon carbide substrate 100 is heated to a high temperature of 1000°C-1600°C to complete the heat treatment. In the high temperature range of 1000°C-1600°C, the silicon atoms in the silicon carbide epitaxial layer 101 sublime and re-condense to grow the first silicon film layer 113 on the surface of the silicon carbide epitaxial layer 101 away from the silicon carbide substrate 100. The number of layers of the first silicon film layer 113 includes one or more layers.

[0064] S1304, growing a second silicon film layer on a surface of the first silicon film layer away from the silicon carbide epitaxial layer by a film forming process, wherein the film forming process includes at least one of an atomic layer deposition process, a plasma enhanced chemical vapor deposition process, and a low pressure chemical vapor deposition process.

[0065] See also Fig.10 The formation of the first silicon film layer 113 helps to improve the quality of the second silicon film layer 114 grown by the film forming process on the side of the silicon carbide epitaxial layer 101 away from the silicon carbide substrate 100. Atomic layer deposition technology is a thin film preparation technology that grows layer by layer at the atomic level. The number of layers or thickness of the second silicon film layer 114 can be simply determined by setting the number of continuous pulses. The formation of the first silicon film layer 113 and the second silicon film layer 114 can form a Si / SiC heterojunction consisting of the silicon film layer 102 and the silicon carbide epitaxial layer 101 in the silicon carbide metal-oxide field effect transistor power device, without the need for a wafer bonding process, which simplifies the preparation process of the Si / SiC heterojunction and reduces the preparation cost. In addition, the Si / SiC heterojunction can have ideal diode rectification characteristics and space charge modulation effects, which improves the carrier mobility of the planar silicon carbide metal-oxide field effect transistor power device and reduces the on-resistance of the planar power device.

[0066] In the above technical solution, Figure 10-Figure 14 Shows Fig. 9 Schematic diagram of the structure corresponding to the method for preparing the body region 103, the active region 104, the planar gate structure 108, the planar source structure 111 and the drain 112 in S140-S160 after the first silicon film layer 113 and the second silicon film layer 114 are formed. Figure 2-Figure 6 as well as Figure 10-Figure 14 , which shows that the preparation of the silicon film layer 102 can be completed by growing the silicon carbide epitaxial layer 101 through a film forming process and / or heating the silicon carbide epitaxial layer 101. Among them, heating the silicon carbide epitaxial layer 101 can make the silicon atoms in the silicon carbide epitaxial layer 101 sublime and re-condense and grow on the surface of the silicon carbide epitaxial layer 101 away from the silicon carbide substrate 100.

[0067] It should be noted that the silicon atoms in the silicon carbide epitaxial layer 101 are sublimated by the heat treatment and re-condensed to grow at least one silicon film layer 102 on the surface of the silicon carbide epitaxial layer 101 away from the silicon carbide substrate 100, that is, the conductivity type of the silicon film layer 102 is the same as the conductivity type of the silicon atom precipitation region. The silicon film layer 102 grown by the film forming process is an undoped silicon film layer.

[0068] Optionally, based on the above technical solution, after growing at least one silicon film layer on the side of the silicon carbide epitaxial layer away from the silicon carbide substrate in S130, and before forming a planar gate structure on the side of the at least one silicon film layer away from the silicon carbide epitaxial layer in S140, the method further includes:

[0069] An active region and a body region are formed at least in the silicon film layer by an ion implantation process.

[0070] by Figure 3 and Fig.13 For example, an active region 104 and a body region 103 are formed in at least one silicon film layer 102 by an ion implantation process.

[0071] Exemplarily, for an N-channel planar silicon carbide metal-oxide field effect transistor power device, the silicon carbide substrate 100 is an N+ silicon carbide substrate, the silicon carbide epitaxial layer 101 is an N-silicon carbide epitaxial layer, the drift region 105 is an N-drift region, the body region 103 is a P-type body region, the first conductivity type active region 106 in the active region 104 is an N+ active region or an N++ active region, and the second conductivity type active region 107 is a P+ active region or a P++ active region. It should be particularly noted that in other embodiments, the active region 104 may also include only the first conductivity type active region 106.

[0072] In the technical solution provided by the embodiment of the present invention, after at least one silicon film layer 102 is grown on the side of the silicon carbide epitaxial layer 101 away from the silicon carbide substrate 100, and before a planar gate structure 108 is formed on the side of the at least one silicon film layer 102 away from the silicon carbide epitaxial layer 101, an active region 104 and a body region 103 are formed on the surface of the silicon carbide epitaxial layer 101 away from the silicon carbide substrate 100 by an ion implantation process.

[0073] like Fig.15 As shown, Fig.15 is a flow chart of another method for preparing a power device provided by an embodiment of the present invention, wherein Figure 1 Based on the preparation method of the power device shown, Fig.15 It is further defined that before growing at least one silicon film layer 102 on a side of the silicon carbide epitaxial layer 101 away from the silicon carbide substrate 100, an active region 104 and a body region 103 are formed on a surface of the silicon carbide epitaxial layer 101 away from the silicon carbide substrate 100 by an ion implantation process. The method for preparing the power device includes the following steps:

[0074] S210 . Provide a silicon carbide substrate.

[0075] See also Fig.16 , a silicon carbide substrate 100 is provided.

[0076] S220 , forming a silicon carbide epitaxial layer on one side of the silicon carbide substrate.

[0077] See also Fig.16 A silicon carbide epitaxial layer 101 is formed on one side of the silicon carbide substrate 100 through an epitaxial process. The preparation method of the silicon carbide epitaxial layer 101 mainly includes at least one of evaporation growth method, liquid phase epitaxy (LPE), molecular beam epitaxy (MBE) and chemical vapor deposition (CVD).

[0078] S230, forming an active region and a body region on a side of the silicon carbide epitaxial layer away from the silicon carbide substrate through an ion implantation process.

[0079] See also Fig.16 , an active region 104 and a body region 103 are formed on the side of the silicon carbide epitaxial layer 101 away from the silicon carbide substrate 100 by an ion implantation process. Exemplarily, for an N-channel planar silicon carbide metal-oxide field effect transistor power device, the silicon carbide substrate 100 is an N+ silicon carbide substrate, the silicon carbide epitaxial layer 101 is an N-silicon carbide epitaxial layer, the drift region 105 is an N-drift region, the body region 103 is a P-type body region, the first conductive type active region 106 in the active region 104 is an N+ active region or an N++ active region, and the second conductive type active region 107 is a P+ active region or a P++ active region. It should be particularly noted that in other embodiments, the active region 104 may also include only the first conductive type active region 106.

[0080] S240, growing at least one silicon film layer on a side of the silicon carbide epitaxial layer away from the silicon carbide substrate.

[0081] See also Fig.17 At least one silicon film layer 102 is grown on a side of the silicon carbide epitaxial layer 101 away from the silicon carbide substrate 100 .

[0082] Optionally, the preparation of the silicon film layer 102 can be completed by growing the silicon carbide epitaxial layer 101 through a film forming process and / or heating the silicon carbide epitaxial layer 101. The heating of the silicon carbide epitaxial layer 101 can cause the silicon atoms in the silicon carbide epitaxial layer 101 to sublime and re-condense and grow on the surface of the silicon carbide epitaxial layer 101 away from the silicon carbide substrate 100.

[0083] The side of the silicon carbide epitaxial layer 101 away from the silicon carbide substrate 100 is heated so that silicon atoms in the silicon carbide epitaxial layer 101 sublime and re-condense to grow at least one silicon film layer 102 on the surface of the silicon carbide epitaxial layer 101 away from the silicon carbide substrate 100, which can be referred to S1301.

[0084] At least one silicon film layer 102 is grown on a side of the silicon carbide epitaxial layer 101 away from the silicon carbide substrate 100 by a film forming process, which may refer to S1302 .

[0085] A heat treatment is performed on the side of the silicon carbide epitaxial layer 101 away from the silicon carbide substrate 100, so that the silicon atoms in the silicon carbide epitaxial layer 101 sublime and re-condense to grow the first silicon film layer 113 on the surface of the silicon carbide epitaxial layer 101 away from the silicon carbide substrate 100, which can be referred to S1303. Then, a second silicon film layer 114 is grown by a film forming process on the surface of the first silicon film layer 113 away from the silicon carbide epitaxial layer 101, which can be referred to S1304. Among them, the formation of the first silicon film layer 113 helps to improve the quality of the second silicon film layer 114 grown by a film forming process on the side of the silicon carbide epitaxial layer 101 away from the silicon carbide substrate 100.

[0086] It should be noted that, in the present embodiment, when the silicon atoms in the silicon carbide epitaxial layer 101 are sublimated by heat treatment and re-condensed to grow a silicon film layer on the surface of the silicon carbide epitaxial layer 101 away from the silicon carbide substrate 100, the conductivity type of the silicon film layer is the same as the conductivity type of the region where the silicon atoms are precipitated.

[0087] S250, forming a planar gate structure on a side of at least one silicon film layer away from the silicon carbide epitaxial layer.

[0088] See also Fig.18 A planar gate structure 108 is formed on a side of at least one silicon film layer 102 away from the silicon carbide epitaxial layer 101 . The planar gate structure 108 includes a gate dielectric layer 109 and a polysilicon gate 110 .

[0089] S260, forming a planar source structure on a side of at least one silicon film layer away from the silicon carbide epitaxial layer.

[0090] See also Fig.19 A planar source structure 111 is formed on the side of at least one silicon film layer 102 away from the silicon carbide epitaxial layer 101. The planar source structure 111 is composed of a source metal electrode, which is connected to the active area 104 through the silicon film layer 102. The source metal electrode can be formed by a sputtering process.

[0091] S270, forming a drain on a side of the silicon carbide substrate away from the silicon carbide epitaxial layer.

[0092] See also Fig.19 A drain 112 is formed on a side of the silicon carbide substrate 100 away from the silicon carbide epitaxial layer 101 by a sputtering process.

[0093] In the technical solution provided by the embodiment of the present invention, before growing at least one silicon film layer 102 on the side of the silicon carbide epitaxial layer 101 away from the silicon carbide substrate 100, an active region 104 and a body region 103 are formed on the surface of the silicon carbide epitaxial layer 101 away from the silicon carbide substrate 100 by an ion implantation process.

[0094] An embodiment of the present invention provides a power device, such as Fig.14 and Fig.19 As shown, the power device includes: a silicon carbide substrate 100; a silicon carbide epitaxial layer 101, the silicon carbide epitaxial layer 101 is located on one side of the silicon carbide substrate 100; at least one silicon film layer 102, the at least one silicon film layer 102 is grown on the side of the silicon carbide epitaxial layer 101 away from the silicon carbide substrate 100; a planar gate structure 108, the planar gate structure 108 is located on the side of the at least one silicon film layer 102 away from the silicon carbide epitaxial layer 101; a planar source structure 111, the planar source structure 111 is located on the side of the at least one silicon film layer 102 away from the silicon carbide epitaxial layer 101; and a drain 112, the drain 112 is located on the side of the silicon carbide substrate 100 away from the silicon carbide epitaxial layer 101.

[0095] In the preparation process of the planar silicon carbide metal-oxide field effect transistor power device provided by the embodiment of the present invention, before forming the planar gate structure 108, the planar source structure 111 and the drain 112, at least one silicon film layer 102 is grown on the side of the silicon carbide epitaxial layer 101 away from the silicon carbide substrate 100. Since the silicon film layer 102 is directly grown on the side of the silicon carbide epitaxial layer 101 away from the silicon carbide substrate 100 to form a Si / SiC heterojunction composed of the silicon film layer 102 and the silicon carbide epitaxial layer 101, it is not necessary to form it through a wafer bonding process, which simplifies the preparation process of the Si / SiC heterojunction and reduces the preparation cost. In addition, the Si / SiC heterojunction can have ideal diode rectification characteristics and space charge modulation effects, which improves the carrier mobility of the planar silicon carbide metal-oxide field effect transistor power device and reduces the on-resistance of the planar power device.

[0096] Optionally, based on the above technical solution, Fig.14 As shown, an active region 104 and a body region 103 are provided in the silicon film layer 102 .

[0097] Specifically, the above structure is that after at least one silicon film layer 102 is grown on the side of the silicon carbide epitaxial layer 101 away from the silicon carbide substrate 100, and before a planar gate structure 108 is formed on the side of the at least one silicon film layer 102 away from the silicon carbide epitaxial layer 101, an active region 104 and a body region 103 are formed on the surface of the silicon carbide epitaxial layer 101 away from the silicon carbide substrate 100 through an ion implantation process.

[0098] Optionally, based on the above technical solution, Fig.19 As shown, the surface of the silicon carbide epitaxial layer 101 and the silicon carbide substrate 100 is provided with an active region 104 and a body region 103 .

[0099] Specifically, the above structure forms an active region 104 and a body region 103 on the surface of the silicon carbide epitaxial layer 101 away from the silicon carbide substrate 100 by an ion implantation process before growing at least one silicon film layer 102 on the side of the silicon carbide epitaxial layer 101 away from the silicon carbide substrate 100 .

[0100] An embodiment of the present invention provides a power module, comprising a substrate and at least one power device described in any embodiment of the present invention, wherein the substrate is used to carry the power device. Therefore, the beneficial effects of the power module including the power device described in any embodiment of the present invention are not described in detail here.

[0101] An embodiment of the present invention provides a power conversion circuit, which is used for one or more of current conversion, voltage conversion, and power factor correction; the power conversion circuit includes a circuit board and at least one power device described in any embodiment of the present invention, and the power device is electrically connected to the circuit board.

[0102] Therefore, the power conversion circuit includes the beneficial effects of any power device described in any embodiment of the present invention, which will not be repeated here.

[0103] An embodiment of the present invention further provides a vehicle, comprising a load and a power conversion circuit as described in any embodiment of the present invention, wherein the power conversion circuit is used to convert alternating current and / or direct current into alternating current and / or direct current and then input it into the load.

[0104] Therefore, the vehicle includes the power conversion circuit of any embodiment of the present invention. Therefore, the beneficial effects of the power conversion circuit described in any embodiment of the present invention are not repeated here.

[0105] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0106] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for preparing a power device, characterized in that: include: Providing a silicon carbide substrate; forming a silicon carbide epitaxial layer on one side of the silicon carbide substrate; Growing at least one silicon film layer on a side of the silicon carbide epitaxial layer away from the silicon carbide substrate; Forming a planar gate structure on a side of the at least one silicon film layer away from the silicon carbide epitaxial layer; Forming a planar source structure on a side of the at least one silicon film layer away from the silicon carbide epitaxial layer; A drain is formed on a side of the silicon carbide substrate away from the silicon carbide epitaxial layer.

2. The method for preparing a power device according to claim 1, characterized in that: Growing at least one silicon film layer on a side of the silicon carbide epitaxial layer away from the silicon carbide substrate comprises: A heat treatment is performed on a side of the silicon carbide epitaxial layer away from the silicon carbide substrate, so that silicon atoms in the silicon carbide epitaxial layer sublime and re-condense to grow at least one silicon film layer on a surface of the silicon carbide epitaxial layer away from the silicon carbide substrate.

3. The method for preparing a power device according to claim 1, characterized in that: Growing at least one silicon film layer on a side of the silicon carbide epitaxial layer away from the silicon carbide substrate by a film forming process comprises: At least one silicon film layer is grown on a side of the silicon carbide epitaxial layer away from the silicon carbide substrate by a film forming process, wherein the film forming process includes at least one of an atomic layer deposition process, a plasma enhanced chemical vapor deposition process and a low pressure chemical vapor deposition process.

4. The method for preparing a power device according to claim 1, characterized in that: Growing at least one silicon film layer on a side of the silicon carbide epitaxial layer away from the silicon carbide substrate comprises: Performing a heating treatment on a side of the silicon carbide epitaxial layer away from the silicon carbide substrate so that silicon atoms in the silicon carbide epitaxial layer sublime and re-condense to grow a first silicon film layer on a surface of the silicon carbide epitaxial layer away from the silicon carbide substrate; A second silicon film layer is grown on a surface of the first silicon film layer away from the silicon carbide epitaxial layer by a film forming process, wherein the film forming process includes at least one of an atomic layer deposition process, a plasma enhanced chemical vapor deposition process, and a low pressure chemical vapor deposition process.

5. The method for preparing a power device according to any one of claims 2 to 4, characterized in that: After growing at least one silicon film layer on a side of the silicon carbide epitaxial layer away from the silicon carbide substrate, and before forming a planar gate structure on a side of the at least one silicon film layer away from the silicon carbide epitaxial layer, the method further includes: An active region and a body region are formed at least in the silicon film layer by an ion implantation process.

6. The method for preparing a power device according to any one of claims 2 to 4, characterized in that: Before growing at least one silicon film layer on a side of the silicon carbide epitaxial layer away from the silicon carbide substrate, the method further comprises: An active region and a body region are formed on a surface of the silicon carbide epitaxial layer away from the silicon carbide substrate by an ion implantation process.

7. A power device, characterized in that: include: Silicon carbide substrate; A silicon carbide epitaxial layer, wherein the silicon carbide epitaxial layer is located on one side of the silicon carbide substrate; At least one silicon film layer, wherein the at least one silicon film layer is grown on a side of the silicon carbide epitaxial layer away from the silicon carbide substrate; A planar gate structure, wherein the planar gate structure is located on a side of the at least one silicon film layer away from the silicon carbide epitaxial layer; A planar source structure, wherein the planar source structure is located on a side of the at least one silicon film layer away from the silicon carbide epitaxial layer; A drain electrode is located on a side of the silicon carbide substrate away from the silicon carbide epitaxial layer.

8. The power device according to claim 7, characterized in that: An active region and a body region are arranged in the silicon film layer.

9. The power device according to claim 7, characterized in that: The surface of the silicon carbide epitaxial layer away from the silicon carbide substrate is provided with an active region and a body region.

10. A power module, characterized in that: It comprises a substrate and at least one power device according to any one of claims 7 to 9, wherein the substrate is used to support the power device.

11. A power conversion circuit, characterized in that: The power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction; The power conversion circuit includes a circuit board and at least one power device as described in any one of claims 7 to 9, and the power device is electrically connected to the circuit board.

12. A vehicle, characterized in that: It comprises a load and a power conversion circuit as claimed in claim 11, wherein the power conversion circuit is used to convert alternating current and / or direct current into alternating current and / or direct current and then input the converted alternating current and / or direct current into the load.

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