Processing method of substrate with metal supporting structure and chip packaging structure

Abstract

The invention relates to the technical field of chip packaging, in particular to a processing method of a substrate with a metal supporting structure and a chip packaging structure. According to the processing method, the circuit pattern is prepared on the substrate firstly, then the metal supporting structure is prepared on the circuit pattern, the metal supporting structure can support the barrier film, the barrier film is prevented from being in contact with the chip pins due to the influence of pressure, pollution caused by an effective resonance area is avoided, meanwhile, the integrity of the cavity is guaranteed, and the reliability of the chip is improved. The performance of the chip is greatly improved; the metal supporting structure can also block up the metal wire for vertical routing, so that the length of the metal wire is reduced, and the metal wire is prevented from being deformed in the resin pressing process; in addition, the metal supporting structure can also be used as a pin of the chip packaging structure, the diameter and the spacing of the pin are not affected by the process capability and the diameter of the BGA ball, the requirement of double-sided packaging of a high-density chip is met, the yield of the chip is improved, and meanwhile, the development of the chip packaging structure is greatly promoted.

Description

Technical Field

[0001] The present invention relates to the technical field of chip packaging, and in particular to a substrate processing method with a metal support structure and a chip packaging structure. Background Art

[0002] Chip packaging structure is one of the key steps in the integrated circuit (IC) manufacturing process, designed to protect the fragile silicon chip from physical damage, chemical corrosion and environmental impact, and provide a way to electrically connect to external circuit boards.

[0003] At present, the chip packaging adopts a plastic sealing layer covering the substrate to wrap the chip, and the plastic sealing layer, substrate and chip form a sealed cavity to prevent the effective resonance area of ​​the chip from being contaminated by the outside world. In order to prevent the overflowing resin from entering the cavity and contaminating the effective resonance area of ​​the chip when the resin and the substrate surface are pressed together, a barrier film is usually set between the chip and the plastic sealing layer. The edge of the barrier film is adhesively connected to the substrate. However, during the resin pressing process, the barrier film will extend downward due to the pressure, and even contact with the pins of the chip, destroying the integrity of the cavity and seriously reducing the performance of the chip.

[0004] In order to prevent electromagnetic interference between chips, metal wires are set around the chips using the vertical bonding process to enable electromagnetic shielding between chips. However, due to the thickness limitation of the chip packaging structure, the vertical bonding wires are relatively long and are easily deformed during the resin pressing process, seriously affecting the yield of the chip packaging structure.

[0005] In order to improve the integration of chips, multi-chip packaging technology has developed rapidly. In the existing technology, the integration of new disks is improved by embedding chips in substrates, but this method causes the overall thickness of the substrate to be thicker, and the chips are embedded in the substrate, which seriously affects the yield of the chips. Furthermore, double-sided packaging technology is used to package the chips, but since the pins of the chip packaging structure usually use BGA pins, the diameter and spacing of such pins are affected by the process capability and diameter of the BGA balls, and cannot meet the requirements of double-sided chip packaging. Therefore, how to solve the above problems, promote the development of chip packaging structures, and improve the yield of chip packaging structures has become an issue to be solved urgently. Summary of the invention

[0006] The embodiments of the present invention provide a substrate processing method with a metal support structure and a chip packaging structure to solve the problem of how to promote the development of the chip packaging structure and improve the yield of the chip packaging structure.

[0007] In a first aspect, the present invention provides a method for processing a substrate having a metal support structure, the processing method comprising:

[0008] Providing a copper-clad substrate;

[0009] Covering the copper-clad substrate with the first dry film having the first circuit pattern set thereon to obtain the copper-clad substrate covered with the first dry film;

[0010] Performing a first electroplating on the copper-clad substrate covered with the first dry film to obtain a substrate after the first electroplating;

[0011] Covering the substrate with a second dry film having a second circuit pattern, wherein the second circuit pattern includes a pattern of the metal support structure, to obtain a substrate covered with the second dry film;

[0012] The substrate covered with the second dry film is subjected to a second electroplating to obtain a substrate with a prepared metal support structure.

[0013] In one embodiment, after obtaining the substrate on which the metal support structure is prepared, the processing method further comprises:

[0014] Etching the substrate on which the metal support structure is prepared to obtain an etched substrate;

[0015] A solder resist layer is prepared on the etched substrate to obtain a substrate with a prepared solder resist layer.

[0016] In one embodiment, after obtaining the substrate after the first electroplating, before covering the substrate with the second dry film having the second circuit pattern, the processing method further includes:

[0017] Etching the substrate after the first electroplating to obtain a substrate with a first circuit pattern prepared thereon;

[0018] A solder resist layer is prepared on the substrate on which the first circuit pattern is prepared, so as to obtain a substrate on which the solder resist layer is prepared.

[0019] In one embodiment, after obtaining the substrate on which the solder mask layer is prepared, before covering the substrate with the second dry film on which the second circuit pattern is set, the processing method further includes:

[0020] Preparing a seed layer on the substrate on which the solder resist layer is prepared, to obtain a substrate on which the seed layer is prepared;

[0021] After the substrate covered with the second dry film is electroplated for the second time, the processing method further comprises:

[0022] The seed layer on the substrate is removed to obtain a substrate with the seed layer removed.

[0023] In one embodiment, the processing method further comprises:

[0024] Performing surface treatment on the substrate to obtain a surface-treated substrate;

[0025] Performing an appearance detection process on the substrate after the surface treatment to obtain a substrate after the appearance detection process;

[0026] Testing the substrate after the shape detection process to obtain a tested substrate;

[0027] The tested substrate is inspected to obtain an inspected substrate.

[0028] In a second aspect, the present invention provides a chip packaging structure, comprising a first chip, a barrier film, a plastic sealing layer, and a substrate with a metal support structure obtained by the processing method described in the first aspect and its embodiments, wherein the conductive pins of the first chip are electrically interconnected with the chip side of the substrate, the barrier film is arranged on the substrate, the barrier film and the substrate form a resonant cavity, the plastic sealing layer is formed on the substrate and the barrier film, the chip and the metal support structure are arranged in the resonant cavity, and the metal support structure is used to support the barrier film when the plastic sealing layer is pressed.

[0029] In one embodiment, the metal support structure is arranged on the circuit on the chip side of the substrate and / or on the pad on the chip side of the substrate, and the metal support structure is respectively arranged on the front side, the back side, the left side and the right side of the first chip.

[0030] In one embodiment, the width of the metal support structure on the circuit is smaller than the width of the circuit, and the width of the metal support structure on the pad is smaller than the width of the pad.

[0031] In a third aspect, the present invention provides a chip packaging structure, comprising a first chip, a metal layer, a plastic sealing layer, N metal wires and a substrate with a metal support structure obtained by the processing method described in the first aspect and its implementation methods, N is a natural number, the conductive pins of the first chip are electrically interconnected with the chip side of the substrate, the metal support structure is arranged on the front side, the back side, the left side and the right side of the first chip, the plastic sealing layer is formed on the substrate and the first chip, the metal layer is arranged on the plastic sealing layer, each of the metal support structures is connected to the metal wire, the other end of each of the metal wires is connected to the metal layer, and each of the metal support structures is used to raise each of the metal wires to reduce the height of each of the metal wires.

[0032] In a fourth aspect, the present invention provides a chip packaging structure, comprising a first chip, a second chip, a plastic packaging layer, and a substrate with a metal support structure obtained by the processing method described in the first aspect and its embodiments, wherein the conductive pins of the first chip are electrically interconnected with the chip side of the substrate, the conductive pins of the second chip are electrically interconnected with the pin side of the substrate, a plastic packaging layer is formed on the first chip, the substrate and the second chip, the metal support structure is arranged on the pin side of the substrate, the height of the metal support structure is higher than the plastic packaging layer on the pin side of the substrate, and the metal support structure is the pin of the chip packaging structure, and is used for electrically interconnecting the chip packaging structure with the outside.

[0033] Compared with the prior art, the embodiments of the present invention have the following beneficial effects:

[0034] The processing method of the present invention first prepares a circuit pattern on a substrate, and then prepares a metal support structure on the circuit pattern after the circuit pattern is prepared. The metal support structure can support the barrier film to prevent the barrier film from being affected by pressure and contacting the chip pins, and avoid contamination of the effective resonance area, while ensuring the integrity of the cavity, greatly improving the performance of the chip; the metal support structure can also raise the metal wires for vertical bonding, reduce the length of the metal wires, and avoid deformation of the metal wires during the resin pressing process, greatly improving the yield of the chip packaging structure; the metal support structure can also serve as the pins of the chip packaging structure, and the diameter and spacing of the pins do not need to be affected by the process capability and diameter of the BGA ball, meeting the requirements of high-density double-sided packaging of the chip, and can replace the process of burying the chip in the substrate, while improving the chip yield, greatly promoting the development of the chip packaging structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative labor.

[0036] Figure 1 It is a schematic flow chart of a method for processing a substrate with a metal support structure provided by one embodiment of the present invention; Figure 2 It is a schematic flow chart of a method for processing a substrate with a metal support structure provided by one embodiment of the present invention; Figure 3 It is a schematic flow chart of a method for processing a substrate with a metal support structure provided by one embodiment of the present invention; Figure 4It is a schematic flow chart of a method for processing a substrate with a metal support structure provided by one embodiment of the present invention; Figure 5 It is a schematic flow chart of a method for processing a substrate with a metal support structure provided by one embodiment of the present invention; Figure 6 is a schematic cross-sectional structural diagram of a chip packaging structure provided by an embodiment of the present invention; Figure 7 is a schematic diagram of a top view of a substrate provided by an embodiment of the present invention; Figure 8 is a schematic cross-sectional structural diagram of a chip packaging structure provided by an embodiment of the present invention; Fig. 9 is a schematic cross-sectional structural diagram of a chip packaging structure provided by an embodiment of the present invention; Among them, 1. a first chip, 2. a barrier film, 3. a plastic sealing layer, 4. a substrate, 5. a metal supporting structure, 6. pins of a chip packaging structure, 7. a metal layer, 8. metal wires, and 9. a second chip. DETAILED DESCRIPTION

[0047] In order to make the technical problems, technical solutions and beneficial effects solved by the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0048] In the description of the present invention, it should be understood that the terms "longitudinal", "radial", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In the description of the present invention, unless otherwise specified, "plurality" means two or more.

[0049] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0050] In order to fully understand the present invention, detailed structures and steps will be presented in the following description to illustrate the technical solutions proposed by the present invention. The preferred embodiments of the present invention are described in detail below, but in addition to these detailed descriptions, the present invention may also have other implementations.

[0051] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the disclosure belongs. It will be further understood that the terms used herein should be interpreted as having a meaning consistent with their meaning in the context of this specification and the relevant technology, and will not be interpreted in an idealized or overly formal sense unless explicitly defined as such herein.

[0052] In one embodiment, if Figure 1 As shown, a schematic flow chart of a method for processing a substrate having a metal support structure is provided, the processing method comprising:

[0053] Step S101: providing a copper-clad substrate.

[0054] The substrate is the basic material of the circuit board, which is pressed together by glass fiber cloth and epoxy resin. Blind holes and / or through holes can be prepared on the substrate according to actual application conditions, and a copper layer is prepared on the substrate with the prepared holes. It can be understood that the copper layer can be prepared by any preparation method, such as chemical copper deposition, copper electroplating, or copper sputtering.

[0055] The thickness of the copper layer and the area of ​​the copper layer can be set according to actual application conditions. The copper layer can be prepared on only one side of the substrate or on both sides of the substrate.

[0056] Step S102: Covering the copper-clad substrate with the first dry film having the first circuit pattern, to obtain the copper-clad substrate covered with the first dry film.

[0057] According to the actual application situation, a circuit pattern is set on the first dry film, and the first digi dry film is adhered to the copper-clad substrate using a film-mounting device. As another implementation method, a circuit pattern can also be set on a wet film, and the wet film can be coated on the substrate.

[0058] Step S103: performing a first electroplating on the copper-clad substrate covered with the first dry film to obtain a substrate after the first electroplating.

[0059] A copper layer is deposited on the exposed first circuit pattern portion on the copper-clad substrate covered with the first dry film by electrochemical reaction. It can be understood that this embodiment uses an additive method to prepare the first circuit pattern. As another implementation method, this embodiment can also use a subtractive method to prepare the first circuit pattern.

[0060] Step S104: Covering the substrate with a second dry film having a second circuit pattern, wherein the second circuit pattern includes a pattern of the metal support structure, to obtain a substrate covered with the second dry film.

[0061] The pattern of the metal support structure can be arranged on the first circuit, or it can be arranged at other positions of the substrate. Preferably, the metal support structure is arranged on the first circuit, and the height of the metal support structure is raised by the first circuit.

[0062] The metal support structure may have the same width as the first line thereunder, or may have a different width from the first line thereunder. Preferably, the width of the metal support structure is smaller than the width of the first line thereunder, so that the metal support structure is more stable.

[0063] It is understandable that the second dry film can be directly covered on the substrate after the first electroplating, and after the substrate covered with the second dry film is electroplated for the second time, the substrate is etched to remove the parts other than the first circuit pattern and the non-metallic support structure. The substrate can also be directly etched after the first electroplating to remove the parts other than the first circuit pattern, and the etched substrate is solder-resisted and then covered with the second dry film to prepare a metal support structure.

[0064] Step S105: performing a second electroplating on the substrate covered with the second dry film to obtain a substrate with a prepared metal support structure.

[0065] A copper layer is deposited on the exposed first circuit pattern portion of the copper-clad substrate covered with the second dry film by electrochemical reaction to form a metal support structure. The height of the metal support structure can be set according to actual application conditions. The height of the metal support structure can be controlled by controlling electroplating.

[0066] It is understandable that this embodiment only illustrates that the metal support structure can be formed by electroplating the substrate twice, and the metal support structure can also be formed by electroplating three times, wherein the sizes of the second layer and the third layer can be the same or different. The present invention can form a metal support structure by electroplating more than once.

[0067] In this embodiment, a circuit pattern is first prepared on a substrate, and a metal support structure is prepared on the circuit pattern after the circuit pattern is prepared. The metal support structure can support the barrier film to prevent the barrier film from contacting the chip pins due to pressure, avoid contamination of the effective resonance area, and ensure the integrity of the cavity, thereby greatly improving the performance of the chip; the metal support structure can also raise the metal wires for vertical bonding, reduce the length of the metal wires, and avoid deformation of the metal wires during resin pressing, thereby greatly improving the yield of the chip packaging structure; the metal support structure can also serve as the pins of the chip packaging structure, and the diameter and spacing of the pins do not have to be affected by the process capability and diameter of the BGA balls, thereby meeting the requirements of high-density double-sided packaging of the chip, and can replace the process of burying the chip in the substrate, thereby improving the chip yield and greatly promoting the development of the chip packaging structure.

[0068] In one embodiment, if Figure 2 As shown, a schematic flow chart of a method for processing a substrate having a metal support structure is provided. Figure 1 Based on the embodiment shown, after step S105, the processing method further includes:

[0069] Step S201: etching the substrate with the prepared metal support structure to obtain an etched substrate.

[0070] In this embodiment, the second dry film is directly covered on the substrate after the first electroplating. After the substrate covered with the second dry film is electroplated for the second time, the substrate is etched again. The etching time can be set according to the thickness of the copper clad substrate, and the parts of the substrate that are not the first circuit pattern and the second circuit pattern are removed to form the first circuit and the metal support structure on the substrate.

[0071] Step S202: preparing a solder resist layer on the etched substrate to obtain a substrate with the solder resist layer prepared thereon.

[0072] The solder resist ink is printed on the etched substrate, and then exposed and developed to form a solder resist layer.

[0073] In this embodiment, after the copper-clad substrate covered with the first dry film is electroplated, it is directly covered with a second dry film and electroplated for a second time to form a metal support structure. After the second electroplating, the substrate is etched and solder-resist treated. This is suitable for the case where the metal support structure does not affect the preparation of the solder resist layer, that is, the sum of the height of the metal support structure and the height of the first circuit is less than the height of the solder resist layer, or is equal to the height of the solder resist layer, or is slightly greater than the height of the solder resist layer. In this embodiment, etching is performed after the metal support structure is formed to avoid the first circuit under the metal support structure being an independent network design, which cannot be electrically conductive with other parts of the first circuit after etching, affecting the second electroplating, and further affecting the preparation of the metal support structure, thereby improving the reliability of the substrate with the metal support structure.

[0074] In one embodiment, if Figure 3 As shown, a schematic flow chart of a method for processing a substrate having a metal support structure is provided. Figure 1 On the basis of the embodiment shown, after step S103 and before step S104, the processing method further includes:

[0075] Step S301: etching the substrate after the first electroplating to obtain a substrate with a first circuit pattern prepared thereon.

[0076] The etching time can be set according to the thickness of the copper clad substrate, and the portion other than the first circuit pattern on the substrate can be removed to form a first circuit on the substrate.

[0077] Step S302: preparing a solder resist layer on the substrate on which the first circuit pattern is prepared, to obtain a substrate on which the solder resist layer is prepared.

[0078] The solder resist ink is printed on the etched substrate, and then exposed and developed to form a solder resist layer.

[0079] In this embodiment, the substrate is directly etched after the first electroplating to remove the portion other than the first circuit pattern, and the etched substrate is solder-resisted and then covered with a second dry film to prepare a metal support structure. The metal support structure is not affected by the solder resist layer, and a metal support structure with a higher height can be set so that the substrate can meet more application scenarios.

[0080] In one embodiment, if Figure 4 As shown, a schematic flow chart of a method for processing a substrate having a metal support structure is provided. Figure 3 Based on the embodiment shown, after step S302 and before step S104, the processing method further includes:

[0081] Step S401: preparing a seed layer on the substrate on which the solder resist layer is prepared, to obtain a substrate on which the seed layer is prepared.

[0082] The seed layer is a metal conductive layer, and any process can be used to prepare the metal conductive layer. Preferably, the seed layer is prepared on a substrate prepared with a solder resist layer by metal sputtering, and the seed layer is used to electrically connect the first circuit of the independent network design under the metal support structure with other parts of the first circuit.

[0083] After step S105, the processing method further includes:

[0084] Step S402: removing the seed layer on the substrate to obtain a substrate with the seed layer removed.

[0085] The seed layer may be substantially removed by etching.

[0086] In the present embodiment, before covering the second dry film on the substrate provided with the solder resist layer, a seed layer is first provided on the substrate provided with the solder resist layer, and the seed layer is utilized to electrically conduct the first circuit of the independent network design under the metal support structure with other parts of the first circuit, thereby preventing the first circuit of the independent network design under the metal support structure from being unable to undergo a second electroplating, thereby affecting the preparation of the metal support structure, and improving the reliability of the substrate.

[0087] In one embodiment, if Figure 5 As shown, a schematic flow chart of a method for processing a substrate having a metal support structure is provided. Figure 1-Figure 4 Based on any of the embodiments shown, the processing method further includes:

[0088] Step S501: performing surface treatment on the substrate to obtain a surface-treated substrate.

[0089] It is understandable that the surface treatment of the substrate in this embodiment should be performed after the solder mask layer is prepared and the metal support structure of the substrate is prepared. The surface treatment can be used to clean the substrate and remove impurities. The surface treatment can also be a mechanical treatment of the substrate or a chemical treatment of the substrate.

[0090] Step S502: performing shape detection processing on the substrate after the surface treatment to obtain a substrate after the shape detection processing.

[0091] The appearance inspection process can be surface defect inspection, color and gloss inspection, texture and roughness inspection, or size and tolerance inspection.

[0092] Step S503: testing the substrate after the shape detection process to obtain a tested substrate.

[0093] The test can be a functional test, a performance test, or a mechanical strength test.

[0094] Step S504: inspecting the tested substrate to obtain an inspected substrate.

[0095] Perform finished product inspection on the substrate so that it can be packaged and shipped.

[0096] In this embodiment, after the solder mask layer is prepared and the metal support structure of the substrate is prepared, the substrate is subjected to surface treatment, appearance inspection, testing and inspection to fully verify the comprehensive quality of the substrate and ensure the quality and reliability of the substrate.

[0097] like Figure 6 As shown, a schematic diagram of a cross-sectional structure of a chip packaging structure is provided, such as Figure 7 As shown, a schematic diagram of a top view structure of a substrate is provided.

[0098] In one embodiment, if Figure 6 and Figure 7 As shown, the chip packaging structure includes a first chip 1, a barrier film 2, a plastic sealing layer 3, and a substrate 4 with a metal support structure 5 obtained by the processing method mentioned in any of the above embodiments, the conductive pins of the first chip 1 are electrically interconnected with the chip side of the substrate 4, the barrier film 2 is arranged on the substrate 4, the barrier film 2 and the substrate 4 form a resonant cavity, the plastic sealing layer 3 is formed on the substrate 4 and the barrier film 2, the chip and the metal support structure 5 are arranged in the resonant cavity, and the metal support structure 5 is used to support the barrier film 2 when the plastic sealing layer 3 is pressed.

[0099] The metal support structure 5 can be directly set on the substrate 4 in the resonant cavity, and the metal support structure 5 can also be set on the first line of the resonant cavity. Preferably, the metal support structure 5 is set on the first line of the resonant cavity, and the height that the metal support structure 5 can support is the sum of the height of the first line below the metal support structure 5 and the height of the metal support structure 5. The height of the metal support structure 5 is set according to actual application conditions. Preferably, the sum of the height of the metal support structure 5 and the height of the first line below it is not greater than the height of the first chip 1 on the substrate 4, and the sum of the height of the metal support structure 5 and the height of the first line below it is greater than the height of the pins of the first chip 1 on the substrate 4.

[0100] It is understandable that the pin side of the substrate 4 should be provided with pins 6 of the chip packaging structure for connecting the chip packaging structure with the outside.

[0101] The barrier film 2 can be adhesively connected to the substrate 4, and the position of the metal support structure 5 can be set as needed. The metal support structure 5 can be set only on one side of the chip, or on the left and right sides of the chip, or on the front and back sides of the chip, or on the front, back, left and right sides of the chip. The metal support structures 5 can be connected together, or can be set independently.

[0102] The chip packaging structure of this embodiment sets the metal support structure 5 in the resonant cavity, and uses the metal support structure 5 to support the barrier film 2, so as to prevent the barrier film 2 from contacting the chip pins due to pressure, avoid contamination of the effective resonant area, and ensure the integrity of the cavity, thereby greatly improving the performance of the chip.

[0103] In one embodiment, if Figure 6 and Figure 7 As shown, based on the above embodiment, the metal support structure 5 is arranged on the circuit on the chip side of the substrate 4 and\or on the pad on the chip side of the substrate 4, and the metal support structure 5 is respectively arranged on the front side, back side, left side and right side of the first chip 1.

[0104] The metal support structure 5 is arranged on the line or pad of the first line. The height that the metal support structure 5 can support is the sum of the height of the first line below the metal support structure 5 and the height of the metal support structure 5. The width of the metal support structure 5 can be set according to the actual application situation. The width of the metal support structure 5 can be greater than the width of the first line below it, the width of the metal support structure 5 can also be the same as the width of the first line below it, or the width of the metal support structure 5 can also be less than the width of the first line below it.

[0105] The cross-sectional shape of the metal support structure 5 can be set according to the actual application. The upper bottom surface of the metal support structure 5 can be rectangular, circular, or elliptical. The bottom surface of the metal support structure 5 can be any shape.

[0106] The chip packaging structure of the present embodiment sets the metal support structure 5 on the first circuit, which can reduce the height of the metal support structure 5, making the metal support structure 5 easier to prepare, and can also increase the height that the metal support structure 5 can support. In addition, the chip packaging structure of the present embodiment sets a separate metal support structure 5 on each side of the first chip 1, which can reduce the stress of the laminated plastic sealing layer 3 and avoid damage to the connected metal support structures 5 due to stress during lamination, thereby affecting the support of the metal support structure 5 for the barrier film 2.

[0107] In one embodiment, if Figure 6As shown, based on the above embodiment, the width of the metal support structure 5 on the line is smaller than the width of the line, and the width of the metal support structure 5 on the pad is smaller than the width of the pad.

[0108] In the chip packaging structure of this embodiment, the width of the metal support structure 5 is smaller than the width of the first circuit thereunder, and the width of the metal support structure 5 is smaller than the width of the pad, so that the metal support structure 5 can be more stable, further ensuring the stability of the chip packaging structure.

[0109] In one embodiment, if Figure 8 As shown, a schematic diagram of the cross-sectional structure of a chip packaging structure is provided, the chip packaging structure includes a first chip 1, a metal layer 7, a plastic sealing layer 3, N metal wires 8 and a substrate 4 with a metal support structure 5 obtained by the processing method mentioned in any of the above embodiments, N is a natural number, the conductive pins of the first chip 1 are electrically interconnected with the chip side of the substrate 4, the metal support structure 5 is arranged on the front side, the back side, the left side and the right side of the first chip 1, the plastic sealing layer 3 is formed on the substrate 4 and the first chip 1, the metal layer 7 is arranged on the plastic sealing layer 3, each of the metal support structures 5 is connected to the metal wire 8, the other end of each of the metal wires 8 is connected to the metal layer 7, and each of the metal support structures 5 is used to raise each of the metal wires 8 to reduce the height of each of the metal wires 8.

[0110] The metal wire 8 of the chip packaging structure is prepared by a vertical wire bonding process, such as Fig. 9 As shown, on one side or multiple sides of the chip, one end of the metal wire is fixed on the metal support structure 5 by using a wire bonding machine, and the other end of the metal wire is fixed on the metal support structure 5 after being bent. After the plastic sealing layer 3 is pressed, the surface of the plastic sealing layer 3 is polished until the bending part of the metal wire is broken to form two metal wires 8. A metal layer 7 is prepared on the surface of the plastic sealing layer 3. The metal layer 7 can be prepared in any way. Preferably, the metal layer 7 is prepared by a metal sputtering process. The metal layer 7 is connected to the metal wires 8 on each side of the chip, so that electromagnetic shielding can be performed between multiple chips in the chip packaging structure.

[0111] In the chip packaging structure of this embodiment, a metal support structure 5 is arranged under the vertically bonded metal wire 8. The metal support structure 5 can prevent the metal wire 8 from deforming during the resin pressing process, thereby greatly improving the yield rate of the chip packaging structure.

[0112] In one embodiment, if Fig. 9As shown, a schematic diagram of the cross-sectional structure of a chip packaging structure is provided, the chip packaging structure includes a first chip 1, a second chip 9, a plastic sealing layer 3, and a substrate 4 with a metal support structure 5 obtained by the processing method mentioned in any of the above embodiments, the conductive pins of the first chip 1 are electrically interconnected with the chip side of the substrate 4, the conductive pins of the second chip 9 are electrically interconnected with the pin side of the substrate 4, the plastic sealing layer 3 is formed on the first chip 1, the substrate 4 and the second chip 9, the metal support structure 5 is arranged on the pin side of the substrate 4, the height of the metal support structure 5 is higher than the plastic sealing layer 3 on the pin side of the substrate 4, the metal support structure 5 is the pin 6 of the chip packaging structure, and is used for the chip packaging structure to be electrically interconnected with the outside.

[0113] The metal support structure 5 can be directly set on the substrate 4, the metal support structure 5 can be set on the implant ball on the pin side of the substrate 4, the position of the metal support structure 5 and the size of the metal support structure 5 can be set according to the actual application situation, preferably, the metal support structure 5 is set on both sides of the first chip 1 of the substrate 4, the height of the metal support structure 5 can be set according to the actual application strength, preferably, the height of the metal support structure 5 should be greater than the height of the second chip 9 on the substrate 4, so that the second chip 9 can be set on the pin side of the substrate 4.

[0114] The chip packaging structure of this embodiment uses a metal support structure 5 as the pin 6 of the chip packaging structure. The height and spacing of the pins do not need to be affected by the process capability and diameter of the BGA ball, which meets the requirements of double-sided chip packaging and can replace the process of burying the chip in the substrate 4. While improving the chip yield, it greatly promotes the development of the chip packaging structure.

[0115] The embodiments described above are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included in the protection scope of the present invention.

Claims

1. A method for processing a substrate having a metal support structure, characterized in that: The processing method comprises: Providing a copper-clad substrate; Covering the copper-clad substrate with the first dry film having the first circuit pattern set thereon to obtain the copper-clad substrate covered with the first dry film; Performing a first electroplating on the copper-clad substrate covered with the first dry film to obtain a substrate after the first electroplating; Covering the substrate with a second dry film having a second circuit pattern, wherein the second circuit pattern includes a pattern of the metal support structure, to obtain a substrate covered with the second dry film; The substrate covered with the second dry film is subjected to a second electroplating to obtain a substrate with a prepared metal support structure.

2. The method for processing a substrate having a metal support structure according to claim 1, wherein: After obtaining the substrate with the prepared metal support structure, the processing method further comprises: Etching the substrate on which the metal support structure is prepared to obtain an etched substrate; A solder resist layer is prepared on the etched substrate to obtain a substrate with a prepared solder resist layer.

3. The method for processing a substrate having a metal support structure according to claim 1, wherein: After obtaining the substrate after the first electroplating, before covering the substrate with the second dry film having the second circuit pattern, the processing method further includes: Etching the substrate after the first electroplating to obtain a substrate with a first circuit pattern prepared thereon; A solder resist layer is prepared on the substrate on which the first circuit pattern is prepared, so as to obtain a substrate on which the solder resist layer is prepared.

4. The method for processing a substrate having a metal support structure according to claim 3, wherein: After obtaining the substrate on which the solder resist layer is prepared, before covering the substrate with the second dry film on which the second circuit pattern is set, the processing method further comprises: Preparing a seed layer on the substrate on which the solder resist layer is prepared, to obtain a substrate on which the seed layer is prepared; After the substrate covered with the second dry film is electroplated for the second time, the processing method further comprises: The seed layer on the substrate is removed to obtain a substrate with the seed layer removed.

5. The method for processing a substrate having a metal support structure according to any one of claims 1 to 4, characterized in that: The processing method also includes: Performing surface treatment on the substrate to obtain a surface-treated substrate; Performing an appearance detection process on the substrate after the surface treatment to obtain a substrate after the appearance detection process; Testing the substrate after the shape detection process to obtain a tested substrate; The tested substrate is inspected to obtain an inspected substrate.

6. A chip packaging structure, characterized in that: The chip packaging structure includes a first chip, a barrier film, a plastic sealing layer, and a substrate with a metal support structure obtained by any processing method of claims 1-5, wherein the conductive pins of the first chip are electrically interconnected with the chip side of the substrate, the barrier film is arranged on the substrate, the barrier film and the substrate form a resonant cavity, the plastic sealing layer is formed on the substrate and the barrier film, the chip and the metal support structure are arranged in the resonant cavity, and the metal support structure is used to support the barrier film when the plastic sealing layer is pressed.

7. The chip packaging structure according to claim 6, characterized in that: The metal support structure is arranged on the circuit on the chip side of the substrate and / or on the pad on the chip side of the substrate, and the metal support structure is respectively arranged on the front side, the back side, the left side and the right side of the first chip.

8. The chip packaging structure according to claim 7, characterized in that: The width of the metal support structure on the circuit is smaller than the width of the circuit, and the width of the metal support structure on the pad is smaller than the width of the pad.

9. A chip packaging structure, characterized in that: The chip packaging structure includes a first chip, a metal layer, a plastic sealing layer, N metal wires and a substrate with a metal support structure obtained by any processing method of claims 1-5, N is a natural number, the conductive pins of the first chip are electrically interconnected with the chip side of the substrate, the metal support structure is arranged on the front side, the back side, the left side and the right side of the first chip, the plastic sealing layer is formed on the substrate and the first chip, the metal layer is arranged on the plastic sealing layer, each of the metal support structures is connected to the metal wire, the other end of each of the metal wires is connected to the metal layer, and each of the metal support structures is used to raise each of the metal wires to reduce the height of each of the metal wires.

10. A chip packaging structure, characterized in that: The chip packaging structure includes a first chip, a second chip, a plastic packaging layer, and a substrate with a metal support structure obtained by any processing method of claims 1-5, the conductive pins of the first chip are electrically interconnected with the chip side of the substrate, the conductive pins of the second chip are electrically interconnected with the pin side of the substrate, a plastic packaging layer is formed on the first chip, the substrate and the second chip, the metal support structure is arranged on the pin side of the substrate, the height of the metal support structure is higher than the plastic packaging layer on the pin side of the substrate, the metal support structure is the pin of the chip packaging structure, and is used for the chip packaging structure to be electrically interconnected with the outside.

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