Correction method for improving packaging yield of chipset

Abstract

The invention relates to the technical field of chip packaging, in particular to a correction method for improving the packaging yield of a chipset, and the method comprises the steps: fixing the chipset to a controllable bearing platform, or fixing a plurality of chips to the controllable bearing platform, and forming the chipset; carrying out relative position detection on the chips in the same group of chip groups, and determining target chips of which the position offset exceeds a position precision threshold in the chip groups; and correcting the position of the target chip, so that the relative position between the chips in the chip set meets the position precision threshold. Based on the above scheme, the yield of chip group packaging can be improved.

Description

Technical Field

[0001] The present application relates to the field of chip packaging technology, and in particular to a correction method for improving the chip set packaging yield. Background Art

[0002] In the field of advanced chip packaging, it may be necessary to combine and package multiple chips into a chipset to achieve higher functional requirements, or it may be necessary to temporarily package multiple chips into a chipset to achieve high-precision control requirements during processing. This requires that the relative positions of each chip in the chipset need to be maintained within a certain accuracy range, and the relative positions of each chip cannot be offset too much, otherwise it will cause the overall failure of the chipset and affect the yield of the chipset packaging. However, in the current solution, after the chips are packaged into the target carrier to form a chipset, the chips in the chipset can no longer be removed and moved, so at least some of the chips in the chipset will be scrapped. Summary of the invention

[0003] In order to solve the above technical problem or at least partially solve the above technical problem, the present application provides a correction method for improving the chipset packaging yield.

[0004] The present application provides a correction method for improving the chip set packaging yield, comprising:

[0005] Fixing a chipset to a controllable carrying platform, or fixing a plurality of chips to the controllable carrying platform, to form the chipset;

[0006] Performing relative position detection on the chips in the same chipset group to determine a target chip in the chipset whose position offset exceeds a position accuracy threshold;

[0007] The position of the target chip is corrected so that the relative positions between the chips in the chipset meet the position accuracy threshold.

[0008] Optionally, the controllable carrying platform includes a plurality of installation areas and vacuum chambers corresponding to the installation areas one by one; the installation areas and the vacuum chambers are connected via through holes;

[0009] The step of fixing the chipset to the controllable carrying platform comprises:

[0010] Placing the chipset in the installation area on the controllable carrying platform, and controlling the vacuum chamber corresponding to the installation area where the chipset is located to form a vacuum, so as to fix the chipset;

[0011] or,

[0012] The step of fixing the plurality of chips to the controllable carrying platform comprises:

[0013] The plurality of chips are placed in the installation area on the controllable carrying platform, and the vacuum chamber corresponding to the installation area where the chips are located is controlled to form a vacuum so as to fix the chips.

[0014] Optionally, identification points are set on the surfaces of all the chips;

[0015] The performing relative position detection on the chips in the same chipset group to determine the target chip in the chipset whose position offset exceeds the position accuracy threshold comprises:

[0016] Acquiring image information of the chipset;

[0017] Determine the relative positions of the identification points corresponding to all the chips in the same chip group based on the image information;

[0018] Based on the relative positions of all the identification points, the target chip is determined.

[0019] Optionally, the correcting the position of the target chip includes:

[0020] removing the target chip from the controllable carrying platform;

[0021] Determine the position information of the target chip, and determine the position information of at least one reference chip; wherein the reference chip is the chip in the same group of the chipset whose position offset does not exceed the position accuracy threshold;

[0022] Determining a target position of the target chip on the controllable carrying platform based on the position information of the target chip and the position information of the reference chip;

[0023] The target chip is fixed to the target position.

[0024] Optionally,

[0025] The step of removing the target chip from the controllable carrying platform comprises:

[0026] Controlling the manipulator to fix the target chip;

[0027] releasing the vacuum chamber corresponding to the target chip so that the target chip is separated from the mounting area;

[0028] Move from the target chip to directly above the controllable carrying platform in the vertical direction;

[0029] The step of fixing the target chip to the target position comprises:

[0030] Determining a displacement amount corresponding to moving the target chip to the target position on a plane parallel to the controllable carrying platform;

[0031] Controlling the manipulator to move the target chip based on the displacement;

[0032] Controlling the manipulator to move the target chip in a direction perpendicular to the plane where the controllable carrying platform is located, until the target chip is moved to an installation area corresponding to the target position;

[0033] The vacuum chamber corresponding to the mounting area corresponding to the target position is controlled to form a vacuum so as to fix the target chip.

[0034] Optionally, the controllable bearing platform comprises a plurality of independent installation areas, and the plurality of independent installation areas are moved in any direction parallel to the plane where the installation areas are located through the action of the fine-tuning component;

[0035] The correcting the position of the target chip comprises:

[0036] Determine the position information of the target chip, and determine the position information of at least one reference chip; wherein the reference chip is the chip in the same group of the chipset whose position offset does not exceed the position accuracy threshold;

[0037] Based on the position information of the target chip and the position information of the reference chip, the installation area corresponding to the target chip is controlled to move.

[0038] Optionally, controlling the movement of the installation area corresponding to the target chip based on the position information of the target chip and the position information of the reference chip includes:

[0039] Determining a target position of the target chip based on the position information of the target chip and the position information of the reference chip;

[0040] Determining a position compensation amount of the installation area corresponding to the target chip based on the target position;

[0041] The mounting area corresponding to the target chip is controlled to move based on the position compensation amount.

[0042] Optionally, the controllable carrying platform is provided with the identification point; before fixing the chipset to the controllable carrying platform, or fixing a plurality of chips to the controllable carrying platform, the method further includes:

[0043] Determine the position information of all the chips based on the identification points on the chip surface, and determine the position information of the installation area on the controllable carrying platform based on the identification points on the controllable carrying platform;

[0044] The chip is fixed to the mounting area based on the position information of the chip and the position information of the mounting area.

[0045] Optionally, after correcting the position of the target chip, the method further includes:

[0046] Returning to the step of detecting the chipset fixed on the controllable carrying platform;

[0047] The method further comprises:

[0048] It is determined that the number of corrections reaches the number threshold and an alarm message is generated.

[0049] Optionally, after correcting the position of the target chip, the method further includes:

[0050] Transferring the chipset from the controllable carrier platform to a target carrier, and keeping the relative positions of all the chips in the chipset unchanged;

[0051] Wherein, the target carrier is used to encapsulate the chipset.

[0052] The correction method for improving the chipset packaging yield provided by the present application can fix the chips on a controllable carrier platform to form a chipset before packaging the chipset, or fix the chipset to the controllable carrier platform, detect the relative positions of all chips in the chipset, and correct the position of the target chip after determining the offset target chip. The controllable carrier platform is different from the carrier used to package the chipset, and the position of any chip can still be adjusted after the chipset is fixed, so the purpose of correcting the target chip can be achieved. Since the chips can be packaged after the chipset is corrected, the present application is conducive to improving the chipset packaging yield. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] Figure 1 A schematic flow chart of a correction method for improving chipset packaging yield provided in an embodiment of the present application;

[0054] Figure 2 A schematic diagram of a chipset structure provided in an embodiment of the present application;

[0055] Figure 3 A schematic diagram of a controllable carrier platform and chipset structure provided in an embodiment of the present application;

[0056] Figure 4 A schematic diagram of a vacuum chamber structure provided in an embodiment of the present application;

[0057] Figure 5A schematic diagram of another chipset structure provided in an embodiment of the present application;

[0058] Figure 6 A schematic diagram of another controllable carrier platform and chipset structure provided in an embodiment of the present application. DETAILED DESCRIPTION

[0059] In order to more clearly understand the above-mentioned purposes, features and advantages of the present application, the scheme of the present application will be further described below. It should be noted that the embodiments of the present application and the features in the embodiments can be combined with each other without conflict.

[0060] In the following description, many specific details are set forth to facilitate a full understanding of the present application, but the present application may also be implemented in other ways different from those described herein; obviously, the embodiments in the specification are only part of the embodiments of the present application, rather than all of the embodiments.

[0061] A correction method for improving the chipset packaging yield provided by an embodiment of the present application is exemplarily described below in conjunction with the accompanying drawings. Figure 1 A schematic flow chart of a correction method for improving chipset packaging yield provided in an embodiment of the present application includes:

[0062] S101, fixing a chipset to a controllable carrying platform, or fixing multiple chips to a controllable carrying platform to form a chipset.

[0063] S102: Perform relative position detection on chips in the same chipset group to determine a target chip in the chipset whose position offset exceeds a position accuracy threshold.

[0064] S103: Correct the position of the target chip so that the relative positions between the chips in the chipset meet the position accuracy threshold.

[0065] The controllable carrying platform in the embodiment of the present application refers to a carrying platform that can fix the chipset and from which the chipset can be removed again.

[0066] The chipset is composed of multiple identical or different chips. In the application scenarios corresponding to the embodiments of the present application, the chips in the chipset need to maintain a specific relative position relationship. Figure 2 A schematic diagram of a chipset structure provided in an embodiment of the present application. Figure 2 As shown, the figure is a top view of a chipset, which is composed of multiple identical or different chips. Figure 2 They are indicated as A, B, C, D, and E respectively. Figure 2A, B, C, D, and E in the figure represent different chips, but there is no restriction on whether they are the same chip. The relative positions of A, B, C, D, and E need to maintain a specific distance. For example, with A as the reference, the distance between B and A needs to be a, and the side B1 of B and the side A1 of A need to be on the same straight line ( Figure 2 In the figure, L0 is indicated, LO is based on the side A1 of A, L0 is the distance between A1 and B1, if the sides of A and B are aligned, L0 = 0). Due to the limitation of accuracy, the distance between A and B is generally not guaranteed to be a in an absolute sense, and the sides of A and B are not on the same straight line in an absolute sense, so they are generally kept within a certain range of accuracy. For example, the distance between A and B is between a-b1 and a+b1 (b1>0), and the distance L0 between the side B1 of B and the side A1 of A is kept between -b2 and +b2 (b2>0), which is the accuracy threshold. Although the target spacing between A and B is a, as long as the spacing between A and B is between a-b1 and a+b1 and the spacing L0 between the side B1 of B and the side A1 of A is between -b2 and +b2, it is considered that the position accuracy threshold is not exceeded. On the contrary, if the distance between A and B is not between a-b1 and a+b1 or L0 is not between -b2 and +b2, it is considered that the position accuracy threshold is exceeded.

[0067] Specifically, the embodiment of the present application can fix the chip to the carrier platform by means of a structure capable of fixing the chip, such as a robot, to form a chipset. Figure 3 A schematic diagram of a controllable carrier platform and chipset structure provided in an embodiment of the present application. Figure 3 As shown in FIG. 3 , which is a top view, after the chips are fixed to the controllable carrier platform 300 to form a chipset, the position of chip E deviates, and the distance between chip E and chip A is c, and c>a+b1, so chip E is the target chip. It should be noted here that since the chipset in the embodiment of the present application only needs to maintain a relative position to meet the position accuracy threshold, Figure 3For the scenario in, chips A, B, C, and D can also be defined as target chips, but this obviously requires the simultaneous correction of four chips A, B, C, and D, and if chip E is determined as the target chip, only one chip needs to be corrected. That is, the target chip defined in the embodiment of the present application is actually determined by the core criterion that the number of chips that need to be corrected is a minority. In some scenarios, if the positions of all chips do not meet the position accuracy threshold, any chip can be selected as the reference chip, and all the remaining chips are determined as target chips. Alternatively, the target chip can be determined with reference to the controllable carrier platform, and its principle can be simply explained as follows: when the positions of all chips in the chipset do not meet the accuracy threshold, a reference chip needs to be selected so that all chips will not deviate too much from the controllable carrier platform after correction. This is because the area of ​​the controllable carrier platform is limited. If the chip deviates too much from the controllable carrier platform, it may cause the chip to be unable to be fixed to the corresponding installation area, affecting the correction of the chip. In the embodiment of the present application, in order to simplify the description, only the situation of the position offset of a single chip is explained.

[0068] After determining that chip E is the target chip, the target chip can be removed from the controllable carrier platform by a manipulator or other device, and the position where the target chip should be located can be determined and fixed again. The background faced here is that in the process of the manipulator fixing the chip to the controllable carrier platform, since the installation accuracy of the manipulator itself is relatively high, after the chip is fixed to the controllable carrier platform, the probability of meeting the position accuracy threshold is relatively high, and not meeting the position accuracy threshold is a low probability event. Therefore, as long as the target chip can be corrected by re-fixing, the purpose of making the relative position between the chips in the chipset meet the position accuracy threshold can be achieved.

[0069] In summary, the present application can improve the yield rate of chipset packaging.

[0070] In some embodiments, after the position of the target chip is corrected, the method further includes:

[0071] Return to test the chipset fixed on the controllable carrier platform.

[0072] Specifically, in the above embodiment, it is mentioned that after the chip is fixed to the controllable carrier platform, the probability of it meeting the position accuracy threshold is relatively high. However, there are still some scenarios where, even with a high probability, the relative positions of the chips in the chipset still do not meet the position accuracy threshold after one correction. Therefore, after the target chip is corrected, the embodiment of the present application can also re-detect the chipset, and if it still does not meet the position accuracy threshold, it is corrected again.

[0073] This method only requires calibration of the target chip without improving the accuracy of the existing packaged chipset equipment. Compared with improving accuracy, the cost of this solution is lower.

[0074] In some embodiments, the method further comprises:

[0075] It is determined that the number of corrections reaches the number threshold and an alarm message is generated.

[0076] Specifically, the chip installation accuracy in the embodiment of the present application presents a normal distribution as a whole, that is, after the chip is fixed, the chip has a greater probability of meeting the position accuracy threshold, and only a small probability of not meeting the position accuracy threshold. Therefore, under normal circumstances, after multiple corrections, the chip can meet the position accuracy threshold. On the contrary, if the position accuracy threshold cannot be met after the number of corrections reaches the threshold, it may represent a failure of the controllable carrier platform or the device used to fix the chip (such as a manipulator). In this case, an alarm message can be generated to prompt personnel to handle it.

[0077] In some embodiments, the controllable carrying platform includes a plurality of installation areas and vacuum chambers corresponding to the installation areas one by one. The installation areas and the vacuum chambers are connected via through holes.

[0078] Fix the chipset to a controllable carrier platform, including:

[0079] The chipset is placed in the installation area on the controllable carrying platform, and the vacuum chamber corresponding to the installation area where the chipset is located is controlled to form a vacuum to fix the chipset.

[0080] or,

[0081] Fix multiple chips to a controllable carrier platform, including:

[0082] Multiple chips are placed in the mounting area on the controllable carrying platform, and the vacuum chamber corresponding to the mounting area where the chips are located is controlled to form a vacuum to fix the chips.

[0083] Specifically, a chipset is formed by fixing multiple chips to a controllable carrier platform as an example. Multiple mounting areas on the controllable carrier platform are used to carry and fix chips. The carrier platform is approximately composed of two parts, namely, a vacuum chamber and a mounting area that are interconnected through through holes. After the chip is placed in the mounting area, a vacuum is formed in the vacuum chamber, and each chip is fixed to a specific position based on the effect of air pressure. After that, the relative position of each chip has been preliminarily determined, that is, a chipset has been formed. Continuing to refer to the above embodiment, in the application scenario corresponding to the embodiment of the present application, based on the influence of the accuracy of the device (such as a manipulator) for fixing the chip, the relative position of each chip in the chipset is likely to meet the position accuracy threshold, but there is still the possibility that the position of an individual chip does not meet the requirements of the position accuracy threshold.

[0084] This step actually replaces the step of packaging the chip into the target carrier, and the formed chipset can detect the relative position and remove the target chip that does not meet the position accuracy threshold requirement. If the target chip needs to be removed, it is only necessary to release the vacuum chamber at the corresponding position of the target chip.

[0085] In order to fix different types of chips, there can be multiple vacuum chambers, and each chip is fixed by multiple vacuum chambers. Figure 4 A schematic diagram of a vacuum chamber structure provided in an embodiment of the present application. Figure 4 As shown, the schematic diagram is a side view of the carrier platform, and chips 401 of different types (shapes) are covered with multiple vacuum chambers 402, and the multiple vacuum chambers 402 form a vacuum together to achieve the purpose of fixing the chip 401, and Figure 4 In the figure, the size of the vacuum chamber 402 is shown to be the same as the size of the through hole, so the through hole is not additionally shown. Figure 4 This is only one form of fixing the chip 401 in the vacuum chamber 402 . The embodiment of the present application can naturally make certain adjustments to the shape of the vacuum chamber 402 to fix the chip 401 in other vacuum ways, which are not listed here one by one.

[0086] In some embodiments, identification points are set on the surfaces of all chips.

[0087] Perform relative position detection on chips in the same chipset to determine the target chip in the chipset whose position offset exceeds the position accuracy threshold, including:

[0088] Get the chipset image information.

[0089] The relative positions of the identification points corresponding to all chips in the same chipset are determined based on the image information.

[0090] Based on the relative positions of all the identification points, the target chip is determined.

[0091] Figure 5 A schematic diagram of another chipset structure provided in an embodiment of the present application. Figure 5 As shown, the surface of the chip in the chipset is provided with easily identifiable identification points 500. In the embodiment of the present application, an image sensor can be provided on the manipulator structure for grabbing the chip to obtain an image of the chipset, and then the position information of each identification point 500 is determined based on the acquired image information, and then the relative position of each identification point 500 is determined. For example, a temporary coordinate system is established based on the acquired image, and then the coordinates of each identification point 500 are determined, and the relative position of each identification point 500 is determined based on the coordinates, and the relative position of the identification point 500 is actually the relative position of each chip. After the relative position of each chip is determined, it can be determined whether the position accuracy threshold is met based on the relative position information of each chip in the expected chipset.

[0092] Continue reading Figure 5 In the embodiment of the present application, at least one identification point 500 may be set on the surface of each chip in the chipset. Figure 5 Two identification points 500 are selectively set in the chip. Based on the setting of the two identification points 500, the exact position of the chip can be determined through the position information of the two identification points 500. Compared with one identification point 500, it can avoid the chip shifting due to the rotation of the chip along the direction perpendicular to the plane where the chipset is located. In some scenarios, the position information of the chip can also be determined by an identification point 500 with a specific pattern. For this method, it is necessary to ensure that the chip will not shift due to rotation based on the pattern information of the identification point 500. In essence, it can still be considered that the position information of the chip is determined by at least two identification points 500.

[0093] In some embodiments, correcting the position of the target chip includes:

[0094] Remove the target chip from the controllable carrying platform.

[0095] The position information of the target chip is determined, and the position information of at least one reference chip is determined, wherein the reference chip is a chip in the same chip group whose position offset does not exceed the position accuracy threshold.

[0096] Based on the position information of the target chip and the position information of the reference chip, a target position of the target chip on the controllable carrying platform is determined.

[0097] Fix the target chip to the target position.

[0098] Specifically, the target chip can be removed after being determined. Since the embodiment of the present application needs to keep the positions of each chip in the same chipset to meet the position accuracy threshold requirement, the target chip can be calibrated based on the position information of at least one reference chip in the same chipset.

[0099] There is a specific relative position relationship between the target chip and the reference chip, such as borrowing Figure 3 , chip E is the target chip, and in this example, whether there is an offset in the direction perpendicular to the plane where the chipset is located is not considered. Therefore, to determine the target position, it is only necessary to use chips A and D as reference chips to determine the target position of chip E. For example, the distance between chip E and chip A is c, the distance between chip E and chip D is d, and the set distance between chip E and chip A is a, and the position accuracy threshold is a+b1, c>a+b1, the set distance between chip E and chip D is e, and the position accuracy threshold is e+b2, d>e+b2, so that the target position can be determined. Further, Figure 3 The XY plane rectangular coordinate axes are also shown in the figure. The target position in the embodiment of the present application can actually be considered as the plane rectangular coordinates on the plane where the chipset is located. For example, the target position is moved in the negative direction of the X axis by de and in the negative direction of the Y axis by ca. It should be noted that other coordinate systems can also determine the target position, such as polar coordinates, etc., which are not listed here one by one.

[0100] In some embodiments,

[0101] Remove the target chip from the controllable carrying platform, including:

[0102] Control the robot to fix the target chip.

[0103] The vacuum chamber corresponding to the target chip is released, so that the target chip is separated from the mounting area.

[0104] Move from the target chip to directly above the controllable carrying platform in the vertical direction.

[0105] Fix the target chip to the target location, including:

[0106] Determine the displacement amount corresponding to moving the target chip to the target position on the plane parallel to the controllable carrying platform.

[0107] The robot is controlled to move the target chip based on the displacement.

[0108] The manipulator is controlled to move the target chip in a direction perpendicular to the plane where the controllable carrying platform is located, until the target chip is moved to an installation area corresponding to the target position.

[0109] The vacuum cavity corresponding to the mounting area corresponding to the target position is controlled to form a vacuum to fix the target chip.

[0110] Specifically, the embodiment of the present application can grab (fix) the target chip by a structure such as a manipulator, and the relative position of the manipulator and the image sensor is fixed. After determining the target chip, the manipulator can adsorb (grab) the target chip, and then release the vacuum chamber corresponding to the target chip, and remove the target chip from the controllable carrying platform.

[0111] In the previous step, the target chip is determined through the image, that is, the relative position relationship between the target chip and other chips is actually determined. Therefore, after the target chip is moved to the top, the distance and direction that the target chip needs to be moved can be directly determined based on the position relationship between the target chip and other chips, which is simpler and faster.

[0112] After removing the target chip, continue to calculate the displacement, move the target chip according to the displacement, until it reaches the corresponding target position on a plane parallel to the plane where the chipset is located, then move the target chip toward the installation area, and finally fix the target chip to complete the calibration.

[0113] In some embodiments, the controllable carrying platform includes a plurality of independent installation areas, and the plurality of independent installation areas are moved in any direction parallel to the plane where the installation areas are located through the action of the fine-tuning component.

[0114] Correct the position of the target chip, including:

[0115] The position information of the target chip is determined, and the position information of at least one reference chip is determined, wherein the reference chip is a chip in the same chip group whose position offset does not exceed the position accuracy threshold.

[0116] Based on the position information of the target chip and the position information of the reference chip, the movement of the mounting area corresponding to the target chip is controlled.

[0117] In some embodiments, based on the position information of the target chip and the position information of the reference chip, controlling the installation area corresponding to the target chip to move includes:

[0118] The target position of the target chip is determined based on the position information of the target chip and the position information of the reference chip.

[0119] A position compensation amount of a mounting area corresponding to the target chip is determined based on the target position.

[0120] The movement of the mounting area corresponding to the target chip is controlled based on the position compensation amount.

[0121] Specifically, the controllable bearing platform in the embodiment of the present application may also be composed of multiple independent installation areas. Figure 6 A schematic diagram of another controllable carrier platform and chipset structure provided in the embodiment of the present application. Figure 6 As shown, the figure is a top view of the controllable carrying platform 300. Each chip in the chipset is fixed on a different installation area 601. After determining the target chip, the target position of the target chip is further determined, and then the position compensation amount can be directly determined. The position compensation amount is actually the offset between the position of the target chip and the target position, and then the installation area 601 corresponding to the target chip is directly moved to achieve the purpose of correcting the target chip. For this method, since the installation area can be directly moved, there is no need to remove the target chip, which reduces the steps of some process flows.

[0122] Continue reading Figure 6 , Figure 6 There are two figures, one before and one after calibration. Before calibration, the target chip is chip E, the set distance between chip E and chip A is a, and the set distance between chip E and chip D is e. In fact, the distance between chip E and chip A is c, and the distance between chip E and chip D is d. For this, it is only necessary to move the installation area 601 corresponding to chip E, and move the installation area 601 corresponding to chip E by ca along the negative direction of the X axis and by de along the negative direction of the Y axis, as shown in FIG. Figure 6 The following figure shows the chipset calibration.

[0123] In some embodiments, the controllable carrier platform is provided with an identification point. Before fixing the chipset to the controllable carrier platform, or fixing multiple chips to the controllable carrier platform, the method further includes:

[0124] The position information of all chips is determined based on the identification points on the chip surface, and the position information of the installation area on the controllable carrying platform is determined based on the identification points on the controllable carrying platform.

[0125] The chip is fixed to the mounting area based on the position information of the chip and the position information of the mounting area.

[0126] Specifically, before fixing the chip, the embodiment of the present application also needs to determine the location of the controllable carrier platform through the identification points on the controllable carrier platform, determine the position information of the installation area on the controllable carrier platform through the identification points on the controllable carrier platform, and determine the moving position of the chip based on the position information of the chip, that is, the chip is accurately fixed to the corresponding installation area through the above method.

[0127] In some embodiments, after the position of the target chip is corrected, the method further includes:

[0128] The chipset is transferred from the controllable carrier platform to the target carrier, and the relative positions of all chips in the chipset are kept unchanged.

[0129] The target carrier is used to package the chipset.

[0130] Specifically, after the chipset is corrected, the relative positions of all chips in the chipset are kept unchanged, and the chips on the controllable carrier platform are transferred as a whole to the target carrier to complete the chip packaging. Since the chipset has been corrected by the correction method for improving the chipset packaging yield before packaging, theoretically, the chipset transferred to the target carrier can achieve a 100% yield, which can achieve no defective products compared to the traditional solution, greatly improving the chip packaging yield.

[0131] After the chip is fixed to the target carrier, the side facing the target carrier can be called the front side, and the side facing away from the target carrier can be called the back side. In the embodiment of the present application, there is actually no limitation on the side facing the controllable carrier platform after being fixed to the controllable carrier platform, that is, it can actually be the front side of the chip or the back side of the chip. In all the above embodiments, there is no limitation on the setting position of the identification point, but with respect to the embodiment of the present application, if the side facing the controllable carrier platform is the front side of the chip, then the identification point can be set at least on the back side of the chip; conversely, if the side facing the controllable carrier platform is the back side of the chip, then the identification point can be set at least on the front side of the chip. In this way, after the chip is fixed to the controllable carrier platform, the image sensor can determine the position of the chip based on the identification points set on the chip.

[0132] In some embodiments, identification points can also be set on both the front and back sides of the chip. Obviously, the relative positions of the identification points set on the front and back sides of the chip are fixed, or the vertical projections of the identification points set on the front and back sides of the chip completely overlap. In this way, the embodiment of the present application can further collect the position of the identification points on the other side of the chip through another image sensor when the robot picks up the chip to determine the position of the chip, so as to avoid the chip offset problem caused by the robot picking up the chip. For example, if the robot picks up the target chip by sucking the back side of the target chip, the image sensor can collect the position of the marking points on the front side of the target chip, and then determine the position of the target chip. In this way, according to the position of the target chip in this case, and the target position of the target chip, the target chip can be fixed in the correct position more accurately, avoiding the influence of the offset caused by the robot picking up the chip.

[0133] It should be noted that, in this article, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the term "comprises" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0134] So far, the technical solutions of the present invention have been described in conjunction with the preferred embodiments shown in the accompanying drawings. However, it is easy for those skilled in the art to understand that the protection scope of the present invention is obviously not limited to these specific embodiments. Without departing from the principle of the present invention, those skilled in the art can make equivalent changes or substitutions to the relevant technical features, and the technical solutions after these changes or substitutions will fall within the protection scope of the present invention.

Claims

1. A correction method for improving the chip set packaging yield, characterized in that: include: Fixing a chipset to a controllable carrying platform, or fixing a plurality of chips to the controllable carrying platform, to form the chipset; Performing relative position detection on the chips in the same chipset group to determine a target chip in the chipset whose position offset exceeds a position accuracy threshold; The position of the target chip is corrected so that the relative positions between the chips in the chipset meet the position accuracy threshold.

2. The method according to claim 1, characterized in that The controllable carrying platform comprises a plurality of installation areas and vacuum chambers corresponding to the installation areas one by one; the installation areas and the vacuum chambers are connected via through holes; The step of fixing the chipset to the controllable carrying platform comprises: Placing the chipset in the installation area on the controllable carrying platform, and controlling the vacuum chamber corresponding to the installation area where the chipset is located to form a vacuum, so as to fix the chipset; or, The step of fixing the plurality of chips to the controllable carrying platform comprises: The plurality of chips are placed in the installation area on the controllable carrying platform, and the vacuum chamber corresponding to the installation area where the chips are located is controlled to form a vacuum so as to fix the chips.

3. The method according to claim 2, characterized in that All the surfaces of the chips are provided with identification points; The performing relative position detection on the chips in the same chipset group to determine the target chip in the chipset whose position offset exceeds the position accuracy threshold comprises: Acquiring image information of the chipset; Determine the relative positions of the identification points corresponding to all the chips in the same chip group based on the image information; Based on the relative positions of all the identification points, the target chip is determined.

4. The method according to claim 3, characterized in that: The correcting the position of the target chip comprises: removing the target chip from the controllable carrying platform; Determine the position information of the target chip, and determine the position information of at least one reference chip; wherein the reference chip is the chip in the same group of the chipset whose position offset does not exceed the position accuracy threshold; Determining a target position of the target chip on the controllable carrying platform based on the position information of the target chip and the position information of the reference chip; The target chip is fixed to the target position.

5. The method according to claim 4, characterized in that The step of removing the target chip from the controllable carrying platform comprises: Controlling the manipulator to fix the target chip; releasing the vacuum chamber corresponding to the target chip so that the target chip is separated from the mounting area; Move from the target chip to directly above the controllable carrying platform in the vertical direction; The step of fixing the target chip to the target position comprises: Determining a displacement amount corresponding to moving the target chip to the target position on a plane parallel to the controllable carrying platform; Controlling the manipulator to move the target chip based on the displacement; Controlling the manipulator to move the target chip in a direction perpendicular to the plane where the controllable carrying platform is located, until the target chip is moved to an installation area corresponding to the target position; The vacuum chamber corresponding to the mounting area corresponding to the target position is controlled to form a vacuum so as to fix the target chip.

6. The method according to claim 3, characterized in that The controllable carrying platform includes a plurality of independent installation areas, and the plurality of independent installation areas are movable in any direction parallel to the plane where the installation areas are located through the action of the fine-tuning component; The correcting the position of the target chip comprises: Determine the position information of the target chip, and determine the position information of at least one reference chip; wherein the reference chip is the chip in the same group of the chipset whose position offset does not exceed the position accuracy threshold; Based on the position information of the target chip and the position information of the reference chip, the installation area corresponding to the target chip is controlled to move.

7. The method according to claim 6, characterized in that The step of controlling the movement of the installation area corresponding to the target chip based on the position information of the target chip and the position information of the reference chip includes: Determining a target position of the target chip based on the position information of the target chip and the position information of the reference chip; Determining a position compensation amount of the installation area corresponding to the target chip based on the target position; The mounting area corresponding to the target chip is controlled to move based on the position compensation amount.

8. The method according to claim 3, characterized in that The controllable carrying platform is provided with the identification point; before fixing the chipset to the controllable carrying platform, or fixing multiple chips to the controllable carrying platform, the method further includes: Determine the position information of all the chips based on the identification points on the chip surface, and determine the position information of the installation area on the controllable carrying platform based on the identification points on the controllable carrying platform; The chip is fixed to the mounting area based on the position information of the chip and the position information of the mounting area.

9. The method according to claim 1, characterized in that: After the position of the target chip is corrected, the method further includes: Returning to the step of detecting the chipset fixed on the controllable carrying platform; The method further comprises: It is determined that the number of corrections reaches the number threshold and an alarm message is generated.

10. The method according to claim 1, characterized in that After the position of the target chip is corrected, the method further includes: Transferring the chipset from the controllable carrying platform to a target carrier, and keeping the relative positions of all the chips in the chipset unchanged; Wherein, the target carrier is used to encapsulate the chipset.

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