Vertical gallium oxide device with optimized heat dissipation and preparation method thereof

Abstract

The invention discloses a gallium oxide device capable of optimizing heat dissipation and a preparation method thereof, and mainly solves the problem that the existing gallium oxide device is poor in heat dissipation performance in the aspect of power electronic application. The device comprises a cathode (1), a gallium oxide substrate (2), a gallium oxide epitaxial layer (3), anode metal (4) and a passivation layer (5) from bottom to top, and optimized heat dissipation areas (6) are arranged around the gallium oxide epitaxial layer and the upper portion of the gallium oxide epitaxial layer or around the gallium oxide epitaxial layer and the whole periphery of the gallium oxide substrate. The heat dissipation capability of the surface of the device is further improved by combining the passivation layer with high thermal conductivity, and heat in the device is released. The two optimized heat dissipation area structures can be achieved through different etching depths on the surface of the gallium oxide epitaxial layer, the overall heat dissipation performance of the device is improved, performance degradation caused by the self-heating effect of the device is avoided, the reliability of the device is improved, the service life of the device is prolonged, and the gallium oxide epitaxial structure can be used for high-power electronic equipment and high-power radio frequency equipment.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor technology, and specifically relates to a vertical gallium oxide device, which can be used in high-power electronic equipment and high-power radio frequency equipment, such as power electronics, automotive-grade inverters, high-voltage power grids, communication base stations, etc. Background Art

[0002] Gallium oxide is one of the hottest semiconductor materials at present. Compared with traditional semiconductor materials Si, Ge, and third-generation semiconductor materials SiC and GaN, it has a bandgap of 4.5-4.9eV and a critical breakdown field strength of about 8MV / cm, which is more than twenty times that of silicon materials and more than twice that of SiC and GaN materials. The superior material properties enable it to achieve smaller size and lower power consumption at the same voltage resistance level, thereby achieving greater power density, better frequency characteristics, and lower power loss. It can be widely used in miniaturized RF power devices and has broad application prospects under the current trend of 5G+IoT. Gallium oxide crystals exist in five crystal forms: α, β, γ, δ, and ε. Among them, β-phase Ga2O3 has been widely studied and applied due to its chemical stability and direct bandgap characteristics. The thermal conductivity of gallium oxide is 0.1-0.3. The low thermal conductivity causes gallium oxide devices to have serious heat dissipation problems, which is one of the problems that power devices must solve.

[0003] For gallium oxide devices, the low-doped epitaxial layer is usually the main area where heat is generated due to its large resistance, and the heat dissipation of vertical devices can only be optimized through the anode and the gallium oxide substrate. The commonly used solution is usually to optimize the heat dissipation at the upper and lower ends of the device through high thermal conductivity materials, such as double-sided silver sintering packaging and high thermal conductivity material heterogeneous integration technology. These technologies can better dissipate the heat on the upper and lower surfaces of the device, but for thicker epitaxial layers, the internal heat accumulation causes a self-heating effect that degrades the characteristics of the device. This technology has limited improvement in the heat dissipation capacity of devices with thicker epitaxial layers used in high-voltage and high-power applications.

[0004] Patent document with application number CN201911174463.9 discloses a gallium oxide semiconductor structure, a vertical gallium oxide-based power device and a preparation method, which transfers the gallium oxide layer to a heterogeneous substrate with high thermal conductivity by heterogeneous bonding and thinning, and improves the heat dissipation capacity of the device by the heterogeneous substrate with high thermal conductivity. However, this method can only improve the heat dissipation capacity of the device surface, and cannot handle the heat inside the device well, and the heat dissipation efficiency is low.

[0005] Patent document CN202011207956.0 discloses a flip-chip MOSFET device and a preparation method, which improves the surface heat dissipation efficiency by etching a micrometer-scale or nanometer-scale array on the back of a gallium oxide substrate and increasing the heat dissipation area on the back of the device. Although this method improves the heat dissipation efficiency of the device surface, for high-power devices, the heat inside the thicker gallium oxide layer still cannot be released well. Summary of the invention

[0006] The purpose of the present invention is to address the deficiencies of the above-mentioned prior art and to propose a vertical gallium oxide device and a preparation method for optimizing heat dissipation, so as to reduce the characteristic degradation of the device due to the self-heating effect and improve the overall heat dissipation performance of the device.

[0007] The technical idea for achieving the purpose of the present invention is to improve the surface heat dissipation capacity of the device through thinning process and high thermal conductivity material integration technology, and to better release the heat inside the device through the optimized heat dissipation structure of etching and filling, thereby improving the heat dissipation performance inside the device.

[0008] According to the above ideas, the technical solutions of the present invention include the following:

[0009] Technical solution 1: A vertical gallium oxide device with optimized heat dissipation, comprising, from bottom to top, a cathode metal (1), a highly doped gallium oxide (2), a gallium oxide epitaxial layer (3), an anode metal (4) and a passivation layer (5), characterized in that an optimized heat dissipation area (6) is provided on the substrate on both sides of the gallium oxide epitaxial layer to improve the overall heat dissipation efficiency of the device.

[0010] Technical Solution 2: A vertical gallium oxide device with optimized heat dissipation, comprising from bottom to top: a cathode metal (1), a gallium oxide highly doped substrate (2), a gallium oxide epitaxial layer (3), an anode metal (4) and a passivation layer (5), characterized in that: optimized heat dissipation areas (6) are provided on both sides of the gallium oxide epitaxial layer and the gallium oxide highly doped substrate to improve the overall heat dissipation efficiency of the device.

[0011] Preferably, the optimized heat dissipation zone (6) has a thickness of 100nm-500μm, a width of 1um-10mm, and a distance from the anode metal (4) of 50nm-1mm. The deposited material is a material with high thermal conductivity, such as diamond, silicon nitride, aluminum nitride and silicon carbide.

[0012] Preferably, the gallium oxide highly doped substrate (2) has a thickness of 100 μm-3 mm and a doping concentration of 1×10 16 ~1×10 20 cm -3 .

[0013] Preferably, the gallium oxide epitaxial layer (3) has a thickness of 100 nm-800 μm and a doping concentration of 1×10 15 ~1×10 19 cm -3 .

[0014] Preferably, the passivation layer (5) is made of any one of aluminum oxide, aluminum nitride and silicon nitride, and has a thickness of 0-3 mm.

[0015] Technical Solution 3: A method for preparing a vertical gallium oxide device for optimizing heat dissipation, characterized in that it comprises the following steps:

[0016] 1) Selecting a gallium oxide epitaxial wafer having a highly doped substrate layer and a low doped epitaxial layer, and pre-treating the wafer;

[0017] 2) Optimize the preparation of heat dissipation area

[0018] 2a) etching the two sides of the low-doped epitaxial layer of the pre-treated gallium oxide epitaxial wafer to form two heat dissipation areas with a spacing of 50nm-1mm, a width of 1um-10mm, and a depth of 10nm-10μm;

[0019] 2b) depositing a material with a high thermal conductivity of 100 nm to 12 μm in thickness on the entire sample surface where the heat dissipation area is etched by HPCVD, LPCVD or PECVD process, wherein the material is any one of diamond, silicon nitride, aluminum nitride and silicon carbide;

[0020] 2c) performing chemical mechanical polishing on the surface of the sample after the deposition to remove excess deposited material and form two optimized heat dissipation zones;

[0021] 3) Evaporation electrode

[0022] 3a) performing CMP thinning on the highly doped substrate layer on the back of the gallium oxide epitaxial wafer to a thickness of 50 nm to 3 mm, preparing a Ti / Au cathode with a thickness of 20 nm to 500 nm on the surface of the thinned highly doped gallium oxide substrate by electron beam evaporation, and performing annealing to form an ohmic contact;

[0023] 3b) using any combination of Ni / Au, Mo / Au and Pt / Au to evaporate a metal with a thickness of 20nm-500nm on the surface of the low-doped epitaxial layer of the device by electron beam evaporation to form an anode;

[0024] 4) Deposition of passivation layer

[0025] Aluminum oxide or aluminum nitride or silicon nitride with a thickness of 10nm-3mm is deposited on the surface of the gallium oxide low-doped epitaxial layer prepared for the anode and the surface of the gallium oxide high-doped substrate prepared for the cathode by ALD or PECVD method to form a passivation layer (5) to complete the device preparation.

[0026] Compared with the prior art, the present invention has the following advantages.

[0027] Firstly, since the present invention prepares the optimized heat dissipation area on the gallium oxide epitaxial layer, the heat generated by the junction area of ​​the device with a thinner epitaxial layer can be well released through the optimized heat dissipation area around it, thereby improving the heat dissipation capacity of the device.

[0028] Secondly, for thick epitaxial layer devices used in high-voltage applications, by preparing an optimized heat dissipation zone around the gallium oxide epitaxial layer and the highly doped substrate, the heat inside the device can be well released, effectively improving the overall heat dissipation capacity of the device.

[0029] Thirdly, the present invention can reduce the thermal resistance caused by the thickness of the substrate by thinning the highly doped gallium oxide substrate layer during the preparation process, thereby greatly improving the heat dissipation capacity of the device substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0031] Figure 1 It is a schematic diagram of the cross-sectional structure of the device of technical solution 1 of the present invention;

[0032] Figure 2 This is a schematic diagram of the cross-sectional structure of a device according to technical solution 2 of the present invention;

[0033] Figure 3 The present invention is prepared Figure 1 , Figure 2 Device implementation flow chart;

[0034] Figure 4 Schematic diagram of the device structure described in the embodiment. DETAILED DESCRIPTION

[0035] The embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0036] Reference Figure 1The vertical gallium oxide device with optimized heat dissipation involved in technical solution 1 of the present invention comprises a cathode metal 1, a gallium oxide highly doped substrate 2, a gallium oxide epitaxial layer 3, an anode metal 4, a passivation layer 5, and an optimized heat dissipation area 6, wherein:

[0037] The gallium oxide highly doped substrate 2 has a thickness of 100 μm-3 mm and a doping concentration of 1×10 16 ~1×10 20 cm -3 . ;

[0038] The cathode 1 is located at the bottom of the gallium oxide high-doped substrate 2, has a thickness of 20nm-500nm, and is made of Ti / Au;

[0039] The gallium oxide epitaxial layer 3 is located on the upper part of the gallium oxide highly doped substrate 2, and has a thickness of 100nm-800μm and a doping concentration of 1×10 15 ~1×10 19 cm -3 .

[0040] The anode metal 4 is located on the upper part of the gallium oxide epitaxial layer 3, and its material is any combination of Ni / Au, Mo / Au and Pt / Au, and its thickness is 20nm-500nm;

[0041] The passivation layer 5 is located on the upper part of the anode metal 4 and the surface of the cathode 1, has a thickness of 10nm-3mm, and the deposited material is any one of aluminum oxide, aluminum nitride and silicon nitride.

[0042] The optimized heat dissipation zone 6 is located around the low-doped epitaxial layer of the gallium oxide epitaxial wafer, has a radius of 50nm-1mm, a width of 1um-10mm, a depth of 10nm-5μm, and the deposited material is any one of diamond, silicon nitride, aluminum nitride and silicon carbide. When the etching depth is greater than the thickness of the epitaxial layer 3, it penetrates the epitaxial layer and extends into the upper part of the highly doped substrate 2.

[0043] Reference Figure 2 The vertical gallium oxide device with optimized heat dissipation involved in technical solution 2 of the present invention comprises a cathode metal 1, a gallium oxide highly doped substrate 2, a gallium oxide epitaxial layer 3, an anode metal 4, a passivation layer 5, and an optimized heat dissipation area 6, wherein:

[0044] The structure of the cathode metal 1, the gallium oxide high-doped substrate 2, the gallium oxide epitaxial layer 3, the anode metal 4 and the passivation layer 5 is the same as that of the technical solution 1; the optimized heat dissipation area 6 is located around the gallium oxide high-doped substrate and the low-doped epitaxial layer, and the deposited material is any one of diamond, silicon nitride, aluminum nitride and silicon carbide, and its radius is 50nm-1mm, the width is 1um-10mm, and the depth is 5μm-10μm, which is greater than the overall thickness of the gallium oxide epitaxial layer 3 and the high-doped substrate 2.

[0045] Reference Figure 3 and Figure 4 The present invention provides three embodiments for preparing the above-mentioned device:

[0046] Example 1: On a gallium oxide epitaxial wafer having a highly doped substrate layer and a low doped epitaxial layer, an aluminum oxide passivation layer with a thickness of 200 nm, an optimized heat dissipation zone with an etching depth of 5 μm and a radius of 50 μm and a deposition material of diamond, an optimized heat dissipation vertical gallium oxide device is prepared.

[0047] Step 1: Select a gallium oxide epitaxial wafer and pre-treat it.

[0048] 1.1) The thickness of the highly doped substrate layer is 500 μm and the doping concentration is 1×10 19 cm -3 The thickness of the low-doped epitaxial layer is 10 μm and the doping concentration is 1×10 18 cm -3 Gallium oxide epitaxial wafer samples, such as Figure 3 (a)

[0049] 1.2) The gallium oxide epitaxial wafer sample was placed in an acetone solution for ultrasonic cleaning for 5 minutes, and then placed in an isopropanol solution or anhydrous ethanol for ultrasonic cleaning for 5 minutes, and then the substrate was placed in deionized water for ultrasonic cleaning for 5 minutes to remove organic impurities on the surface of the gallium oxide;

[0050] 1.3) After the organic cleaning, the sample was placed in piranha solution for 10 minutes of surface optimization treatment, and then washed with deionized water for 5 minutes.

[0051] Step 2: Etching optimized heat dissipation area 6

[0052] 2.1) The pre-treated gallium oxide epitaxial wafer sample is patterned in the etching area with a photoresist, and then the sample is placed in an ICP plasma etcher for etching to a depth of 5 μm, and the photoresist used as a mask is removed by organic cleaning;

[0053] 2.2) setting the process conditions of chamber pressure to 30 tor, temperature to 800°C, microwave power to 500W, gas to 50sccm H2, 120sccm CH4 and 100sccm O2 respectively, and depositing diamond with a thickness of 5.5μm in the etched area by HPCVD equipment;

[0054] 2.3) For the sample with diamond deposited, the excess deposited material on the surface is removed by chemical mechanical polishing to obtain a gallium oxide epitaxial wafer sample with an optimized heat dissipation area around the gallium oxide epitaxial layer and extending into the upper part of the gallium oxide highly doped substrate, such as Figure 3 (b) as shown.

[0055] Step 3, Evaporation of Electrode

[0056] 3.1) Prepare Ti / Au cathodes with a thickness of 60nm / 120nm on the highly doped substrate surface of the gallium oxide epitaxial wafer sample by electron beam evaporation, such as Figure 3 (c)

[0057] 3.2) The annealing temperature is set to 400°C and the annealing time is 1 min. The sample in step 3.1) is subjected to thermal annealing to form an ohmic contact, and a Mo / Au anode with a thickness of 60nm / 120nm is deposited on the surface of the epitaxial layer. Figure 3 (d) as shown.

[0058] Step 4, deposit a passivation layer, such as Figure 3 (e).

[0059] The device is prepared by depositing a 200nm thick aluminum oxide passivation layer on the surface of the prepared anode gallium oxide low-doped epitaxial layer using an ALD device.

[0060] Example 2: A vertical gallium oxide device with optimized heat dissipation is prepared on a gallium oxide epitaxial wafer with a highly doped substrate layer and a low doped epitaxial layer. The thickness of the silicon nitride passivation layer is 120 nm, the etching depth of the optimized heat dissipation area is 25 μm, the radius is 150 μm, and the deposition material is silicon oxide.

[0061] Step 1: Select gallium oxide epitaxial wafer and pre-treat it

[0062] The thickness of the highly doped substrate layer is 600 μm and the doping concentration is 1×10 19 cm -3 The thickness of the low-doped epitaxial layer is 20 μm and the doping concentration is 1×10 18 cm -3 Gallium oxide epitaxial wafer samples, such as Figure 3 (a)

[0063] The gallium oxide epitaxial wafer sample is placed in an acetone solution for ultrasonic cleaning for 8 minutes, then placed in a propanol solution or anhydrous ethanol for ultrasonic cleaning for 8 minutes, and then the substrate is placed in deionized water for ultrasonic cleaning for 8 minutes to remove organic impurities on the surface of the gallium oxide;

[0064] After the organic cleaning, the sample was placed in piranha solution for 20 minutes of surface optimization treatment, and then washed with deionized water for 8 minutes.

[0065] Step 2: etching the optimized heat dissipation area 6, such as Figure 3 (b).

[0066] The surface of the pretreated gallium oxide epitaxial wafer sample is patterned with a photoresist in the etching area, and the sample is placed in an ICP plasma etcher for etching to a depth of 25 μm, and then the photoresist used as a mask is removed by organic cleaning;

[0067] Using LPCVD equipment, under the process conditions of chamber pressure of 120mtoor, temperature of 600℃, microwave power of 300W, gas of 200sccmSiH4 and 100sccmO2, silicon oxide with a thickness of 10μm was deposited in the etched area;

[0068] The excess deposited material on the surface of the gallium oxide epitaxial layer is removed by chemical mechanical polishing to obtain a gallium oxide epitaxial wafer sample with an optimized heat dissipation area around the gallium oxide epitaxial layer and extending into the upper part of the gallium oxide high-doped substrate, such as Figure 3 (b) as shown.

[0069] Step 3: Evaporation of electrodes

[0070] Ti / Au cathodes with a thickness of 80 nm / 200 nm were prepared on the highly doped substrate surface of the gallium oxide epitaxial wafer sample by electron beam evaporation. Figure 3 (c)

[0071] The sample with the Ti / Au cathode deposited was subjected to a thermal annealing treatment for 2 min at a temperature of 460°C to form an ohmic contact;

[0072] Then, a Pt / Au anode with a thickness of 80nm / 200nm is deposited on the surface of the epitaxial layer of the gallium oxide epitaxial wafer sample. Figure 3 (d) as shown.

[0073] Step 4: deposit a passivation layer, such as Figure 3 (e).

[0074] A silicon nitride passivation layer with a thickness of 120 nm is deposited on the surface of the gallium oxide low-doped epitaxial layer after evaporating the electrode to complete the device preparation.

[0075] Example 3: An optimized heat dissipation vertical gallium oxide device with an aluminum nitride passivation layer thickness of 150 nm, an optimized heat dissipation area etching depth of 120 μm, a radius of 150 μm, and a deposition material of silicon oxide is prepared on a gallium oxide epitaxial wafer with a highly doped substrate layer and a low doped epitaxial layer.

[0076] Step A: Select gallium oxide epitaxial wafer and pretreat it

[0077] A1) The thickness of the highly doped substrate layer is 400 μm and the doping concentration is 2×10 19 cm -3 The thickness of the low-doped epitaxial layer is 40 μm and the doping concentration is 2×10 18 cm -3 Gallium oxide epitaxial wafer samples, such as Figure 4 (a)

[0078] A2) placing the gallium oxide epitaxial wafer sample in an acetone solution for ultrasonic cleaning for 10 minutes, then placing it in an isopropanol solution or anhydrous ethanol for ultrasonic cleaning for 10 minutes, and then placing the substrate in deionized water for ultrasonic cleaning for 10 minutes to remove organic impurities on the surface of the gallium oxide;

[0079] A3) After the organic cleaning, the sample was placed in piranha solution for 30 minutes of surface optimization treatment, and then rinsed with deionized water for 10 minutes.

[0080] Step B, etching the optimized heat dissipation area 6, such as Figure 4 (b).

[0081] B1) performing patterning of the etching area on the pretreated gallium oxide epitaxial wafer sample using silicon oxide as a mask, then placing the sample in an ICP plasma etcher for etching to a depth of 120 μm, and removing the silicon oxide used as a mask by inorganic cleaning;

[0082] B2) depositing silicon oxide with a thickness of 130 μm in the etched area by PECVD equipment, wherein the deposition process conditions are: chamber pressure of 15 mtoor, temperature of 300° C., microwave power of 200 W, gas of 50 sccm NH 3 , 50 sccm SiH 4 and 120 sccm O 2 ;

[0083] B3) For the sample deposited with silicon oxide, excess deposited material on the surface of the gallium oxide epitaxial layer is removed by chemical mechanical polishing to obtain a gallium oxide epitaxial wafer sample having an optimized heat dissipation area around the gallium oxide highly doped substrate and the gallium oxide epitaxial layer.

[0084] Step C, Evaporation of Electrode

[0085] C1) Thinning the highly doped substrate of the gallium oxide epitaxial wafer sample to a thickness of 320 μm.

[0086] C2) A Ti / Au cathode with a thickness of 100nm / 300nm is prepared on the surface of the thinned highly doped substrate of the gallium oxide epitaxial wafer sample by electron beam evaporation, such as Figure 4 (c)

[0087] C3) performing thermal annealing on the gallium oxide epitaxial wafer sample after step C1) to form an ohmic contact, the annealing temperature is 500° C., and the duration is 5 minutes.

[0088] C4) depositing a Ni / Au anode with a thickness of 100nm / 300nm on the epitaxial layer surface of the annealed sample, such as Figure 4 (d) as shown.

[0089] Step D, depositing a passivation layer, such as Figure 4 (e).

[0090] A silicon nitride passivation layer with a thickness of 120 nm is deposited on the surface of the gallium oxide low-doped epitaxial layer of the prepared anode to complete the device preparation.

[0091] The above description is only a specific example of the present invention and does not constitute any limitation to the present invention. Obviously, for professionals in this field, after understanding the content and principles of the present invention, it is possible to make various modifications and changes in form and details without departing from the principles and structures of the present invention. For example, in addition to the HPCVD, PECVD and LPCVD mentioned above, other material deposition equipment such as ALD or MOCVD can be used to deposit the optimized heat dissipation area material. The process parameters of the deposited material can also be modified and changed according to different equipment and material requirements. However, these modifications and changes based on the ideas of the present invention are still within the scope of protection of the claims of the present invention.

Claims

1. A vertical gallium oxide device for optimizing heat dissipation, comprising, from bottom to top, a cathode metal (1), a highly doped gallium oxide (2), a gallium oxide epitaxial layer (3), an anode metal (4) and a passivation layer (5), characterized in that: An optimized heat dissipation area (6) is provided on the substrate surrounding the gallium oxide epitaxial layer, for improving the overall heat dissipation efficiency of the device.

2. A vertical gallium oxide device with optimized heat dissipation, including from bottom to top: A cathode metal (1), a gallium oxide highly doped substrate (2), a gallium oxide epitaxial layer (3), an anode metal (4) and a passivation layer (5), characterized in that an optimized heat dissipation area (6) is provided around the gallium oxide epitaxial layer and the gallium oxide highly doped substrate to improve the overall heat dissipation efficiency of the device.

3. The device according to claim 1 or 2, characterized in that: The optimized heat dissipation area (6) has a thickness of 100nm-500μm, a width of 1um-10mm, and a distance from the anode metal (4) of 50nm-1mm. The deposited material is a material with high thermal conductivity, which is any one of diamond, silicon nitride, aluminum nitride and silicon carbide.

4. The device according to claim 1 or 2, characterized in that: The gallium oxide highly doped substrate (2) has a thickness of 100 μm-3 mm and a doping concentration of 1×10 16 ~1×10 20 cm -3 .

5. The device according to claim 1 or 2, characterized in that: The gallium oxide epitaxial layer (3) has a thickness of 100 nm-800 μm and a doping concentration of 1×10 15 ~1×10 19 cm -3 .

6. The device according to claim 1 or 2, characterized in that: The passivation layer (5) is made of any one of aluminum oxide, aluminum nitride and silicon nitride, and has a thickness of 0-3 mm.

7. A method for preparing a vertical gallium oxide device with optimized heat dissipation, characterized in that: The steps include: 1) Selecting a gallium oxide epitaxial wafer having a highly doped substrate layer and a low doped epitaxial layer, and pre-treating the wafer; 2) Optimize the preparation of heat dissipation area 2a) etching around the low-doped epitaxial layer of the pre-treated gallium oxide epitaxial wafer to form two heat dissipation areas with a spacing of 50nm-1mm, a width of 1um-10mm, and a depth of 10nm-10μm; 2b) depositing a material with a high thermal conductivity of 100 nm to 12 μm in thickness on the entire sample surface where the heat dissipation area is etched by HPCVD, LPCVD or PECVD process, wherein the material is any one of diamond, silicon nitride, aluminum nitride and silicon carbide; 2c) performing chemical mechanical polishing on the surface of the sample after the deposition to remove excess deposited material and form two optimized heat dissipation zones; 3) Evaporation electrode 3a) performing CMP thinning on the highly doped substrate layer on the back of the gallium oxide epitaxial wafer to a thickness of 50 nm to 3 mm, preparing a Ti / Au cathode with a thickness of 20 nm to 500 nm on the surface of the thinned highly doped gallium oxide substrate by electron beam evaporation, and performing annealing to form an ohmic contact; 3b) using any combination of Ni / Au, Mo / Au and Pt / Au to evaporate a metal with a thickness of 20nm-500nm on the surface of the low-doped epitaxial layer of the device by electron beam evaporation to form an anode; 4) Deposition of passivation layer Aluminum oxide or aluminum nitride or silicon nitride with a thickness of 10nm-3mm is deposited on the surface of the gallium oxide low-doped epitaxial layer prepared for the anode and the surface of the gallium oxide high-doped substrate prepared for the cathode by ALD or PECVD method to form a passivation layer (5) to complete the device preparation.

8. The method according to claim 5, characterized in that: In step 1), the gallium oxide epitaxial wafer is pre-treated as follows: 1a) Organic cleaning: Place the sample in an acetone solution and ultrasonically clean it for 5-10 minutes, then place it in an isopropanol solution or anhydrous ethanol and ultrasonically clean it for 10 minutes, and finally place the sample in deionized water and ultrasonically clean it for 5-10 minutes to remove organic impurities on the sample surface. 1b) Piranha treatment: After the organic cleaning, the sample is placed in a piranha solution for 10-30 minutes for surface optimization treatment, and then washed with deionized water for 5-10 minutes to complete the sample pretreatment.

9. The method according to claim 5, characterized in that: The conditions for annealing the sample in step 3a) are: annealing temperature is 400° C.-500° C., and annealing time is 1 min-10 min.

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