Multi-channel SCR device with adjustable trigger voltage and maintaining voltage for ESD protection of high-voltage integrated circuit

Abstract

The invention belongs to the field of design of an electrostatic discharge (ESD) protection device of a high-voltage integrated circuit (IC), aims at an improved lateral silicon controlled rectifier (MLSCR), and particularly provides a multi-channel SCR device which is used for ESD protection of the high-voltage integrated circuit and is adjustable in trigger voltage and maintaining voltage, and the multi-channel SCR device can be used for achieving ESD protection of an input / output port (I / O for short) and a power domain. The device comprises two MLSCR structures, has the advantages of being adjustable in trigger voltage and maintaining voltage, high in latch-up resistance, high in robustness and the like, and can be suitable for integrated circuit ESD protection under various high-voltage power supply domains.

Description

Technical Field

[0001] The present invention belongs to the field of electrostatic discharge (ESD) protection device design of high voltage integrated circuits (ICs), and specifically relates to an ESD protection structure device, in particular to a modified lateral silicon controlled rectifier (MLSCR). Background Art

[0002] ESD refers to the phenomenon of charge transfer between two objects with different electrostatic potentials, which is one of the main causes of damage to electronic components and ICs. ESD damage is hidden, latent, random and complex. With the development of semiconductor process technology, IC failure and damage caused by ESD have become an increasingly serious problem. Therefore, it is very important to study the ESD protection scheme of IC chips.

[0003] In a specific semiconductor process, ESD protection devices need to meet a certain ESD design window when working, that is, the safe operating range of the device should be less than the minimum breakdown voltage of the protected circuit and greater than the operating voltage of the protected circuit. For ESD protection devices with hysteresis characteristics, the trigger voltage and the holding voltage should be within the ESD design window. In the design of ESD protection devices for high-voltage integrated circuits, the holding voltage and trigger voltage of ESD protection devices need to meet the requirements of higher operating voltages. The characteristics of ESD protection devices that meet the appropriate design window and have high robustness have always been the focus and difficulty of ESD protection device design. Therefore, it is of great significance to design ESD protection devices with adjustable trigger voltage and holding voltage, strong anti-latch capability and high robustness.

[0004] There is a traditional ESD protection device MLSCR with hysteresis characteristics, which has the characteristics of high robustness, simple structure, high area utilization, etc., and is very suitable for ESD protection in chips. The device structure is as follows Figure 1 As shown, including: A P-type substrate 110, on which a first N-type doping region 120 and a first P-type doping region 130 are formed; the first N-type doping region is horizontally tangent to the first P-type doping region; In the first N-type doping region 120, a first P-type heavily doped region 140 and a first N-type heavily doped region 150 are sequentially provided from near to far with reference to the first P-type doping region 130; a second P-type heavily doped region 141 spanning the first N-type doping region 120 and the first P-type doping region 130 is provided between the two regions; in the first P-type doping region 130, a second N-type heavily doped region 151 and a third P-type heavily doped region 142 are sequentially provided from near to far with reference to the first N-type doping region 120; The first N-type heavily doped region 150 and the first P-type heavily doped region 140 are connected to the anode; the second N-type heavily doped region 151 and the third P-type heavily doped region 142 are connected to the cathode; Shallow trench isolation is respectively provided between the first N-type heavily doped region 150 and the first P-type heavily doped region 140 , between the first P-type heavily doped region 140 and the second P-type heavily doped region 141 , between the second P-type heavily doped region 141 and the second N-type heavily doped region 151 , and between the second N-type heavily doped region 151 and the third N-type heavily doped region 142 .

[0005] The device has a parasitic PNP transistor, a parasitic NPN transistor, a parasitic reverse diode, and two well resistors: The first parasitic PNP transistor Q p1 , including a first P-type heavily doped region 140, a first N-type doped region 120, and a first P-type doped region 130; the first parasitic NPN transistor Q n1 , including a first N-type doping region 120, a first P-type doping region 130, and a second N-type heavily doped region 151; the first parasitic reverse diode D1, including a first N-type doping region 120, a second P-type heavily doped region 141; the first well resistor R NW , including a first N-type doped region 120 well resistor; the second well resistor R PW , including a first P-type doping region 130 well resistor.

[0006] Working principle of the device: When the ESD event reaches the anode of the device and the ESD voltage is greater than the breakdown voltage of the device D1, a current will flow through R NW , D1, R PW , that is, the current flows from the anode to the cathode in sequence through the first N-type heavily doped region 150, the first N-type doped region 120, the second P-type heavily doped region 141, the first P-type doped region 130, and the third P-type heavily doped region 142. As the current increases, R NW and R PW The pressure drop increases, making Q n1 and Q p1 On. n1 and Q p1The collector current increases, at R NW and R PW The pressure drop on Q continues to increase. n1 and Q p1 The emitter junction voltage increases, coupling between the parasitic NPN transistor and the parasitic PNP transistor to form a positive feedback, and the SCR channel is turned on.

[0007] The conventional MLSCR can effectively control the trigger voltage through the breakdown voltage of the parasitic reverse diode D1, but its main way of discharging ESD current is still through the SCR channel. Although the SCR channel has a strong ESD current discharge capability, due to the positive feedback between its two bipolar transistors, the maintenance voltage of the SCR channel is about 1.5V. This maintenance voltage cannot meet the requirements of the ESD protection design of high-voltage integrated circuits, and latch-up phenomenon is prone to occur, making the device unable to shut down and affecting the normal operation of the circuit, and in severe cases, causing chip damage.

[0008] Therefore, the present invention proposes an MLSCR device capable of regulating the trigger voltage and the holding voltage, and the device has more trigger channels and more ESD current discharge channels. Different trigger channels can adjust the trigger voltage, and different ESD current discharge channels can adjust the holding voltage, thereby making it suitable for ESD protection of integrated circuits under various high-voltage power domains. In addition, its multi-channel characteristics also make it have the characteristics of high robustness and high area utilization. Summary of the invention

[0009] The purpose of the present invention is to provide a multi-channel SCR device with adjustable trigger voltage and holding voltage for high-voltage integrated circuit ESD protection. The device has the characteristics of adjustable trigger voltage and holding voltage, strong anti-latch capability and high robustness, and can be applied to high-voltage integrated circuit ESD protection in various power domains. The technical solution adopted by the present invention is: A multi-channel MLSCR device with adjustable trigger voltage and holding voltage, comprising: The device comprises a P-type silicon substrate, a first N-type doping region is formed on the P-type silicon substrate; a second N-type doping region, a third N-type doping region, and a first P-type doping region are formed on the first N-type doping region; the first P-type doping region is completely surrounded by the first N-type doping region, the second N-type doping region, and the third N-type doping region; The second N-type doping region is provided with a first P-type heavily doped region; a second P-type heavily doped region is provided between the second N-type doping region and the first P-type doping region and spans the two regions; a third P-type heavily doped region and a first N-type heavily doped region are provided in the first P-type doping region in sequence from near to far with the second P-type heavily doped region as a reference; the third N-type doping region is provided with a second N-type heavily doped region; The first P-type heavily doped region and the second N-type heavily doped region are connected to the anode; the third P-type heavily doped region and the first N-type heavily doped region are connected to the cathode; Shallow trench isolation is provided between the second P-type heavily doped region and the third P-type heavily doped region, between the third P-type heavily doped region and the first N-type heavily doped region, and between the first N-type heavily doped region and the second N-type heavily doped region; The first P-type doping region is formed by longitudinally stacking one or more P-type doping regions with different doping doses, and the first N-type doping region, the second N-type doping region, and the third N-type doping region are formed by longitudinally stacking one or more N-type doping regions with different doping doses.

[0010] The device has two parasitic PNP transistors, three parasitic NPN transistors, and three well resistors: The first parasitic PNP transistor includes a first P-type heavily doped region, a second N-type doped region, a second P-type heavily doped region, a first P-type doped region, and a third P-type heavily doped region; the second parasitic PNP transistor includes a first P-type heavily doped region, a second N-type doped region, and a first P-type doped region; the first parasitic NPN transistor includes a second N-type heavily doped region, a third N-type doped region, a first P-type doped region, and a first N-type heavily doped region; the second parasitic lateral NPN transistor includes a second N-type doped region, a first P-type doped region, a third N-type doped region, a first an N-type heavily doped region; the third parasitic vertical NPN transistor includes a first N-type doping region, a first P-type doping region, and a first N-type heavily doped region; the first well resistor includes a well resistor of a first P-type well region; the second well resistor includes a well resistor of a third N-type doping region in the first N-type doping region with reference to the first N-type heavily doped region and a well resistor of the third N-type doping region; the third well resistor includes a well resistor of a second N-type doping region in the first N-type doping region with reference to the first N-type heavily doped region.

[0011] The first parasitic PNP transistor forms a PNP channel; the first parasitic NPN transistor forms an NPN channel; the second parasitic PNP transistor, the second parasitic lateral NPN transistor, the third parasitic vertical NPN transistor, the first well resistor, the second well resistor, and the third well resistor together form an SCR channel.

[0012] The present invention provides a multi-channel SCR device with adjustable trigger voltage and holding voltage for ESD protection of high-voltage integrated circuits. In addition to inheriting the high robustness, simple structure, high area utilization and other characteristics of traditional MLSCR devices, the device also has the advantages of adjustable trigger voltage and holding voltage and strong anti-latch capability. Compared with traditional MLSCR devices, the triggering mode of the device is optimized, and it is triggered by a PNP channel or an NPN channel. The adjustability of its trigger voltage can be adjusted by regulating the BV of the first parasitic PNP transistor and the first parasitic NPN transistor. CEO (common emitter-collector junction avalanche breakdown voltage of a bipolar transistor); the main ESD discharge paths of the device are the PNP path and the SCR path, and the holding voltage can be adjusted by regulating the current ratio of the PNP channel and the SCR channel, so as to avoid the occurrence of the latch-up effect and make the device suitable for different ESD design windows.

[0013] An optimized multi-channel MLSCR device with adjustable trigger voltage and holding voltage, comprising: The device comprises a P-type silicon substrate, a first N-type doping region is formed on the P-type silicon substrate; a second N-type doping region, a third N-type doping region, and a first P-type doping region are formed on the first N-type doping region; the first P-type doping region is completely surrounded by the first N-type doping region, the second N-type doping region, and the third N-type doping region; The second N-type doping region is provided with a first P-type heavily doped region; a second P-type heavily doped region spanning the second N-type doping region and the first P-type doping region is provided between the two regions; a third P-type heavily doped region and a first N-type heavily doped region are provided in the first P-type doping region in order from near to far with the second P-type heavily doped region as a reference; a fourth P-type heavily doped region spanning the two regions is provided between the third N-type doping region and the first P-type doping region; the third N-type doping region is provided with a second N-type heavily doped region; The first P-type heavily doped region and the second N-type heavily doped region are connected to the anode; the third P-type heavily doped region and the first N-type heavily doped region are connected to the cathode; Shallow trench isolation is provided between the second P-type heavily doped region and the third P-type heavily doped region, between the third P-type heavily doped region and the first N-type heavily doped region, and between the first N-type heavily doped region and the fourth P-type heavily doped region.

[0014] The first P-type doping region is formed by longitudinally stacking one or more P-type doping regions with different doping doses, and the first N-type doping region, the second N-type doping region, and the third N-type doping region are formed by longitudinally stacking one or more N-type doping regions with different doping doses.

[0015] The device has two parasitic PNP transistors, three parasitic NPN transistors, and three well resistors: The first parasitic PNP transistor includes a first P-type heavily doped region, a second N-type doped region, a second P-type heavily doped region, a first P-type doped region, and a third P-type heavily doped region; the second parasitic PNP transistor includes a first P-type heavily doped region, a second N-type doped region, and a first P-type doped region; the first parasitic NPN transistor includes a second N-type heavily doped region, a third N-type doped region, a fourth P-type heavily doped region, a first P-type doped region, and a first N-type heavily doped region; the second parasitic lateral NPN transistor includes a second N-type doped region, a first P-type heavily doped region, and a third P-type heavily doped region. doped region, a first N-type heavily doped region; the third parasitic vertical NPN transistor includes a first N-type doped region, a first P-type doped region, and a first N-type heavily doped region; the first well resistor includes a first P-type well resistor; the second well resistor includes a well resistor close to the third N-type doped region in the first N-type doped region with reference to the first N-type heavily doped region and a well resistor of the third N-type doped region; the third well resistor includes a well resistor close to the second N-type doped region in the first N-type doped region with reference to the first N-type heavily doped region and a well resistor of the second N-type doped region.

[0016] The first parasitic PNP transistor forms a PNP channel; the first parasitic NPN transistor forms an NPN channel; the second parasitic PNP transistor, the second parasitic NPN lateral transistor, the third parasitic vertical NPN transistor, the first well resistor, the second well resistor, and the third well resistor together form an SCR channel.

[0017] The present invention provides an optimized multi-channel SCR device with adjustable trigger voltage and holding voltage for high-voltage integrated circuit ESD protection. In addition to having adjustable trigger voltage and holding voltage and strong anti-latch capability, the device mainly optimizes the trigger channel. The device is triggered by a PNP channel or an NPN channel, and its trigger voltage adjustability can be adjusted by adjusting the BV of the first parasitic PNP transistor and the first parasitic NPN transistor. CEO The main ESD discharge paths of the device are the PNP path and the SCR path. The holding voltage can be adjusted by adjusting the current ratio of the PNP channel and the SCR channel to avoid the latch effect and make the device suitable for different ESD design windows. Compared with the device before optimization, the first parasitic PNP transistor and the first parasitic NPN transistor of the optimized device are more similar in structure, so the BV CEO Closer, making the trigger voltage of the device more stable. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 This is the traditional MLSCR structure diagram and equivalent circuit diagram.

[0019] Figure 2 This is the device structure diagram and equivalent circuit diagram described in Example 1.

[0020] Figure 3 This is the device structure diagram and equivalent circuit diagram described in Example 2. DETAILED DESCRIPTION

[0021] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the accompanying drawings and specific implementation methods. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0022] It should be noted that all directional indications in the embodiments of the present invention (such as up, down, left, right, front, back, etc.) are only used to explain the relative position relationship, movement status, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0023] In addition, the descriptions of "first", "second", etc. in the present invention are only for descriptive purposes and cannot be understood as referring to or implying their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" or "second" may explicitly or implicitly include at least one of the features.

[0024] In addition, the technical solutions between the various embodiments can be combined with each other, but it must be based on the fact that ordinary technicians in the field can implement it. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0025] Example 1 This embodiment provides a multi-channel SCR device with adjustable trigger voltage and holding voltage for high-voltage integrated circuit ESD protection. The device structure and equivalent circuit diagram are shown in FIG. Figure 2 shown.

[0026] The device of Embodiment 1 includes a P-type silicon substrate 110, a first N-type doping region 120 is formed on the P-type silicon substrate 110; a second N-type doping region 121, a third N-type doping region 122, and a first P-type doping region 130 are formed on the first N-type doping region 120; the first P-type doping region 130 is completely surrounded by the first N-type doping region 120, the second N-type doping region 121, and the third N-type doping region 122; The second N-type doping region 121 is provided with a first P-type heavily doped region 140; a second P-type heavily doped region 141 is provided between the second N-type doping region 121 and the first P-type doping region 130, spanning the two regions; in the first P-type doping region 130, a third P-type heavily doped region 142 and a first N-type heavily doped region 150 are provided in sequence from near to far with reference to the second P-type heavily doped region 141; the third N-type doping region 122 is provided with a second N-type heavily doped region 151; The first P-type heavily doped region 140 and the second N-type heavily doped region 151 are connected to the anode; the third P-type heavily doped region 142 and the first N-type heavily doped region 151 are connected to the cathode; Shallow trench isolation is respectively provided between the second P-type heavily doped region 141 and the third P-type heavily doped region 142, between the third P-type heavily doped region 142 and the first N-type heavily doped region 150, and between the first N-type heavily doped region 150 and the second N-type heavily doped region 151; The first P-type doping region 130 is formed by longitudinally stacking one or more P-type doping regions with different doping doses, and the first N-type doping region 120, the second N-type doping region 121, and the third N-type doping region 122 are formed by longitudinally stacking one or more N-type doping regions with different doping doses.

[0027] The device described in Example 1 has two parasitic PNP transistors, three parasitic NPN transistors, and three well resistors: The first parasitic PNP transistor Q p1 , including a first P-type heavily doped region 140, a second N-type doped region 121, a second P-type heavily doped region 141, a first P-type doped region 130, and a third P-type heavily doped region 142; the second parasitic PNP transistor Q p2 , including a first P-type heavily doped region 140, a second N-type doped region 121, and a first P-type doped region 130; the first parasitic NPN transistor Q n1 , including a second N-type heavily doped region 151, a third N-type doped region 122, a first P-type doped region 130, and a first N-type heavily doped region 150; the second parasitic lateral NPN transistor Q n2 , including a second N-type doping region 121, a first P-type doping region 130, and a first N-type heavily doped region 150; the third parasitic vertical NPN transistor Q n3 , including a first N-type doping region 120, a first P-type doping region 130, and a first N-type heavily doped region 150; the first well resistor R PW , including a first P-type well region 130 well resistor; the second well resistor R NW1, including a well resistor in the first N-type doping region 120 close to the third N-type doping region 122 and a well resistor in the third N-type doping region 122 with the first N-type heavily doped region 150 as a reference; the third well resistor R NW2 , including a well resistance in the first N-type doping region 120 close to the second N-type doping region 121 and a well resistance in the second N-type doping region 121 with the first N-type heavily doped region 150 as a reference.

[0028] The first parasitic PNP transistor Q p1 The first parasitic NPN transistor Q n1 The second parasitic PNP transistor Q p2 , the second parasitic lateral NPN transistor Q n2 , the third parasitic vertical NPN transistor Q n3 , the first well resistance R PW , the second well resistance R NW1 , the third well resistor R NW2 Together they form the SCR channel. Figure 2 The equivalent circuit is shown in the dashed box.

[0029] The working principle of the device described in Example 1 can be based on Q p1 and Q n1 BV CEO There are two types of sizes: When Q n1 BV CEO Greater than Q p1 , the ESD event reaches the anode of the device described in Example 1, and the ESD voltage is greater than Q p1 BV CEO When the electron current flows through Q p1 The emitter junction flows to the anode of the device described in Example 1, and the hole current flows to the cathode through the second P-type heavily doped region 141, the first P-type doped region 130, and the third P-type heavily doped region 142. At this time, as the anode voltage increases, Q p1 The emitter junction voltage increases, making Q p2 Turn on and conduct current. When the anode voltage increases to Q n1 BV CEO Later, with Q p1 and Q p2 The collector current increases, making R PW The pressure drop increases, so Q n1 Open, followed by Q n2 and Q n3 Q n2 and Q n3 The collector current increases, at R NW1 and R NW2The voltage drop across the p1 and Q p2 The emitter junction voltage increases, and positive feedback is formed between the parasitic NPN transistor and the parasitic PNP transistor. At this point, the SCR channel is turned on. At this time, there are two main ESD discharge channels, namely the SCR channel and the PNP channel. n1 It does not participate in the process of coupling to form positive feedback, so the NPN channel does not serve as the main ESD discharge channel; When Q p1 BV CEO Greater than Q n1 , the ESD event reaches the anode of the device described in Example 1, and the ESD voltage is greater than Q n1 BV CEO When the electron current flows to the anode of the device described in Example 1 through the third N-type doping region 122 and the second N-type heavily doped region 151, the hole current flows through Q n1 The emitter junction flows to the cathode. At this time, as the anode voltage increases, the current flowing through Q n1 The current increases, R PW The voltage drop will increase, making Q n2 and Q n3 Turn on and conduct current. When the anode voltage increases to Q p1 BV CEO After that, along with Q n2 , Q n3 The collector current increases, making R NW1 and R NW2 The pressure drop increases, so Q p1 and Q p2 will turn on, and Q p1 and Q p2 The emitter junction voltage will also increase, coupling between the parasitic NPN transistor and the parasitic PNP transistor to form a positive feedback, so that the SCR channel is turned on. At this time, there are two main ESD discharge channels, namely the SCR channel and the PNP channel. n1 It does not participate in the process of coupling to form positive feedback, so the NPN channel does not serve as the main ESD discharge channel.

[0030] BV CEO The size of can be obtained by the following formula: {BV}_{CEO}\approx \frac {{V}_{B}} {\sqrt[{S}] {β}} Where V B is the PN junction avalanche breakdown voltage, β is the common emitter branch short-circuit current amplification factor, and S is a constant, which is generally 2~6 for silicon.

[0031] Q can be adjusted by adjusting the dosage of the first N-type doping region 120, the second N-type doping region 121, the third N-type doping region 122, and the first P-type doping region 130. p1 and Q n1 V B Q can be adjusted by adjusting the distance between the first P-type heavily doped region 140 and the second P-type heavily doped region 141 and the distance between the first N-type heavily doped region 150 and the third N-type doped region 122. p1 and Q n1 The above method can be used to adjust Q p1 and Q n1 BV CEO , thereby achieving the purpose of regulating the trigger voltage, so that the trigger voltage of the device described in Example 1 is suitable for different ESD design windows.

[0032] The holding voltage of the device described in Example 1 is proportional to the ratio of the current through the PNP channel and the SCR channel. Increasing the current proportion of the PNP channel can effectively increase the holding voltage, and the control of the holding voltage can also be achieved by adjusting the size of the well resistance, that is, mainly through the following methods: Regulate the dosage of the first N-type doping region 120, the second N-type doping region 121, the third N-type doping region 122, and the first P-type doping region 130; regulate the distance between the first P-type heavily doped region 140 and the second P-type heavily doped region 141; regulate the distance between the second N-type doping region 121 and the third P-type heavily doped region 142; regulate the distance between the third P-type heavily doped region 142 and the first N-type heavily doped region 150.

[0033] Example 2 This embodiment provides an optimized multi-channel SCR device with adjustable trigger voltage and holding voltage for high-voltage integrated circuit ESD protection. The device structure and equivalent circuit diagram are shown in FIG. Figure 3 shown.

[0034] The device of Embodiment 2 includes a P-type silicon substrate 110, a first N-type doping region 120 is formed on the P-type silicon substrate 110; a second N-type doping region 121, a third N-type doping region 122, and a first P-type doping region 130 are formed on the first N-type doping region 120; the first P-type doping region 130 is completely surrounded by the first N-type doping region 120, the second N-type doping region 121, and the third N-type doping region 122; The second N-type doping region 121 is provided with a first P-type heavily doped region 140; a second P-type heavily doped region 141 is provided between the second N-type doping region 121 and the first P-type doping region 130, spanning the two regions; a third P-type heavily doped region 142 and a first N-type heavily doped region 150 are provided in the first P-type doping region 141 in order from near to far with reference to the second P-type heavily doped region 141; a fourth P-type heavily doped region 143 is provided between the third N-type doping region 122 and the first P-type doping region 130, spanning the two regions; the third N-type doping region 122 is provided with a second N-type heavily doped region 151; The first P-type heavily doped region 140 and the second N-type heavily doped region 151 are connected to the anode; the third P-type heavily doped region 142 and the first N-type heavily doped region 151 are connected to the cathode; Shallow trench isolation is provided between the second P-type heavily doped region 141 and the third P-type heavily doped region 142, between the third P-type heavily doped region 142 and the first N-type heavily doped region 150, and between the first N-type heavily doped region 150 and the fourth P-type heavily doped region 143. The first P-type doping region 130 is formed by longitudinally stacking one or more P-type doping regions with different doping doses, and the first N-type doping region 120, the second N-type doping region 121, and the third N-type doping region 122 are formed by longitudinally stacking one or more N-type doping regions with different doping doses.

[0035] The device has two parasitic PNP transistors, three parasitic NPN transistors, and three well resistors: The first parasitic PNP transistor Q p1 , including a first P-type heavily doped region 140, a second N-type doped region 121, a second P-type heavily doped region 141, a first P-type doped region 130, and a third P-type heavily doped region 142; the second parasitic PNP transistor Q p2 , including a first P-type heavily doped region 140, a second N-type doped region 121, and a first P-type doped region 130; the first parasitic NPN transistor Q n1 , including a second N-type heavily doped region 151, a third N-type doped region 122, a fourth P-type heavily doped region 143, a first P-type doped region 130, and a first N-type heavily doped region 150; the second parasitic lateral NPN transistor Q n2 , including a second N-type doping region 121, a first P-type doping region 130, and a first N-type heavily doped region 150; the third parasitic vertical NPN transistor Q n3 , including a first N-type doping region 120, a first P-type doping region 130, and a first N-type heavily doped region 150; the second well resistor R NW1, including a well resistance in the first N-type doping region 120 close to the third N-type doping region 122 and a well resistance in the third N-type doping region 122 with the first N-type heavily doped region 150 as a reference; the first well resistance R PW , including a first P-type well region 130 well resistor; the third well resistor R NW2 , including a well resistance in the first N-type doping region 120 close to the second N-type doping region 121 and a well resistance in the second N-type doping region 121 with the first N-type heavily doped region 150 as a reference.

[0036] The first parasitic PNP transistor Q p1 The first parasitic NPN transistor Q n1 The second parasitic PNP Q p2 transistor, a second parasitic lateral NPN transistor Q n2 , the third parasitic vertical NPN transistor Q n3 , the first well resistance R PW , the second well resistance R NW1 , the third well resistor R NW2 Together they form the SCR channel. Figure 3 The equivalent circuit is shown in the dashed box.

[0037] The working principle of the device described in Example 2 can be based on Q p1 and Q n1 BV CEO There are two types of sizes: When Q n1 BV CEO Greater than Q p1 , the ESD event reaches the anode of the device described in Example 2, when the ESD voltage is greater than Q p1 BV CEO When the electron current flows through Q p1 The emitter junction flows to the anode of the device described in Example 2, and the hole current flows to the cathode through the second P-type heavily doped region 141, the first P-type doped region 130, and the third P-type heavily doped region 142. At this time, as the anode voltage increases, Q p1 The emitter junction voltage increases, making Q p2 Turn on and conduct current. When the anode voltage increases to Q n1 BV CEO Later, with Q p1 and Q p2 The collector current increases, making R PW The pressure drop increases, so Q n1 Open, followed by Q n2 and Q n3 Q n2 and Q n3The collector current increases, at R NW1 and R NW2 The voltage drop across the p1 and Q p2 The emitter junction voltage increases, and positive feedback is formed between the parasitic NPN transistor and the parasitic PNP transistor. At this point, the SCR channel is turned on. At this time, there are two main ESD discharge channels, namely the SCR channel and the PNP channel. n1 It does not participate in the process of coupling to form positive feedback, so the NPN channel does not serve as the main ESD discharge channel.

[0038] When Q p1 BV CEO Greater than Q n1 , the ESD event reaches the anode of the device described in Example 2, when the ESD voltage is greater than Q n1 BV CEO When the electron current flows to the anode of the device described in Example 2 through the third N-type doped region 122 and the second N-type heavily doped region 151, the hole current flows to the anode of the device described in Example 2 through Q n1 The emitter junction flows to the cathode. At this time, as the anode voltage increases, the current flowing through Q n1 The current increases, R PW The voltage drop will increase, making Q n2 and Q n3 Turn on and conduct current. When the anode voltage increases to Q p1 BV CEO Later, with Q n2 , Q n3 The collector current increases, making R NW1 and R NW2 The pressure drop increases, so Q p1 and Q p2 will turn on, and Q p1 and Q p2 The emitter junction voltage will also increase, coupling between the parasitic NPN transistor and the parasitic PNP transistor to form a positive feedback, so that the SCR channel is turned on. At this time, there are two main ESD discharge channels, namely the SCR channel and the PNP channel. n1 It does not participate in the process of coupling to form positive feedback, so the NPN channel does not serve as the main ESD discharge channel.

[0039] BV CEO The size of can be obtained by the following formula: {BV}_{CEO}\approx \frac {{V}_{B}} {\sqrt[{S}] {β}} Where V Bis the PN junction avalanche breakdown voltage, β is the common emitter branch short-circuit current amplification factor, and S is a constant, which is generally 2~6 for silicon.

[0040] Q can be adjusted by adjusting the dosage of the first N-type doping region 120, the second N-type doping region 121, the third N-type doping region 122, and the first P-type doping region 130. p1 and Q n1 V B Q can be adjusted by adjusting the distance between the first P-type heavily doped region 140 and the second P-type heavily doped region 141 and the distance between the first N-type heavily doped region 150 and the junction of the fourth P-type heavily doped region 143 and the third N-type doped region 122. p1 and Q n1 The above method can be used to adjust Q p1 and Q n1 BV CEO , thereby achieving the purpose of regulating the trigger voltage, so that the trigger voltage of the device described in Example 2 is suitable for different ESD design windows.

[0041] The holding voltage of the device described in Example 2 is proportional to the ratio of the current through the PNP channel and the SCR channel. Increasing the current proportion of the PNP channel can effectively increase the holding voltage, and the control of the holding voltage can be achieved by adjusting the size of the well resistance, that is, mainly through the following methods: Regulate the dosage of the first N-type doping region 120, the second N-type doping region 121, the third N-type doping region 122, and the first P-type doping region 130; regulate the distance between the first P-type heavily doped region 140 and the second P-type heavily doped region 141; regulate the distance between the second N-type doping region 121 and the third P-type heavily doped region 142; regulate the distance between the third P-type heavily doped region 142 and the first N-type heavily doped region 150.

[0042] The above examples are only used to illustrate the technical solutions of the present invention and are not intended to limit the present invention. Although the present invention has been described with reference to preferred examples, those skilled in the art should understand that any feature disclosed in this specification, unless otherwise specified, may be replaced by other alternative features that are equivalent or have similar purposes. All disclosed features, or steps in all methods or processes, except for mutually exclusive features and / or steps, may be combined in any manner without departing from the purpose and scope of the technical solutions of the present invention, and should all be included in the scope of the claims of the present invention.

Claims

1. A multi-channel MLSCR with adjustable trigger voltage and holding voltage, characterized in that: The device comprises a P-type silicon substrate, a first N-type doping region is formed on the P-type silicon substrate; a second N-type doping region, a third N-type doping region, and a first P-type doping region are formed on the first N-type doping region; the first P-type doping region is completely surrounded by the first N-type doping region, the second N-type doping region, and the third N-type doping region; The second N-type doping region is provided with a first P-type heavily doped region; a second P-type heavily doped region is provided between the second N-type doping region and the first P-type doping region and spans the two regions; a third P-type heavily doped region and a first N-type heavily doped region are provided in the first P-type doping region in sequence from near to far with the second P-type heavily doped region as a reference; the third N-type doping region is provided with a second N-type heavily doped region; The first P-type heavily doped region and the second N-type heavily doped region are connected to the anode; the third P-type heavily doped region and the first N-type heavily doped region are connected to the cathode; Shallow trench isolation is provided between the second P-type heavily doped region and the third P-type heavily doped region, between the third P-type heavily doped region and the first N-type heavily doped region, and between the first N-type heavily doped region and the second N-type heavily doped region.

2. An MLSCR device optimized for the device described in claim 1, characterized in that: The device comprises a P-type silicon substrate, a first N-type doping region is formed on the P-type silicon substrate; a second N-type doping region, a third N-type doping region, and a first P-type doping region are formed on the first N-type doping region; the first P-type doping region is completely surrounded by the first N-type doping region, the second N-type doping region, and the third N-type doping region; The second N-type doping region is provided with a first P-type heavily doped region; a second P-type heavily doped region spanning the second N-type doping region and the first P-type doping region is provided between the two regions; a third P-type heavily doped region and a first N-type heavily doped region are provided in the first P-type doping region in order from near to far with the second P-type heavily doped region as a reference; a fourth P-type heavily doped region spanning the two regions is provided between the third N-type doping region and the first P-type doping region; the third N-type doping region is provided with a second N-type heavily doped region; The first P-type heavily doped region and the second N-type heavily doped region are connected to the anode; the third P-type heavily doped region and the first N-type heavily doped region are connected to the cathode; Shallow trench isolation is provided between the second P-type heavily doped region and the third P-type heavily doped region, between the third P-type heavily doped region and the first N-type heavily doped region, and between the first N-type heavily doped region and the fourth P-type heavily doped region.

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