Enhanced GaN-based HEMT (High Electron Mobility Transistor) power device with high-reliability grid-control performance and preparation method
By forming a periodic Fin island structure and a Tri-Gate gate structure in GaN-based enhanced power electronics, the problems of threshold instability and large leakage under high voltage are solved, high reliability and high voltage resistance are achieved, and the The industrialization process of GaN-based power electronic devices.
Patent Information
- Application Number
- CN202411321245.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-23
- Publication Date
- 2024-12-27
AI Technical Summary
The existing GaN-based enhanced power electronic devices have problems of threshold instability and large gate leakage under high voltage, which affects their reliability and industrialization.
By forming a periodic Fin island structure in the p-GaN gate region, and forming an ohmic contact and side wall on the top of the Fin island, a Tri-Gate gate structure is formed, and hole injection is suppressed by ohmic contact and lateral electric field, it is realized. High threshold stability and low leakage.
It significantly improves the threshold stability and gate withstand voltage of the device, increases the gate voltage swing, solves the leakage problem, improves the reliability and output current capability of the device, and promotes the industrialization of GaN-based power electronic devices.
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Figure CN119208369A_ABST
Abstract
Description
Technical Field
[0001] The invention relates to a semiconductor device, and in particular to the technical field of preparation of an Al(In, Ga)N / GaN heterostructure high electron mobility transistor. Background Art
[0002] GaN-based high electron mobility transistors (HEMTs) have excellent characteristics such as high output power density, high frequency and high voltage, high temperature resistance, and radiation resistance. They have great application potential in GaN-based power electronic devices and microwave devices. Enhancement mode is a key requirement for the safe operation of power electronic devices, that is, when working at high voltage, the device is safe even if it loses gate control and will not cause the system to burn out. This requires that power electronic devices must be enhanced-mode (also called normally-off). From a safety perspective, the device design has low gate leakage, large gate voltage swing, and strong gate reliability, which are the core requirements for long-term high-performance operation of power devices.
[0003] Based on the consideration of the safe operation of electronic power devices, the main way to prepare GaN-based enhancement-mode power electronic devices in the industry is the p-(Al)GaN gate enhancement technology. The p-GaN gate cap layer enhancement-mode HEMT device has good threshold uniformity and current output capability, and its monolithic structure makes it have the potential to work at a higher frequency, which has triggered extensive research. This technology forms a p-(Al)GaN gate on an undoped Al(In,Ga)N / GaN heterostructure, and uses the spatial depletion region of the pn junction under the gate to deplete the 2DEG to achieve enhancement. Commercial p-GaN enhancement-mode devices are mainly divided into ohmic contact type and Schottky contact type according to the different gate metals. Among them, the ohmic contact type has good dynamic resistance characteristics and switching characteristics. The main limitation is that it requires a pre-stage drive and the gate leakage current is large (the forward turn-on of the PN junction causes the gate forward leakage to increase). The Schottky type uses a low work function metal as the gate metal to form a reverse-biased Schottky diode with the gate metal and the p-GaN layer, which suppresses the gate leakage and achieves a higher gate voltage swing. However, due to the relatively floating potential of the p-GaN layer of the Schottky contact, there is a threshold instability problem under high drain voltage stress. In power switching applications, the drain voltage of the power transistor switches between high and low values. Drain bias stress has been found to have an adverse effect on the V th Drift exerts a more significant effect and is believed to be caused by hole deletion.
[0004] How to achieve p-GaN gate enhancement-mode GaN HEMT devices with small gate leakage, large gate voltage swing, and high threshold stability, and further improve reliability to enterprise-level applications, is the next step to effectively improve the process repeatability and yield of GaN-based enhancement-mode devices and an important means to promote the industrialization of GaN-based power electronic devices. Summary of the invention
[0005] In view of this, the main purpose of the present invention is to provide a p-GaN gate-enhanced HEMT power device structure and a preparation method with high reliability gate control performance, so as to simultaneously achieve the functions of high threshold stability and large gate voltage swing.
[0006] The present invention etches the p-GaN layer in the gate region periodically to form a Fin island structure along the gate width direction, i.e., the vertical channel direction, and etches to a depth exceeding the GaN buffer layer. Then, dielectric deposition is performed, and then a hole is opened on the top of the p-GaN Fin island. Then, after depositing a gate metal, an ohmic contact is formed on the top of the Fin island and a MIS structure (Tri-Gate) gate structure is formed on the sidewall, which is called p-GaN ohmic-MIS Tri-Gate. When the gate voltage is low, the top of such a composite Tri-Gate structure can realize hole injection with an ohmic contact, which can solve the potential floating problem and suppress the threshold drift problem caused by high voltage stress on the drain. When the gate voltage is high, the electric field of the lateral MIS can form an inversion on the side wall of the p-GaN Fin island, obtain a layer of electrons, and form an npn-like super junction structure, which can realize lateral electric field expansion and deplete the hole concentration in the p-GaN layer to achieve depletion or even inversion. The high gate leakage caused by hole injection in the longitudinal ohmic contact part is reduced by lateral electric field expansion, so as to realize a high reliability gate and high withstand voltage of the gate structure.
[0007] Specifically, the enhanced GaN-based HEMT power device provided by the present invention includes a substrate and a p-GaN / Al(In,Ga)N / GaN heterostructure thereon, wherein the Al(In,Ga)N / GaN heterojunction gate p-GaN region forms a Tri-Gate structure, the p-GaN Fin island in the Tri-Gate structure is a periodically parallel arranged narrow strip structure, the length direction of the narrow strip structure is parallel to the channel direction, and the periodic arrangement direction of the narrow strip structure is perpendicular to the channel direction, a gate dielectric is deposited on the side wall portion of the p-GaNFin island in the Tri-Gate gate structure to form an MIS structure, and the top directly contacts the gate metal to form an ohmic contact; the source and drain are respectively located at both ends of the channel.
[0008] In the above-mentioned enhanced GaN-based HEMT power device, the length of the p-GaN Fin island in the gate length direction (same as the channel direction) is 1 to 4 μm, the width of the p-GaN Fin island periodic narrow strip structure in the Tri-Gate gate structure in the gate width direction (perpendicular to the channel direction) is 50 to 500 nm, and the Fin island spacing is 50 to 500 nm.
[0009] The ohmic contact portion on the top of the gate p-GaN Fin island can be formed into an ohmic contact by annealing, or can be formed into an ohmic contact by heavy doping of the p-GaN surface and contacting with metal by ion implantation.
[0010] The sidewall of the gate p-GaN Fin island is partially in MIS contact, and the gate dielectric layer can be SiN, SiO2, AlON, AlSiO, AlSiN or SiON, and the thickness is preferably 5 to 30 nm.
[0011] The gate metal is Ni / Au, Ni / Ag or other metals.
[0012] The Al(In,Ga)N / GaN heterojunction is composed of a GaN buffer layer and an Al(In,Ga)N barrier layer sequentially stacked on a substrate, wherein the Al(In,Ga)N can be AlN, AlGaN, AlInN, InGaN or AlInGaN.
[0013] The present invention also provides a method for preparing the above-mentioned enhanced GaN-based HEMT power device, comprising the following steps:
[0014] 1) depositing a GaN buffer layer, an Al(In,Ga)N barrier layer and a p-GaN layer on a substrate in sequence to form a p-GaN / Al(In,Ga)N / GaN heterostructure;
[0015] 2) Etching the p-GaN layer outside the gate region and self-stopping at the Al(In,Ga)N barrier layer;
[0016] 3) preparing ohmic contact electrodes as source and drain electrodes at both ends of the channel region and on the Al(In,Ga)N barrier layer;
[0017] 4) Perform isolation operations on the device;
[0018] 5) Etching the p-GaN layer and the Al(In,Ga)N barrier layer in the gate region along the gate width direction to 30 to 100 nm of the GaN buffer layer to obtain a periodic Fin island structure;
[0019] 6) depositing gate dielectric to cover the gate region and the channel region;
[0020] 7) Etching and removing the gate dielectric on the top of the Fin island structure;
[0021] 8) Depositing gate metal to cover the gate area;
[0022] 9) Annealing the gate metal to form a p-GaN gate ohmic contact to obtain the p-GaN ohmic-MISTri-Gate enhanced GaN-based HEMT power device.
[0023] The present invention etches the gate region in the gate width direction perpendicular to the channel direction to form a periodic Fin island structure. The top of the Fin island directly contacts the gate metal to form an ohmic contact. When the gate is in a voltage-applied working state, hole injection can be achieved, so that the potential of the p-GaN layer of the gate Fin island is in a non-floating state, which can effectively avoid the problem of gate threshold drift and simultaneously realize the conductivity modulation GIT effect. The side wall of the Fin island forms an MIS structure by depositing an insulating medium and a metal. The gate metal of the side wall of the Fin island and the top gate metal are the same metal and have the same potential. When the gate voltage is small, the p-GaN region is not affected. The gate ohmic contact plays a major role. When the gate voltage increases, the lateral MIS structure causes the side wall of the Fin island to form depletion or even inversion. The lateral electric field can shield the longitudinal electric field to form an npn-like super junction structure, which can effectively increase the gate withstand voltage and prevent hot electrons from flowing through the gate p-GaN region to bombard the top region. At the same time, a high gate withstand voltage is achieved and the problem of gate reliability threshold drift is effectively solved, thereby successfully providing an effective method for preparing high-performance enhanced devices.
[0024] In the above step 1), the thickness of the Al(In,Ga)N barrier layer is between 15 and 30 nm to ensure a high 2DEG concentration. It can be an AlN binary alloy layer, or an AlGaN, AlInN or InGaN ternary alloy layer, or an AlInGaN quaternary alloy layer.
[0025] In the above step 1), the thickness of the p-GaN layer is between 80 and 200 nm, and the hole doping concentration is between 1e17 and 1e20.
[0026] In the above step 2), the width of the p-GaN layer in the gate region in the gate length direction (channel direction) after etching is more than 1 μm, and the etching of the p-GaN layer is self-stopped at the surface of the Al(In,Ga)N barrier layer by Cl-based plasma etching to ensure the uniformity of the enhancement threshold.
[0027] In the above step 3), the ohmic contact electrode is prepared by a lift-off process and an alloying process at 700 to 900° C. (in the case of Au) or an alloying process at 300 to 600° C. (in the case of Au-free).
[0028] In the above step 4), the device isolation adopts table isolation or injection isolation.
[0029] In the above step 5), the p-GaN layer in the gate region to the GaN channel layer is etched by electron beam lithography to form a periodic Fin island structure, and the width of the Fin island is between 50 and 300 nm.
[0030] In the above step 6), the deposited gate dielectric can be SiN, SiO2, AlON, AlSiO, AlSiN or SiON, grown by atomic layer deposition (ALD), chemical vapor deposition (CVD) or molecular beam epitaxy (MBE) technology, with a growth temperature of 500-1000°C and a thickness between 5 and 30 nanometers.
[0031] In the above step 8), the gate P-type ohmic contact metal includes any one of Ti, Al, Ni, Au or a combination of two or more thereof, preferably Ni / Au, Ti / Au or other P-type ohmic contact metals.
[0032] Based on the above technical solution, it can be seen that the enhanced gallium nitride-based HEMT device and the manufacturing method thereof of the present invention have the following advantages over the prior art:
[0033] 1. The gallium nitride-based electronic device provided by the present invention structures the gate p-GaN region, forms a periodic Fin island structure by etching p-GaN in a direction perpendicular to the current direction, and prepares a p-GaN ohmic contact gate contact on the top of the Fin island. The ohmic contact can achieve barrier-free conduction between the gate metal and the electron holes in the p-GaN region, so that its potential does not float, which can solve the problem of threshold drift of the current commercial p-GaN Schottky gate contact and significantly improve the stability of the device gate threshold.
[0034] 2. The gallium nitride-based electronic device provided by the present invention structures the gate p-GaN region, forms a periodic Fin island structure by etching p-GaN in a direction perpendicular to the current direction, and deposits a gate dielectric on the sidewall of the Fin island to form an MIS structure. Through lateral gate voltage regulation, when the gate voltage is small, the sidewall voltage has no effect, while when the gate voltage is large, the high voltage on the sidewall causes the p-GaN sidewall to form depletion or even inversion. At this time, an npn-like superjunction structure is formed in the gate width direction of the p-GaN layer, which effectively solves the problem of large gate leakage, achieves the ability to improve the gate voltage resistance, increases the gate voltage swing, solves the problem of drive design limitations, and can inhibit hot electrons injected into the gate from bombarding the gate metal and p-GaN contact interface, significantly improving the gate voltage resistance and reliability.
[0035] 3. The gallium nitride-based electronic device provided by the present invention adopts a top p-GaN ohmic contact, which can realize GIT conductivity modulation, effectively improve the output current capability of GaN-based enhancement mode devices, increase output power, and promote the industrialization process of GaN-based power electronic devices. BRIEF DESCRIPTION OF THE DRAWINGS
[0036] For a more complete understanding of the present invention and its advantages, please refer to the following description in conjunction with the accompanying drawings. The device structures in the accompanying drawings are not necessarily shown to scale, but the emphasis is placed on clearly illustrating the principles of the present invention.
[0037] Figure 1 It is a schematic diagram of the structure of an enhanced gallium nitride-based electronic device manufactured according to an embodiment of the present invention, the left side is a cross-sectional view of the device in the gate length direction (channel direction), and the right side is a cross-sectional view of the device in the gate width direction (perpendicular to the channel direction).
[0038] Figure 2 It is a schematic diagram of the device structure in the process flow of manufacturing an enhancement-mode gallium nitride-based electronic device according to an embodiment of the present invention. The left figure is a cross-sectional view of the device in the gate length direction (channel direction) of each process step, and the right figure is a cross-sectional view of the gate region in the gate width direction (perpendicular to the channel direction) of each process step.
[0039] Description of reference numerals:
[0040] 1-substrate; 2-GaN buffer layer; 3-Al(In,Ga)N barrier layer; 4-p-GaN layer; 5-ohmic contact electrode; 6-gate dielectric layer; 7-gate metal. DETAILED DESCRIPTION
[0041] Hereinafter, the present invention will be described in detail by way of examples with reference to the accompanying drawings to assist members of the art to fully understand the purpose, features and effects of the present invention. The accompanying drawings show exemplary embodiments of the present invention, but it should be understood that the present invention can also be implemented in various other forms and should not be limited by the embodiments described herein. In addition, in the following description, descriptions of known structures and technologies are omitted to avoid unnecessary confusion of the concept of the present invention. In addition, the various embodiments of the present invention provided below and the technical features in the embodiments can be combined with each other in any manner.
[0042] The terms used herein are only for describing specific embodiments and are not intended to limit the present invention. In addition, the terms "including", "comprising", "having", etc. used herein indicate the presence of the features, steps, operations and / or components, but do not exclude the presence or addition of one or more other features, steps, operations or components. All terms (including technical and scientific terms) used herein have the meanings commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein should be interpreted as having meanings consistent with the context of this specification and should not be interpreted in an idealized or overly rigid manner.
[0043] Figure 1 1 is a schematic diagram of the structure of an enhanced gallium nitride-based electronic device prepared in this embodiment, comprising a substrate, a GaN buffer layer 2, an Al(In,Ga)N barrier layer 3, and a p-GaN layer 4 are sequentially stacked on the substrate 1, a Tri-Gate structure is formed in the gate p-GaN region, the p-GaN Fin island in the Tri-Gate structure is a periodically parallel narrow strip structure, and the periodic arrangement direction of the narrow strips is perpendicular to the channel direction, a gate dielectric is deposited on the side wall portion of the p-GaN Fin island in the Tri-Gate gate structure to form an MIS structure, and the top directly contacts the gate metal to form an ohmic contact; the source and drain are respectively located at both ends of the channel.
[0044] Combine the following Figure 2 The method for manufacturing an enhanced gallium nitride-based electronic device proposed in this embodiment is described in detail to better understand the technical solution of the present invention and the beneficial effects achieved. The manufacturing method includes:
[0045] Step 1: Provide a substrate 1.
[0046] Step 2: growing a p-GaN / Al(In,Ga)N / GaN heterostructure on a substrate 1, including a GaN buffer layer 2 (thickness 2-6 μm), an Al(In,Ga)N barrier layer 3 (thickness 15-30 nm) and a p-GaN layer 4 (thickness 80-200 nm) sequentially deposited on the substrate 1, such as Figure 2 As shown in Figure a.
[0047] Step 3: Etch the p-GaN layer 4 outside the gate region and stop at the Al(In,Ga)N barrier layer 3, as shown in FIG. Figure 2 As shown in Figure b;
[0048] The length of the p-GaN gate region (i.e., gate length) is above 1 μm, and the etching of the p-GaN layer 4 is automatically stopped by the Cl-based plasma etching at the surface of the Al(In,Ga)N barrier layer 3 to ensure the uniformity of the enhancement threshold.
[0049] Step 4: Prepare ohmic contact electrodes 5 as source and drain electrodes on the Al(In,Ga)N barrier layer 3 at both ends of the channel region. Figure 2 As shown in Figure c;
[0050] This step can be done by either gold-containing ohmic contact or gold-free ohmic contact. The Au-containing ohmic contact layer is prepared by a lift-off process and an alloying process at a temperature of 700°C to 900°C; the Au-free ohmic contact layer is prepared by a lift-off process and an alloying process at a temperature of 300°C to 700°C.
[0051] Step 5: Isolate the device obtained in step 4, wherein the isolation is performed by mesa isolation or injection isolation.
[0052] Step 6: Etch the p-GaN layer 4 along the gate width direction in the gate region to obtain a periodic Fin island structure, and etch to a depth of 30-100nm of the GaN buffer layer 2, such as Figure 2 As shown in Figure d;
[0053] Among them, the p-GaN layer in the gate area, the Al(In,Ga)N barrier layer and part of the GaN buffer layer are etched by electron beam lithography to form a periodic Fin island structure, with a Fin island width of 50 to 300 nm and a Fin island spacing of 50 to 500 nm.
[0054] Step 7: Deposit a gate dielectric layer 6, such as Figure 2 As shown in Figure e;
[0055] The gate dielectric layer 6 may be SiN, SiO2, AlON, AlSiO, AlSiN or SiON, grown by ALD, CVD or molecular beam epitaxy (MBE) technology, with a growth temperature of 500-1000° C. and a thickness of 5 to 30 nanometers.
[0056] Step 8: Etch and remove the gate dielectric on the top of the Fin island, such as Figure 2 As shown in Figure f.
[0057] Step 9: Deposit gate metal 7 to obtain Figure 2 The structure shown in Figure g;
[0058] The gate metal 7 may be any one of Ti, Al, Ni, and Au, or a combination of two or more thereof, and is preferably a P-type ohmic contact metal such as Ni / Au or Ti / Au.
[0059] Step 10: Annealing the gate metal 7 to form a p-GaN gate ohmic contact, thus completing the manufacturing of the p-GaN ohmic-MIS Tri-Gate enhanced GaN-based electronic device.
Claims
1. An enhanced GaN-based HEMT power device, comprising a substrate and a GaN buffer layer, an Al(In,Ga)N barrier layer and a p-GaN layer stacked in sequence on the substrate, characterized in that: A Tri-Gate gate structure is formed in the gate region, including periodically arranged narrow strip p-GaN Fin islands, whose length direction is parallel to the channel direction and whose periodic arrangement direction is perpendicular to the channel direction; in the Tri-Gate gate structure, a gate dielectric is deposited on the sidewall of the p-GaN Fin island to form an MIS structure, and the top directly contacts the gate metal to form an ohmic contact; the source and drain are respectively located at both ends of the channel.
2. The enhanced-mode GaN-based HEMT power device according to claim 1, characterized in that: The length of the p-GaN Fin island is 1-4 μm, the width is 50-500 nm, and the distance between the Fin islands is 50-500 nm.
3. The enhanced-mode GaN-based HEMT power device according to claim 1, characterized in that: The gate dielectric is SiN, SiO2, AlON, AlSiO, AlSiN or SiON, and has a deposition thickness of 5 to 30 nm.
4. The enhanced-mode GaN-based HEMT power device according to claim 1, characterized in that: The Al(In,Ga)N barrier layer is AlN, AlGaN, AlInN, InGaN or AlInGaN, and has a thickness of 15-30 nm.
5. The enhancement mode GaN-based HEMT power device according to claim 1, characterized in that: The thickness of the p-GaN layer is 80-200 nm, and the hole doping concentration is between 1e17 and 1e20.
6. The method for preparing the enhanced-mode GaN-based HEMT power device according to any one of claims 1 to 5, comprising the following steps: 1) depositing a GaN buffer layer, an Al(In,Ga)N barrier layer and a p-GaN layer on a substrate in sequence; 2) Etching the p-GaN layer outside the gate region and self-stopping at the Al(In,Ga)N barrier layer; 3) preparing ohmic contact electrodes as source and drain electrodes at both ends of the channel region and on the Al(In,Ga)N barrier layer; 4) Perform isolation operations on the device; 5) Etching the p-GaN layer and the Al(In,Ga)N barrier layer in the gate region along the gate width direction to 30 to 100 nm of the GaN buffer layer to obtain a periodic Fin island structure; 6) depositing gate dielectric to cover the gate region and the channel region; 7) Etching and removing the gate dielectric on the top of the Fin island structure; 8) Depositing gate metal to cover the gate area; 9) Annealing the gate metal to form a p-GaN gate ohmic contact to obtain the device.
7. The preparation method according to claim 6, characterized in that: Step 3) using a stripping process and an alloying process to make an ohmic contact electrode; Step 4) using a mesa isolation or an injection isolation method to achieve device isolation.
8. The preparation method according to claim 6, characterized in that: Step 5) Etching is performed using electron beam lithography.
9. The preparation method according to claim 6, characterized in that: Step 6) growing the gate dielectric by atomic layer deposition, chemical vapor deposition or molecular beam epitaxy.
10. The preparation method according to claim 6, characterized in that: In step 8), the gate metal is selected from any one of Ti, Al, Ni, and Au, or a combination of two or more thereof.