Interlayer ferroelectric transistor with 25 polarization state and preparation method thereof

Abstract

The invention discloses an interlayer ferroelectric transistor with a 25 polarization state and a preparation method of the interlayer ferroelectric transistor, and belongs to the field of ferroelectric functional devices.The interlayer ferroelectric transistor is prepared based on a graphene / hexagonal boron nitride (Gr / hBN) heterostructure, a heterojunction Gr / hBN is arranged on a SiO2 / Si substrate, the bottom layer is an hBN sheet, the top layer is a single-layer Gr, and the rotation angle between the Gr and the hBN is controlled within 1 degree through dry transfer; further preparing a Gr / hBN interlayer ferroelectric transistor through electron beam exposure and electron beam evaporation processes; more than 25 stable polarization states can be realized at room temperature, and the method can be further used as an artificial nerve synapse to be applied to neuromorphic calculation and shows excellent calculation accuracy.

Description

Technical Field

[0001] The present invention relates to the technical field of transistor manufacturing and preparation, and in particular to an interlayer ferroelectric transistor with 25 polarization states and a preparation method thereof. Background Art

[0002] The emergence of artificial intelligence and machine learning has prompted neuromorphic computing to overcome the memory wall bottleneck in the von Neumann framework. In this context, ferroelectric materials, which can generate multiple electrically addressable polarization states, have developed into strong candidate materials for neuromorphic hardware. The number of polarization states significantly determines the computational accuracy and storage density of neuromorphic hardware. In traditional three-dimensional oxide ferroelectrics, early attempts were made to tune the dipole states and nucleation energy by introducing lattice defects, heterointerfaces, or phase transitions. However, when three-dimensional ferroelectrics are used for device integration in the form of thin films, the count of discrete polarization states is reduced to less than four. In contrast, emerging van der Waals ferroelectrics can exhibit quadruple / sextuary polarization states through special ion migration mechanisms. Although there have been extensive efforts to create stable multi-state polarization in existing ferroelectric materials, the number of stable polarization states at room temperature is still less than 16 (<4-bit) due to the limited adjustable degrees of freedom. In addition, the high thickness and complex stacking structure of existing ferroelectric devices further restrict the miniaturization and high-density integration of devices. In view of the shortcomings of the prior art, the present invention designs and prepares a simple structure interlayer ferroelectric transistor with 25 polarization states. Summary of the invention

[0003] Technical problems to be solved: In view of the technical problems that the adjustable degrees of freedom in the prior art are limited, the number of stable polarization states at room temperature is still less than 16, and the high thickness and complex stacking structure of existing ferroelectric devices further limit the miniaturization and high-density integration of the devices. The present invention provides an interlayer ferroelectric transistor with 25 polarization states and a preparation method thereof. Based on the Gr / hBN heterostructure, a ferroelectric transistor with a simple stacking structure that can generate more than 25 polarization states at room temperature is prepared, laying the foundation for the development of high-density non-volatile storage and high-precision storage and computing systems.

[0004] Technical solution:

[0005] A method for preparing an interlayer ferroelectric transistor with 25 polarization states specifically comprises the following steps:

[0006] S1, 2D material preparation: peeling off single-layer Gr and hBN flakes respectively;

[0007] S2: Cut the PDMS and place it on a clean glass slide, and use oxygen plasma for surface treatment; spin-coat the PPC reagent on the PDMS surface, then place it on a hot plate and heat it at 105°C for 3 minutes, and use oxygen plasma to treat the surface of the PDMS that has been spin-coated with PPC;

[0008] S3: Take two clean glass slides, add 3 ml of PC reagent on one of them, and then immediately cover it with another glass slide, then slowly pull the two glass slides apart to form a layer of PC film, cut a square hole in the middle of the 3M white tape, the area of ​​the square hole should be slightly larger than the surface-treated PDMS in S2, and then use it to stick the PC film to cover the surface-treated PDMS in S2, to prepare a PC / PPC / PDMS dry transfer carrier;

[0009] S4: Cover the PC / PPC / PDMS dry transfer carrier on the single-layer Gr obtained in S1 at 90°C, then slowly lift the PC / PPC / PDMS dry transfer carrier, stick the single-layer Gr, and mark its position on the PC / PPC / PDMS dry transfer carrier; then align the straight edge of the single-layer Gr on the PC / PPC / PDMS dry transfer carrier with the straight edge of the hBN thin film on the silicon wafer and cover it, heat it to 180°C after covering and keep it for 2 minutes, and finally slowly lift the carrier, and the PPC / PC film will be thermally released on the silicon wafer; clean PPC and PC to complete the construction of the Gr / hBN heterojunction;

[0010] S5: Spin-coat PMMA at a speed of 4000 r / s for 1 min on the surface of the silicon wafer where the Gr / hBN heterojunction is located, and then heat it at 170°C for 2 min; spin-coat PMMA at a speed of 4000 r / s for 1 min again, and then place it on a hot plate and heat it at 180°C for 5 min; use a field emission electron microscope and an electron beam exposure system to complete the exposure of the electrode, and then place the silicon wafer in a developer solution of isopropanol: water = 3:1 to complete the development for 30 seconds; use an electron beam deposition device to evaporate 5nm Ti / 60nm Au on the surface of the silicon wafer; soak the silicon wafer in acetone reagent, place it on a hot plate and heat it at 65°C to make the PMMA-carrying metal thin layer in the unexposed area fall off; soak the silicon wafer in isopropanol reagent for cleaning for 5 minutes, and then blow dry it with nitrogen to obtain a Gr / hBN ferroelectric transistor, that is, an interlayer ferroelectric transistor with a polarization state of 25.

[0011] Furthermore, the specific steps of S1 are:

[0012] S101, pre-cleaning the silicon wafer using an oxygen plasma system at 50W / 50sccm / 2min;

[0013] S102, using blue tape to stick 4 to 5 square millimeter two-dimensional material crystals respectively, and aligning the tapes so that the crystals are evenly distributed in an area of ​​1 square centimeter on the tapes, and then covering the silicon wafer;

[0014] S103, placing the silicon wafer covered by the blue tape on a hot plate and heating it at 100°C for 1 min, slowly peeling off the blue tape after cooling to complete mechanical peeling, and mechanical peeling is performed to obtain single-layer Gr and hBN thin sheets respectively.

[0015] Furthermore, the specific steps of S2 are:

[0016] S201, cut a small piece of PDMS and place it on a clean glass slide, and treat its surface with oxygen plasma under the conditions of 30W / 20sccm / 30s;

[0017] S202, turning over the PDMS, and treating the surface again with oxygen plasma at 50W / 50sccm / 2min;

[0018] S203, using a spin coater to spin coat the PPC reagent on the PDMS surface at a rotation speed of 4000 r / s for 1 min, then placing it on a hot plate and heating it at 105° C. for 3 min, and treating the PDMS spin-coated with PPC with oxygen plasma under the condition of 20 W / 10 sccm / 3 s.

[0019] Furthermore, the mass fraction of the PPC reagent in S203 is 15% by mass, and the solvent is anisole.

[0020] Furthermore, the mass fraction of the PC reagent in S3 is 5%, and the solvent is dichloromethane.

[0021] Furthermore, the process of cleaning PPC and PC in S4 is: cleaning the silicon wafer in dichloromethane for 20 minutes, cleaning in acetone for 15 minutes, and cleaning in isopropanol for 5 minutes.

[0022] An interlayer ferroelectric transistor with a polarization state of 25 prepared by any of the above preparation methods, wherein the heterojunction Gr / hBN is placed on a SiO2 / Si substrate, the bottom layer is a hBN thin sheet, the top layer is a single layer of Gr, and 5nm Ti / 60nm Au electrodes are constructed as source and drain electrodes by electron beam exposure and electron beam evaporation.

[0023] Furthermore, the thicknesses of the single-layer Gr and hBN sheets are 0.34 nm and 20 nm, respectively.

[0024] Principle explanation: Gr and hBN have similar hexagonal honeycomb lattices. It is predicted that the Gr / hBN heterojunction should exhibit upward and downward interlayer polarizations in the AB and BA stacking configurations, respectively. In principle, the interlayer polarization reversal can be achieved by sliding the upper Gr layer by a BN bond length within one moiré period, resulting in sliding ferroelectricity. In the present invention, the ferroelectric polarization intensity is regulated by applying source-drain DC pulses to the Gr channel.

[0025] Beneficial effects:

[0026] (1) This application proposes for the first time an interlayer ferroelectric transistor with 25 polarization states and a method for preparing the same. At room temperature, by changing the bias pulse between the source and drain electrodes, the ferroelectric transistor exhibits at least 25 stable and discrete polarization states;

[0027] (2) Using the different current levels corresponding to multi-state polarization as weights, the constructed convolutional neural network can achieve a recognition accuracy of 98.4% for MNIST handwritten digits;

[0028] (3) In addition, the device has a simple stacking structure and working mode, which lays the foundation for the development of high-performance nanoscale storage and computing systems. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 Schematic diagram of the structure and working mode of the Gr / hBN interlayer ferroelectric transistor in the embodiment of the present application;

[0030] Figure 2 The Raman spectrum characterization and optical image of the Gr / hBN interlayer ferroelectric transistor in the embodiment of the present application, wherein the left image is the Raman spectrum characterization image, and the right image is the optical image;

[0031] Figure 3 This is an electrical characterization diagram of the slip ferroelectricity of the Gr / hBN interlayer ferroelectric transistor in the embodiment of the present application; Figure 3 The upper left figure shows the channel resistance of the device measured at 1.5K as the pulse amplitude (V pulse ) and gate voltage (V G ) function; Figure 3 Lower left picture and Figure 3 Same as the upper left picture, but V pulse The direction of application is reversed; Figure 3 The middle right picture shows V extracted from the two pictures on the left. pulse =RV at -9 / -6 / +0.5 / +6 / +9V G curve;

[0032] Figure 4 Characterization of the slip ferroelectric hysteresis window of the Gr / hBN interlayer ferroelectric transistor in the embodiment of the present application;

[0033] Figure 5 is a graph showing the polarization intensity of the Gr / hBN interlayer ferroelectric transistor as a function of the pulse bias voltage in an embodiment of the present application;

[0034] Figure 6The cyclic enhancement and suppression of the current level of the Gr / hBN interlayer ferroelectric transistor in the embodiment of the present application under the action of increasing positive and negative bias voltages and the cumulative frequency diagram of different current levels, wherein the upper figure is a cyclic enhancement and suppression diagram, and the lower figure is a cumulative frequency diagram of different current levels;

[0035] Figure 7 This is a 4-bit working mode demonstration diagram of the Gr / hBN interlayer ferroelectric transistor in the embodiment of the present application;

[0036] Figure 8 This is a convolutional neural network flow chart and the corresponding handwritten digit recognition accuracy rate used in the Gr / hBN interlayer ferroelectric transistor in the embodiment of the present application, where the upper figure is a convolutional neural network flow chart and the lower figure is a handwritten digit recognition accuracy rate chart. DETAILED DESCRIPTION

[0037] The present invention is described in detail below with reference to the accompanying drawings and specific embodiments.

[0038] The following reagents and instruments are required:

[0039] Graphite crystal (HQ graphene); hBN crystal (HQ graphene);

[0040] Silicon wafer (University, 300nm SiO2 / Si); Blue tape for mechanical stripping (ultronsystems); White tape (3M);

[0041] PDMS (DOW CORNING 184); PC (Sigma-Aldrich); PPC (Sigma-Aldrich); PMMA (MicroChem 495A4);

[0042] Dichloromethane (B&K, pesticide grade 99.9%); anisole (alladin, chromatography grade 99.9%); acetone (Vokay, chromatography grade 99.9%); isopropyl alcohol (Tedia, chromatography grade 99.9%);

[0043] Two-dimensional material transfer station (Meita Optoelectronics), electron beam deposition equipment (Syskey E-Beam Evaporationsystem), oxygen plasma system (Femto Scince Convance), spin coater (Spin Processor POLOS), optical microscope (Nikon LV100ND), field emission electron microscope (Zeiss Sigma 300), electron beam exposure system (RaithQuantum), atomic force microscope (SmartSPM-1000), Raman spectrometer (Horiba JYLabram EVO, 532nm), low-temperature transport equipment (OXFORD TeslatronPT), source meter (Keithley 2400 / Keithley 6430).

[0044] Example 1

[0045] This embodiment provides a method for preparing a single-layer interlayer ferroelectric transistor with 25 polarization states, comprising the following steps:

[0046] S1, preparation of two-dimensional materials: pre-clean silicon wafers using an oxygen plasma system at 50W / 50sccm / 2min; use blue tape to stick two-dimensional material crystals of 4 to 5 square millimeters, and stick the tape so that the crystals are evenly distributed in an area of ​​1 square centimeter on the tape, and then cover the silicon wafer; place the silicon wafer covered with blue tape on a hot plate and heat it at 100°C for 1 minute, and after cooling, slowly peel off the blue tape to complete mechanical peeling, and mechanically peel off to obtain single-layer Gr and hBN thin films; use an optical microscope to confirm the positions of single-layer Gr and hBN thin layers on the silicon wafer by the difference in optical contrast; use an atomic force microscope to confirm the thickness and surface cleanliness of the two-dimensional materials at the corresponding positions;

[0047] S2: Cut a small piece of PDMS and place it on a clean glass slide, and treat its surface with oxygen plasma at 30W / 20sccm / 30s; turn the PDMS over and treat the surface again with oxygen plasma at 50W / 50sccm / 2min; use a spin coater to spin coat the PPC reagent on the PDMS surface at 4000r / s for 1min, then place it on a hot plate and heat it at 105℃ for 3min, and treat the PDMS with PPC spin-coated with oxygen plasma at 20W / 10sccm / 3s;

[0048] S3: Take two clean glass slides, add 3 ml of PC reagent on one of them, and then immediately cover it with another glass slide, then slowly pull the two glass slides apart to form a layer of PC film, cut a square hole in the middle of the 3M white tape, the area of ​​the square hole should be slightly larger than the surface-treated PDMS in S2, and then use it to stick the PC film to cover the surface-treated PDMS in S2 to prepare a PC / PPC / PDMS dry transfer carrier;

[0049] S4: Cover the PC / PPC / PDMS dry transfer carrier on the single-layer Gr obtained in S1 at 90°C, then slowly lift the PC / PPC / PDMS dry transfer carrier, stick the single-layer Gr, and mark its position on the PC / PPC / PDMS dry transfer carrier; then align the straight edge of the single-layer Gr on the PC / PPC / PDMS dry transfer carrier with the straight edge of the hBN thin film on the silicon wafer and cover it, heat it to 180°C after covering and keep it for 2 minutes, and finally slowly lift the carrier, and the PPC / PC film will be thermally released on the silicon wafer; clean PPC and PC to complete the construction of the Gr / hBN heterojunction;

[0050] S5: Spin-coat PMMA at a speed of 4000 r / s for 1 min on the surface of the silicon wafer where the Gr / hBN heterojunction is located, and then heat it at 170°C for 2 min; spin-coat PMMA at a speed of 4000 r / s for 1 min again, and then place it on a hot plate and heat it at 180°C for 5 min; use a field emission electron microscope and an electron beam exposure system to complete the exposure of the electrode, and then place the silicon wafer in a developer solution of isopropanol: water = 3:1 to complete the development for 30 seconds; use an electron beam deposition device to evaporate 5nm Ti / 60nm Au on the surface of the silicon wafer; soak the silicon wafer in acetone reagent, place it on a hot plate and heat it at 65°C to make the PMMA-carrying metal thin layer in the unexposed area fall off; soak the silicon wafer in isopropanol reagent for cleaning for 5 minutes, and then blow dry it with nitrogen to obtain a Gr / hBN ferroelectric transistor, that is, an interlayer ferroelectric transistor with a polarization state of 25.

[0051] The mass fraction of the PPC reagent in S203 is 15% by mass, and the solvent is anisole.

[0052] The mass fraction of the PC reagent in S3 is 5%, and the solvent is dichloromethane.

[0053] The interlayer ferroelectric transistor with 25 polarization states prepared by the preparation method has a heterojunction Gr / hBN placed on a SiO2 / Si substrate, a bottom layer of hBN thin slices, and a top layer of single-layer Gr. 5nmTi / 60nm Au electrodes are constructed as source and drain electrodes by electron beam exposure and electron beam evaporation. The thicknesses of the single-layer Gr and hBN thin slices are 0.34nm and 20nm, respectively.

[0054] Source-drain bias pulse control and electrical transport test of Gr / hBN ferroelectric transistors: Based on the sample holder of the low-temperature transport equipment, the device leads are completed; the sample is placed in the chamber and evacuated to 1×10 -6 torr, and the chamber temperature was lowered to 1.5K. In order to achieve the regulation of multi-state polarization, a source-drain bias pulse (V pulse ) at the gate voltage (V G ) is zero. The change in polarization direction and intensity causes a difference in carrier concentration inside Gr, so the change in the polarization state of the system can be detected by the offset of the Dirac point. After each pulse, by executing V G Scan and record the transmission characteristics of the device, such as Figure 3 As shown. Apply 0.5V steps from V pulse = = +10V to -10V pulse, it can be observed that all Dirac points gradually shift towards the hole doping direction, and vice versa, they shift reversibly towards the electron doping direction. Extract V in the forward and reverse evolution of the pulse respectively pulse =Transfer curves under +9 / +6 / +0.5 / -6 / -9V conditions. It can be observed that the offset of DPs increases first and then decreases as the pulse decreases monotonically, thus showing the physical image of ferroelectric hysteresis, such as Figure 3 As shown in the middle right figure. The concrete ferroelectric hysteresis image can be obtained by subtracting the forward mapping and the reverse mapping, as shown in Figure 4 As shown in the figure, the three significant memory windows correspond to the main Dirac point (PDP) and two secondary Dirac points (SDP). The corresponding interlayer polarization values ​​can be calculated by the two-dimensional polarization model, and the hysteresis loops corresponding to the three Dirac points can be extracted respectively, as shown in Figure 5 shown.

[0055] Multi-state polarization control and application of Gr / hBN ferroelectric transistors: The slip ferroelectricity in Gr / hBN devices can be extended to room temperature (300K). By applying continuously increasing positive / negative pulses, 25 uniformly distributed polarization states are reversibly controlled in Gr / hBN ferroelectric transistors, which is reflected in the cyclic long-term enhancement and long-term suppression of the device current level, such as Figure 6 As shown in the upper middle figure; the current levels corresponding to the 25 polarization states do not degrade significantly over a period of more than 20 s and can be well separated, as shown in Figure 6 As shown in the figure below. 16 independent polarization states can be extracted from a single cycle. The stable and distinguishable current states enable the device to be applied to 4-bit high-density non-volatile memory, such as Figure 7 Based on the uniform multi-state polarization exhibited by Gr / hBN ferroelectric transistors, a deep convolutional neural network was constructed, as shown in Figure 8As shown in the upper middle figure, the recognition accuracy of MNIST handwritten digit images is as high as 98.4%, with only a 0.2% loss in accuracy compared to the baseline value. Figure 8 As shown in the figure below.

[0056] The above description is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principle of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A method for preparing an interlayer ferroelectric transistor having 25 polarization states, characterized in that: The steps include: S1, 2D material preparation: peeling off single-layer Gr and hBN flakes respectively; S2: Cut the PDMS and place it on a clean glass slide, and use oxygen plasma for surface treatment; spin-coat the PPC reagent on the PDMS surface, then place it on a hot plate and heat it at 105°C for 3 minutes, and use oxygen plasma to treat the surface of the PDMS that has been spin-coated with PPC; S3: Take two clean glass slides, add 3 ml of PC reagent on one of them, and then immediately cover it with another glass slide, then slowly pull the two glass slides apart to form a layer of PC film, cut a square hole in the middle of the 3M white tape, the area of ​​the square hole should be slightly larger than the surface-treated PDMS in S2, and then use it to stick the PC film to cover the surface-treated PDMS in S2 to prepare a PC / PPC / PDMS dry transfer carrier; S4: Cover the PC / PPC / PDMS dry transfer carrier on the single-layer Gr obtained in S1 at 90°C, then slowly lift the PC / PPC / PDMS dry transfer carrier, stick the single-layer Gr, and mark its position on the PC / PPC / PDMS dry transfer carrier; then align the straight edge of the single-layer Gr on the PC / PPC / PDMS dry transfer carrier with the straight edge of the hBN thin film on the silicon wafer and cover it, heat it to 180°C after covering and keep it for 2 minutes, and finally slowly lift the carrier, and the PPC / PC film will be thermally released on the silicon wafer; clean PPC and PC to complete the construction of the Gr / hBN heterojunction; S5: Spin-coat PMMA at a speed of 4000 r / s for 1 min on the surface of the silicon wafer where the Gr / hBN heterojunction is located, and then heat it at 170°C for 2 min; spin-coat PMMA at a speed of 4000 r / s for 1 min again, and then place it on a hot plate and heat it at 180°C for 5 min; use a field emission electron microscope and an electron beam exposure system to complete the exposure of the electrode, and then place the silicon wafer in a developer solution of isopropanol: water = 3:1 to complete the development for 30 seconds; use an electron beam deposition device to evaporate 5nm Ti / 60nm Au on the surface of the silicon wafer; soak the silicon wafer in acetone reagent, place it on a hot plate and heat it at 65°C to make the PMMA-carrying metal thin layer in the unexposed area fall off; soak the silicon wafer in isopropanol reagent for cleaning for 5 minutes, and then blow dry it with nitrogen to obtain a Gr / hBN ferroelectric transistor, that is, an interlayer ferroelectric transistor with a polarization state of 25.

2. The method for preparing an interlayer ferroelectric transistor having 25 polarization states according to claim 1, characterized in that: The specific steps of S1 are: S101, pre-cleaning the silicon wafer using an oxygen plasma system at 50W / 50sccm / 2min; S102, using blue tape to stick 4 to 5 square millimeter two-dimensional material crystals respectively, and aligning the tapes so that the crystals are evenly distributed in an area of ​​1 square centimeter on the tapes, and then covering the silicon wafer; S103, placing the silicon wafer covered by the blue tape on a hot plate and heating it at 100°C for 1 min, slowly peeling off the blue tape after cooling to complete mechanical peeling, and mechanical peeling is performed to obtain single-layer Gr and hBN thin sheets respectively.

3. The method for preparing an interlayer ferroelectric transistor having 25 polarization states according to claim 1, characterized in that: The specific steps of S2 are: S201, cut a small piece of PDMS and place it on a clean glass slide, and treat its surface with oxygen plasma under the conditions of 30W / 20sccm / 30s; S202, turning over the PDMS, and treating the surface again with oxygen plasma at 50W / 50sccm / 2min; S203, using a spin coater to spin coat the PPC reagent on the PDMS surface at a rotation speed of 4000 r / s for 1 min, then placing it on a hot plate and heating it at 105° C. for 3 min, and treating the PDMS spin-coated with PPC with oxygen plasma under the condition of 20 W / 10 sccm / 3 s.

4. The method for preparing an interlayer ferroelectric transistor having 25 polarization states according to claim 3, characterized in that: The mass fraction of the PPC reagent in S203 is 15% by mass, and the solvent is anisole.

5. The method for preparing an interlayer ferroelectric transistor having 25 polarization states according to claim 1, characterized in that: The mass fraction of the PC reagent in S3 is 5%, and the solvent is dichloromethane.

6. The method for preparing an interlayer ferroelectric transistor having 25 polarization states according to claim 1, characterized in that: The process of cleaning PPC and PC in S4 is: cleaning the silicon wafer in dichloromethane for 20 minutes, cleaning in acetone for 15 minutes, and cleaning in isopropanol for 5 minutes.

7. An interlayer ferroelectric transistor with a 25 polarization state obtained by the preparation method according to any one of claims 1 to 6, characterized in that: The heterojunction Gr / hBN is placed on a SiO2 / Si substrate, with the bottom layer being a hBN sheet and the top layer being a single layer of Gr. 5nm Ti / 60nm Au electrodes are constructed as source and drain electrodes by electron beam exposure and electron beam evaporation.

8. The interlayer ferroelectric transistor with 25 polarization states according to claim 7, characterized in that: The thicknesses of the single-layer Gr and hBN sheets are 0.34 nm and 20 nm respectively.

Images