Thin film transistor and display panel

Abstract

The invention relates to a thin film transistor and a display panel. The thin film transistor comprises a substrate; the active layer is positioned on one side of a part of the substrate; the first gate layer is located on the side, away from the substrate, of the active layer; the first gate dielectric layer is located between the active layer and the first gate layer, the first gate dielectric layer comprises a first dielectric layer, the first dielectric layer is located on the surface of the side, away from the substrate, of the active layer, the orthographic projection of the first dielectric layer on the substrate completely covers the orthographic projection of the active layer on the substrate, and the first dielectric layer does not make contact with the side wall of the active layer. According to the thin film transistor provided by the invention, the interface characteristic between the active layer and the first gate dielectric layer can be improved, so that the stability and bias reliability of the thin film transistor are improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a thin film transistor and a preparation method thereof, a driving substrate, a display panel and a display device. Background Art

[0002] As an important switch control element, thin film transistor (TFT) plays a key role in display devices. The thin film transistor structure has been widely used in liquid crystal display (LCD) displays and is one of the core components of modern display technology.

[0003] Metal oxide thin film transistors (MOTFTs) have the characteristics of high electron mobility, large-area production, and relatively low manufacturing temperature. As a research hotspot in recent years, they have received widespread attention. Most metal oxide thin film transistors are amorphous structures, and defects in the film will lead to insufficient bias reliability of semiconductor devices, which depends on the interface characteristics between the active layer and the gate dielectric layer in the thin film transistor. Summary of the invention

[0004] The present application provides a thin film transistor and a preparation method thereof, a driving substrate, a display panel and a display device, so as to improve the interface characteristics between an active layer and a gate dielectric layer, thereby improving the stability and bias reliability of the thin film transistor.

[0005] The present application provides a thin film transistor, comprising: a substrate; an active layer, located on one side of a portion of the substrate; a first gate layer, located on a side of the active layer away from the substrate; a first gate dielectric layer, located between the active layer and the first gate layer, the first gate dielectric layer comprising a first dielectric layer, the first dielectric layer being located on a surface of a side of the active layer away from the substrate, the orthographic projection of the first dielectric layer on the substrate completely covering the orthographic projection of the active layer on the substrate, and the first dielectric layer not contacting the side wall of the active layer.

[0006] In some embodiments, an orthographic projection of a side wall of the first dielectric layer on the substrate coincides with an orthographic projection of a side wall of the active layer on the substrate.

[0007] In some embodiments, a sidewall of the active layer is retracted toward an interior of the active layer relative to a sidewall of the first dielectric layer.

[0008] In some embodiments, a thickness of the first dielectric layer along a direction perpendicular to the substrate is 5 nm-20 nm.

[0009] In some embodiments, the first gate dielectric layer further includes: a second dielectric layer, the second dielectric layer including a first portion and a second portion, the first portion being located on a side of the first dielectric layer away from the active layer, and the second portion being located on a side of the active layer along a direction parallel to the substrate surface and covering a side wall of the first dielectric layer and a side wall of the active layer; wherein a thickness of the second portion along a direction perpendicular to the substrate is greater than a thickness of the first portion along a direction perpendicular to the substrate.

[0010] In some embodiments, the second dielectric layer is a single-layer structure.

[0011] In some embodiments, the second dielectric layer is a multi-layer structure.

[0012] In some embodiments, the second dielectric layer includes a first insulating layer and a second insulating layer, the first insulating layer is located on one side of the substrate and covers the surface of the first dielectric layer on a side facing away from the active layer, the sidewall of the first dielectric layer and the sidewall of the active layer; the second insulating layer is located on a side of the first insulating layer facing away from the substrate; wherein the thickness of the second insulating layer located on the side of the active layer along a direction parallel to the surface of the substrate is greater than the thickness of the second insulating layer located on the side of the first dielectric layer facing away from the active layer.

[0013] In some embodiments, the density of the first dielectric layer and the density of the first insulating layer are both greater than the density of the second insulating layer.

[0014] In some embodiments, the thickness fluctuation of the first insulating layer in various regions is smaller than the thickness fluctuation of the second insulating layer in various regions.

[0015] In some embodiments, it also includes: a source electrode, which penetrates the first gate dielectric layer on the side of the active layer away from the substrate and is connected to the source region in the active layer; a drain electrode, which penetrates the first gate dielectric layer on the side of the active layer away from the substrate and is connected to the drain region in the active layer.

[0016] In some embodiments, a second gate layer is located between the substrate and the active layer; a second gate dielectric layer is located between the second gate layer and the active layer; a conductive connector is located on the side of the active layer parallel to the substrate and penetrates the second gate dielectric layer and the first gate dielectric layer, and the conductive connector is connected to the second gate layer.

[0017] In some embodiments, the conductive connection is connected to the drain electrode of the active layer; the conductive connection is connected to the drain electrode and is made of the same material.

[0018] In some embodiments, the material of the second gate layer is a light-shielding material; and the orthographic projection of the second gate layer on the substrate completely covers the orthographic projection of the channel region of the active layer on the substrate.

[0019] The present application also provides a method for preparing a thin film transistor, comprising: forming an active layer and a first gate dielectric layer on one side of a substrate, the step of forming the first gate dielectric layer comprising forming a first dielectric layer, the first dielectric layer being located on a surface of the active layer facing away from the substrate, the orthographic projection of the first dielectric layer on the substrate completely covering the orthographic projection of the active layer on the substrate, and the first dielectric layer not contacting the side wall of the active layer; forming a first gate layer on a side of the first gate dielectric layer facing away from the active layer.

[0020] In some embodiments, the steps of forming the active layer and the first dielectric layer include: forming an active material layer on one side of the substrate; forming a first dielectric material layer on a side of the active material layer facing away from the substrate; etching the first dielectric material layer to form a first dielectric layer; and etching the active material layer using the first dielectric layer as a mask to form the active layer.

[0021] In some embodiments, the step of forming the first gate dielectric layer also includes: forming a first insulating layer; the first insulating layer is located on one side of the substrate and covers the surface of the first dielectric layer on the side away from the active layer, the side wall of the first dielectric layer and the side wall of the active layer; forming a second insulating layer on the side of the first insulating layer away from the substrate; wherein the thickness of the second insulating layer located on the side of the active layer along a direction parallel to the surface of the substrate is greater than the thickness of the second insulating layer located on the side of the first dielectric layer away from the active layer.

[0022] In some embodiments, the process of forming the first dielectric material layer includes an atomic layer deposition process; and the process of forming the first insulating layer includes an atomic layer deposition process.

[0023] The present application also provides a driving substrate, comprising the thin film transistor of the present application.

[0024] The present application also provides a display panel, comprising the thin film transistor of the present application.

[0025] The present application also provides a display device, including the display panel of the present application.

[0026] The technical solution of this application has the following technical effects:

[0027] The technical solution of the present application provides a thin film transistor and a preparation method, a driving substrate, a display panel and a display device. The first dielectric layer is used to protect the surface of the active layer facing away from the substrate during the formation of the active layer. There is no need to use a photoresist layer to directly define the pattern of the active layer, which can avoid the contact between the photoresist layer and the active layer, thereby avoiding photoresist residue and reducing the damage to the surface characteristics of the active layer, thereby improving the interface characteristics between the active layer and the first gate dielectric layer, and improving the stability and bias reliability of the thin film transistor.

[0028] Other features and advantages of the present application will be described in the following description, and partly become apparent from the description, or be understood by practicing the present application. The purpose and other advantages of the present application can be realized and obtained by the structures specifically pointed out in the description, claims and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The present application will be described in more detail below based on embodiments and with reference to the accompanying drawings:

[0030] Figure 1 A schematic diagram of the structure of a thin film transistor provided in an embodiment of the present application.

[0031] Figure 2 A schematic diagram of the structure between a first gate dielectric layer and an active layer in another thin film transistor provided in an embodiment of the present application.

[0032] Figure 3 A schematic diagram of the structure of another thin film transistor provided in an embodiment of the present application.

[0033] Figure 4 A schematic diagram of the structure between a first gate dielectric layer and an active layer in another thin film transistor provided in an embodiment of the present application.

[0034] Figure 5 A schematic diagram of the structure of another thin film transistor provided in an embodiment of the present application.

[0035] Figure 6 A schematic diagram of the structure of another thin film transistor provided in an embodiment of the present application.

[0036] Figure 7 A flow chart of a method for preparing a thin film transistor provided in an embodiment of the present application.

[0037] Figure 8 A schematic diagram of the structure after an active material layer and a first dielectric material layer are formed in a method for preparing a thin film transistor provided in an embodiment of the present application.

[0038] Fig. 9A schematic diagram of the structure after forming a first dielectric layer and an active layer in a method for preparing a thin film transistor provided in an embodiment of the present application.

[0039] Fig.10 A schematic diagram of the structure after a first gate dielectric layer and a first gate layer are formed in a method for preparing a thin film transistor provided in an embodiment of the present application.

[0040] Fig.11 A schematic diagram of the structure after forming a source region and a drain region in an active layer in a method for preparing a thin film transistor provided in an embodiment of the present application.

[0041] Fig.12 A schematic structural diagram of forming a source electrode, a drain electrode and a conductive connection in the steps of a method for preparing a thin film transistor provided in an embodiment of the present application.

[0042] Fig.13 A schematic diagram of the structure of a thin film transistor provided in an embodiment of the present application. DETAILED DESCRIPTION

[0043] In order to enable those skilled in the art to better understand the technical solution of the present application, and to fully understand and implement how the present application applies technical means to solve technical problems and achieve the corresponding technical effects, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only embodiments of a part of the present application, not all embodiments. The embodiments of the present application and the various features in the embodiments can be combined with each other without conflict, and the technical solutions formed are all within the scope of protection of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without making creative work should belong to the scope of protection of the present application.

[0044] The present application provides a thin film transistor, referring to Figure 1 , Figure 3 , Figure 5 and Figure 6 , including: a substrate 100 , an active layer 200 , a first gate layer 400 and a first gate dielectric layer 300 .

[0045] refer to Figure 1 , Figure 3 , Figure 5 and Figure 6, the active layer 200 is located on one side of a portion of the substrate 100. The first gate layer 400 is located on the side of the active layer 200 facing away from the substrate 100. The first gate dielectric layer 300 is located between the active layer 200 and the first gate layer 400. The first gate dielectric layer 300 includes a first dielectric layer 310, which is located on the surface of the active layer 200 facing away from the substrate 100, and the orthographic projection of the first dielectric layer 310 on the substrate 100 completely covers the orthographic projection of the active layer 200 on the substrate 100, and the first dielectric layer 310 does not contact the side wall of the active layer 200.

[0046] In this embodiment, the first dielectric layer 310 is used to protect the surface of the active layer 200 facing away from the substrate 100 during the formation of the active layer 200. There is no need to use a photoresist layer to directly define the pattern of the active layer 200, which can avoid the contact between the photoresist layer and the active layer 200, thereby avoiding photoresist residue and reducing damage to the surface characteristics of the active layer 200, thereby improving the interface characteristics between the active layer 200 and the first gate dielectric layer 300, and improving the stability and bias reliability of the thin film transistor.

[0047] In one embodiment, the thin film transistor may be an oxide thin film transistor (Oxide TFT) or a metal oxide thin film transistor, which is not specifically limited herein.

[0048] In one embodiment, the substrate 100 is a flexible substrate or a hard substrate, the hard substrate is, for example, a glass substrate, and the flexible substrate is, for example, a plastic substrate. The material of the substrate 100 can be selected according to the display performance and application scenario.

[0049] In one embodiment, the material of the active layer 200 includes any one of amorphous silicon (a-Si), microcrystalline silicon (poly-Si) and an oxide material, and the oxide material is composed of, for example, Indium Gallium Zinc Oxide (IGZO).

[0050] In one embodiment, reference Figure 1 , Figure 3 , Figure 5 and Figure 6 The active layer 200 includes a source region 210, a channel region 220, and a drain region 230. The source region 210 is located at one side of the channel region 220 and connected to the channel region 220. The drain region 230 is located at the other side of the channel region 220 and connected to the channel region 220. The source region 210 and the drain region 230 are doped with conductive ions.

[0051] In one embodiment, the material of the first gate layer 400 is a metal material or polysilicon.

[0052] In one embodiment, reference Figure 1 and Figure 6 The first gate dielectric layer 300 includes: a first dielectric layer 310 and a second dielectric layer 320; the second dielectric layer includes a first part and a second part, the first part is located on the side of the first dielectric layer 310 away from the active layer 200, and the second part is located on the side of the active layer 200 along a direction parallel to the surface of the substrate 100 and covers the sidewalls of the first dielectric layer 310 and the active layer 200; wherein the thickness of the second part along the direction perpendicular to the substrate 100 is greater than the thickness of the first part along the direction perpendicular to the substrate 100, so that the second dielectric layer 320 can play a role in flattening the plane, thereby reducing the probability of fracture and collapse of subsequent film layers, thereby helping to improve the stability and yield of subsequent film layers.

[0053] refer to Figure 1 The second dielectric layer 320 is a multi-layer structure. For example, the second dielectric layer 320 may be composed of a two-layer structure. In other exemplary embodiments, the second dielectric layer 320 may also be composed of a film layer structure of more than two layers, which is not specifically limited here. Figure 6 , the second dielectric layer 320 is a single-layer structure.

[0054] In one embodiment, the material of the first dielectric layer 310 is a silicon oxide layer, and the material of the second dielectric layer 320 is a silicon oxide layer.

[0055] refer to Figure 1 The second dielectric layer 320 includes a first insulating layer 321 and a second insulating layer 322. The first insulating layer 321 is located on one side of the substrate 100 and covers the surface of the first dielectric layer 310 on the side away from the active layer 200, the sidewall of the first dielectric layer 310 and the sidewall of the active layer 200; the second insulating layer 322 is located on the side of the first insulating layer 321 away from the substrate 100; wherein the thickness H4 of the second insulating layer 322 located on the side of the active layer 200 along a direction parallel to the surface of the substrate 100 is greater than the thickness H3 of the second insulating layer 322 located on the side of the first dielectric layer 310 away from the active layer 200. Among them, the function of the first insulating layer 321 is to cover one side of the substrate 100 and the side walls of the first dielectric layer 310 and the active layer 200, and the function of the second insulating layer 322 is to cover the side of the first insulating layer 321 away from the substrate 100 and achieve the purpose of flattening, thereby reducing the probability of subsequent film layers breaking and collapsing, thereby helping to improve the stability and yield of subsequent film layers.

[0056] In this embodiment, the second dielectric layer 320 is a multi-layer structure, which improves the covering effect of the step morphology that may be formed between the first dielectric layer 310 and the active layer 200, so as to further improve the formation yield of subsequent film layers and improve the structural stability of the entire thin film transistor.

[0057] In one embodiment, reference Figure 1 The thickness of the first insulating layer 321 and the thickness of the second insulating layer 322 fluctuate. The thickness fluctuation of each region of the first insulating layer 321 is smaller than the thickness fluctuation of the second insulating layer 322. The second insulating layer 322 is used to cover the thickness difference between each region of the first insulating layer 321 to improve the stability of subsequent film layers.

[0058] In one embodiment, reference Figure 1 The density of the first dielectric layer 310 and the density of the first insulating layer 321 are both greater than the density of the second insulating layer 322 to improve the performance and stability of the thin film transistor device.

[0059] In one embodiment, reference Figure 3 and Figure 5 , the first gate dielectric layer 300 only includes the first dielectric layer 310 .

[0060] In one embodiment, reference Figure 2 and Figure 3 The sidewall of the first dielectric layer 310 is flush with the sidewall of the active layer 200 in a direction perpendicular to the substrate 100, so that the orthographic projection of the first dielectric layer 310 on the substrate 100 coincides with the orthographic projection of the sidewall of the active layer 200 on the substrate 100, so that the orthographic projection of the first dielectric layer 310 on the substrate 100 just covers the orthographic projection of the active layer 200 on the substrate 100.

[0061] In one embodiment, reference Figure 1 , Figure 4 , Figure 5 and Figure 6 , the sidewall of the active layer 200 is retracted toward the inside of the active layer 200 relative to the sidewall of the first dielectric layer 310, so that a step morphology is formed between the first dielectric layer 310 and the active layer 200. The thickness of the first dielectric layer 310 along the direction perpendicular to the substrate 100 is 3nm-20nm. For example, the thickness of the first dielectric layer 310 along the direction perpendicular to the substrate 100 can be 3nm, 5nm, 7nm, 10nm, 15nm, 18nm or 20nm, which is not specifically limited here. The step morphology can be controlled by using the thickness difference between the first dielectric layer 310 and the active layer 200,

[0062] refer to Figure 1 and Figure 6, in order to facilitate the formation of minimized step morphology, so as to improve the formation yield of subsequent film layers. In this embodiment, the thickness of the active layer 200 along the direction perpendicular to the substrate 100 can be 10nm-50nm, for example, the thickness of the active layer 200 along the direction perpendicular to the substrate 100 can be 10nm, 15nm, 25nm, 30nm, 35nm, 40nm, 45nm, 50nm, etc., without specific limitation. In this embodiment, by reasonably controlling the thickness difference between the thickness of the active layer and the thickness of the first dielectric layer, the size of the step morphology that may be formed between the first dielectric layer 310 and the active layer 200 is controlled.

[0063] In one embodiment, reference Figure 1 , Figure 3 , Figure 5 and Figure 6 The thin film transistor further includes: an interlayer dielectric layer 40, covering the surface of the first gate layer 400 and the first gate dielectric layer 300 facing away from the substrate 100, so as to flatten the in-plane step difference between the first gate layer 400 and the first gate dielectric layer 300, thereby achieving the purpose of planarization.

[0064] In one embodiment, reference Figure 1 , Figure 3 , Figure 5 and Figure 6 The thin film transistor also includes: a source electrode 500, which penetrates the first gate dielectric layer 300 on the side of the active layer 200 away from the substrate 100 and is connected to the source region 210 in the active layer 200; a drain electrode 600, which penetrates the first gate dielectric layer 300 on the side of the active layer 200 away from the substrate 100 and is connected to the drain region 230 in the active layer 200.

[0065] In one embodiment, reference Figure 1 , Figure 3 , Figure 5 and Figure 6 The thin film transistor further includes: a planar layer 20 covering the source electrode 500 , the drain electrode 600 and the surface of the interlayer dielectric layer 40 facing away from the substrate 100 .

[0066] In one embodiment, the thin film transistor has a single-gate structure or a double-gate structure.

[0067] In one embodiment, reference Figure 1 , Figure 3 , Figure 5 and Figure 6 The thin film transistor has a dual-gate structure, and the thin film transistor further includes: a second gate layer 800 located between the substrate 100 and the active layer 200; and a second gate dielectric layer 900 located between the second gate layer 800 and the active layer 200.

[0068] In this embodiment, the thin film transistor is a dual-gate thin film transistor, the first gate layer 400 can be the top gate of the thin film transistor, and the second gate layer 800 can be the bottom gate of the thin film transistor. By changing the voltage of the first gate layer 400 and the second gate layer 800, the current between the source electrode 500 and the drain electrode 600 can be controlled to achieve the conduction and cutoff of the thin film transistor. Since the dual-gate structure can achieve better electric field distribution, the thin film transistor has a higher current density and improves the performance of the device. The double-gate thin film transistor (DG-TFT) is a transistor structure improved on the basis of the thin film transistor, with better electrical performance and higher switching speed.

[0069] In this embodiment, reference Figure 1 , Figure 3 , Figure 5 and Figure 6 The material of the second gate layer 800 serving as the bottom gate may be a light-shielding material. The orthographic projection of the second gate layer 800 on the substrate 100 completely covers the orthographic projection of the channel region 220 of the active layer 200 on the substrate 100. The opaque second gate layer 800 can well block the light from the backlight, thereby preventing the light from shining on the channel region 220 to generate carriers and affect the off-state current characteristics of the thin film transistor.

[0070] In other embodiments, the thin film transistor has a single-gate structure, and the second gate layer 800 and the second gate dielectric layer 900 may not be provided.

[0071] In one embodiment, reference Figure 1 , Figure 3 , Figure 5 and Figure 6 The thin film transistor further includes: a conductive connection member 700, which is located on the side of the active layer 200 parallel to the substrate 100 and penetrates the second gate dielectric layer 900 and the first gate dielectric layer 300, and the conductive connection member 700 is connected to the second gate layer 800. The conductive connection member 700 is connected to the drain electrode 600 of the active layer 200; the conductive connection member 700 is connected to the drain electrode 600 and is made of the same material.

[0072] Figure 7 A flow chart of a method for preparing a thin film transistor provided in an embodiment of the present application. The method for preparing a thin film transistor comprises:

[0073] Step S100: forming an active layer and a first gate dielectric layer on one side of the substrate, wherein the step of forming the first gate dielectric layer includes forming a first dielectric layer, wherein the first dielectric layer is located on a surface of the active layer facing away from the substrate, wherein the orthographic projection of the first dielectric layer on the substrate completely covers the orthographic projection of the active layer on the substrate, and the first dielectric layer does not contact the side wall of the active layer;

[0074] Step 200: forming a first gate layer on a side of the first gate dielectric layer away from the active layer.

[0075] In one embodiment, in conjunction with reference Figure 8 and Fig. 9 The steps of forming the active layer 200 and the first dielectric layer 310 include: forming an active material layer 200' on one side of the substrate 100; forming a first dielectric material layer 310' on a side of the active material layer 200' away from the substrate 100; etching the first dielectric material layer 310' to form the first dielectric layer 310; using the first dielectric layer 310 as a mask, etching the active material layer 200' to form the active layer 200, wherein the orthographic projection of the first dielectric layer 310 on the substrate 100 needs to completely cover the orthographic projection of the active layer 200 on the substrate 100, and the first dielectric layer 310 does not contact the side wall of the active layer 200.

[0076] In this embodiment, taking a thin film transistor with a dual-gate structure as an example, the method for preparing the thin film transistor also includes: before forming the active layer 200 and the first gate dielectric layer 300, forming a second gate layer 800 on one side of the substrate 100; before forming the active layer 200 and the first gate dielectric layer 300, forming a second gate dielectric layer 900 on the side of the second gate layer away from the substrate 100.

[0077] In other embodiments, when the thin film transistor has a single-gate structure, the second gate dielectric layer 900 and the second gate layer 800 may not be formed.

[0078] In one embodiment, the process of forming the active material layer 200 ′ is a deposition process, such as an atomic layer deposition (ALD) process.

[0079] In one embodiment, the process of forming the first dielectric material layer 310 ′ is a deposition process, such as atomic layer deposition, so as to utilize the thickness control capability of atomic layer deposition to form the first dielectric material layer 310 ′ with a thickness of 3 nm-20 nm.

[0080] In one embodiment, reference Figure 8 The method for preparing the thin film transistor further includes: forming a patterned photoresist layer 10 on a side of a portion of the first dielectric material layer 310' away from the active material layer 200'.

[0081] In one embodiment, reference Figure 8 and Fig. 9The first dielectric material layer 310 ′ is etched using the patterned photoresist layer 10 as a mask to form the first dielectric layer 310 , and the active material layer 200 ′ is etched using the first dielectric layer 310 and the patterned photoresist layer 10 as masks to form the active layer 200 .

[0082] In one embodiment, the process of etching the first dielectric material layer 310 ′ is an etching process. For example, a dry etching process may be used to etch the first dielectric material layer 310 ′ to form the first dielectric layer 310 .

[0083] In one embodiment, the process of etching the active material layer 200 ′ is an etching process, for example, a wet etching process is used to etch the active material layer 200 ′ to form the active layer 200 .

[0084] In one embodiment, after etching the active material layer 200 ′, the photoresist layer 10 is removed.

[0085] In one embodiment, reference Fig. 9 The sidewall of the active layer 200 is retracted toward the inside of the active layer 200 relative to the sidewall of the first dielectric layer 310, and a step morphology is formed between the first dielectric layer 310 and the active layer 200. In other embodiments, no step morphology may be formed between the first dielectric layer 310 and the active layer 200.

[0086] refer to Fig.10 The step of forming the first gate dielectric layer 300 also includes: forming a first insulating layer 321, the first insulating layer 321 is located on one side of the substrate 100 and covers the surface of the first dielectric layer 310 on the side away from the active layer 200, the sidewall of the first dielectric layer 310 and the sidewall of the active layer 200; forming a second insulating layer 322 on the side of the first insulating layer 321 away from the substrate 100; wherein the thickness H4 of the second insulating layer 322 located on the side of the active layer 200 along the direction parallel to the surface of the substrate 100 is greater than the thickness H3 of the second insulating layer 322 located on the side of the first dielectric layer 310 away from the active layer 200.

[0087] In one embodiment, the first gate dielectric layer 300 is a multi-layer structure. In other embodiments, the first gate dielectric layer can be a single-layer structure.

[0088] In one embodiment, the process of forming the first insulating layer 321 is a deposition process, such as an atomic deposition process, so as to prepare the first insulating layer 321 by utilizing the high coverage of the atomic deposition process to improve the formation yield of subsequent film layers.

[0089] In one embodiment, the process of forming the second insulating layer 322 is a deposition process, such as a chemical vapor deposition (CVD) process, to flatten the surface of the first insulating layer 321 away from the substrate 100, thereby reducing the probability of subsequent film layers breaking and collapsing, thereby helping to improve the stability and yield of subsequent film layers.

[0090] In one embodiment, reference Fig.10 The density characteristics of the first dielectric layer 310, the first insulating layer 321 and the second insulating layer 322 are that the density of the first dielectric layer 310 and the density of the first insulating layer 321 are greater than the density of the second insulating layer 322, so as to improve the performance and stability of the thin film transistor device.

[0091] refer to Fig.10 and Fig.11 After forming the first gate layer 400 on the side of the first gate dielectric layer 300 away from the active layer 200, the method for preparing the thin film transistor further includes: forming a source region 210 and a drain region 230 in the active layer 200; forming an interlayer dielectric layer 40 on the side of the first gate layer 400 and the second insulating layer 322 away from the substrate 100, and the interlayer dielectric layer 40 can flatten the in-plane step difference between the first gate layer 400 and the first gate dielectric layer 300, thereby achieving the purpose of planarization.

[0092] refer to Fig.12 The method for preparing the thin film transistor also includes: forming a source electrode 500, penetrating the first gate dielectric layer 300 on the side of the active layer 200 away from the substrate 100 and connected to the source region 210 in the active layer 200; forming a drain electrode 600, penetrating the first gate dielectric layer 300 on the side of the active layer 200 away from the substrate 100 and connected to the drain region 230 in the active layer 200.

[0093] In one embodiment, reference Fig.12 The method for preparing the thin film transistor also includes: forming a conductive connecting member 700, the conductive connecting member 700 is located on the side of the active layer 200 along a direction parallel to the substrate 100 and penetrates the second gate dielectric layer and the first gate dielectric layer 300, wherein the conductive connecting member 700 is connected to the second gate layer 800.

[0094] In one embodiment, reference Fig.13 The method for preparing the thin film transistor further includes: forming a planar layer 20 , wherein the planar layer 20 covers the source electrode 500 , the drain electrode 600 , the conductive connecting member 700 , and the surface of the interlayer dielectric layer 40 facing away from the substrate 100 .

[0095] In one embodiment, the present application provides a driving substrate, the driving substrate comprising a thin film transistor provided in any of the above embodiments, with reference to Figure 1 , Figure 3 , Figure 5 and Figure 6 The first dielectric layer 310 in the thin film transistor is used to protect the surface of the active layer 200 facing away from the substrate 100 during the formation of the active layer 200. There is no need to use a photoresist layer to directly define the pattern of the active layer 200, which can avoid the contact between the photoresist layer and the active layer 200, thereby avoiding photoresist residue and reducing the damage to the surface characteristics of the active layer 200, thereby improving the interface characteristics between the active layer 200 and the first gate dielectric layer 300, and improving the stability and bias reliability of the thin film transistor.

[0096] In one embodiment, the present application provides a display panel, which includes the thin film transistor provided in the above embodiment, referring to Figure 1 , Figure 3 , Figure 5 and Figure 6 The first dielectric layer 310 in the thin film transistor is used to protect the surface of the active layer 200 facing away from the substrate 100 during the formation of the active layer 200. There is no need to use a photoresist layer to directly define the pattern of the active layer 200, which can avoid the contact between the photoresist layer and the active layer 200, thereby avoiding photoresist residue and reducing the damage to the surface characteristics of the active layer 200, thereby improving the interface characteristics between the active layer 200 and the first gate dielectric layer 300, and improving the stability and bias reliability of the thin film transistor.

[0097] refer to Figure 1 , Figure 3 , Figure 5 and Figure 6 , the source electrode and / or drain electrode of the thin film transistor can be connected to the pixel electrode of the light emitting device layer. Exemplarily, the light emitting device layer includes: a pixel definition layer 50, in which a pixel opening 60 is provided; a light emitting layer located in the pixel opening 60; a cathode layer located on the side of the light emitting layer and the pixel definition layer away from the substrate; and an anode layer located between the planar layer 20 and the light emitting layer. The source electrode 500 of the thin film transistor is connected to the anode layer 30 of the light emitting device layer.

[0098] In one embodiment, the embodiment of the present application provides a display device, which includes the display panel provided in the above embodiment. Since the principle of solving the problem of the display device is similar to that of the aforementioned display panel, the implementation of the display panel in the display device can refer to the implementation of the aforementioned display panel, and the repeated parts will not be repeated. The display device can be: any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, etc. The other essential components of the display device should be understood by ordinary technicians in this field, and will not be repeated here, nor should they be used as limitations on the present invention.

[0099] The various embodiments or implementation methods in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the various embodiments can be referenced to each other.

[0100] In the description of this specification, reference to the terms "embodiment", "exemplary embodiment", "some embodiments", "illustrative embodiment", "example", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application.

[0101] In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0102] In the description of the present application, it should be noted that the terms "center", "up", "down", "left", "right", "vertical", "horizontal", "inside", "outside", etc., indicating orientations or positional relationships, are orientations or positional relationships based on the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0103] It is to be understood that the terms "first", "second", etc. used in this application can be used to describe various structures in this application, but these structures are not limited by these terms. These terms are only used to distinguish a first structure from another structure.

[0104] In one or more of the accompanying drawings, the same elements are represented by similar reference numerals. For the sake of clarity, the parts in the accompanying drawings are not drawn to scale. In addition, some well-known parts may not be shown. For the sake of simplicity, the structure obtained after several steps can be described in one figure. Many specific details of the present application are described below, such as the structure, materials, dimensions, processing technology and technology of the device, so that the present application can be more clearly understood. However, as those skilled in the art will appreciate, the present application can be implemented without following these specific details.

[0105] It should be noted that, in this application, the terms "include", "comprises" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element limited by the sentence "includes a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0106] Although the implementation methods disclosed in this application are as above, the above contents are only the implementation methods adopted for facilitating the understanding of this application, and are not intended to limit this application. Any technician in the technical field to which this application belongs can make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed in this application, but the scope of patent protection of this application shall still be based on the scope defined in the attached claims.

Claims

1. A thin film transistor, characterized in that: include: substrate; An active layer, located on one side of a portion of the substrate; A first gate layer, located on a side of the active layer away from the substrate; A first gate dielectric layer is located between the active layer and the first gate layer, the first gate dielectric layer includes a first dielectric layer, the first dielectric layer is located on a surface of the active layer facing away from the substrate, an orthographic projection of the first dielectric layer on the substrate completely covers an orthographic projection of the active layer on the substrate, and the first dielectric layer does not contact a side wall of the active layer.

2. The thin film transistor according to claim 1, characterized in that: An orthographic projection of a side wall of the first dielectric layer on the substrate coincides with an orthographic projection of a side wall of the active layer on the substrate.

3. The thin film transistor according to claim 1, characterized in that: The sidewall of the active layer is retracted toward the inside of the active layer relative to the sidewall of the first dielectric layer.

4. The thin film transistor according to any one of claims 1 to 3, characterized in that: The first gate dielectric layer further includes: a second dielectric layer, the second dielectric layer comprising a first portion and a second portion, the first portion being located on a side of the first dielectric layer away from the active layer, and the second portion being located on a side of the active layer in a direction parallel to the substrate surface and covering a sidewall of the first dielectric layer and a sidewall of the active layer; The thickness of the second portion along a direction perpendicular to the substrate is greater than the thickness of the first portion along a direction perpendicular to the substrate.

5. The thin film transistor according to claim 4, characterized in that: The second dielectric layer is a single-layer structure, or the second dielectric layer is a multi-layer structure.

6. The thin film transistor according to claim 5, characterized in that: When the second dielectric layer is a multi-layer structure, the second dielectric layer includes a first insulating layer and a second insulating layer, the first insulating layer is located on one side of the substrate and covers the surface of the first dielectric layer on a side away from the active layer, the sidewall of the first dielectric layer and the sidewall of the active layer; the second insulating layer is located on a side of the first insulating layer away from the substrate; The thickness of the second insulating layer located at the side of the active layer in a direction parallel to the substrate surface is greater than the thickness of the second insulating layer located at a side of the first dielectric layer away from the active layer.

7. The thin film transistor according to claim 1, characterized in that: Also includes: a source electrode, penetrating the first gate dielectric layer on a side of the active layer facing away from the substrate and connected to a source region in the active layer; Drain electrode; The first gate dielectric layer penetrates the active layer at a side away from the substrate and is connected to the drain region in the active layer.

8. The thin film transistor according to claim 7, characterized in that: Also includes: a second gate layer, located between the substrate and the active layer; A second gate dielectric layer, located between the second gate layer and the active layer; A conductive connector is located on the side of the active layer parallel to the substrate and penetrates the second gate dielectric layer and the first gate dielectric layer, the conductive connector is connected to the second gate layer; the conductive connector is connected to the drain electrode of the active layer; the conductive connector is connected to the drain electrode and is made of the same material.

9. The thin film transistor according to claim 8, characterized in that: The material of the second gate layer is a light-shielding material; the orthographic projection of the second gate layer on the substrate completely covers the orthographic projection of the channel region of the active layer on the substrate.

10. A display panel, characterized in that: The invention comprises a thin film transistor as claimed in any one of claims 1 to 9.

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