Inverted silver mirror light emitting diode chip and preparation method thereof

Abstract

The invention discloses a flip silver mirror light-emitting diode chip and a preparation method thereof, and the preparation method comprises the following steps: providing a substrate, sequentially depositing an N-type semiconductor layer, an active light-emitting layer and a P-type semiconductor layer on the substrate, and etching to form an exposed region on the N-type semiconductor layer, forming a current spreading layer on the P-type semiconductor layer through sputtering, forming a first insulating layer through deposition, forming a Bragg reflection layer through evaporation, forming an N-type Bragg reflection layer through hole and a P-type Bragg reflection layer through hole through etching, performing etching by using a plasma cleaning machine, performing Ar etching with gradually increased etching power, performing O2 etching, and then performing cleaning so as to form a P-type Bragg reflection layer through hole; the silver reflector layer is formed through evaporation, the stress of the silver metal layer is reduced through the electron beam evaporation method, and the problem that the silver reflector layer prepared through the electron beam evaporation technology falls off is greatly solved.

Description

Technical Field

[0001] The invention relates to the technical field of semiconductor preparation, in particular to an inverted silver mirror light emitting diode chip and a preparation method thereof. Background Art

[0002] Flip-chip silver mirror light-emitting diode chips are widely used due to their advantages such as back-light emission, strong heat dissipation capability, good weldability, large thrust and high reliability.

[0003] Existing flip-chip silver mirror LED chips usually use a magnetron sputtering process to prepare a silver reflector layer, but the use of magnetron sputtering equipment is expensive. In order to reduce the cost of preparing flip-chip silver mirror LEDs, the silver reflector layer is often prepared using an electron beam evaporation process. However, the silver reflector layer prepared by the electron beam evaporation process is extremely easy to fall off, resulting in a yield of only 10% for the prepared flip-chip silver mirror LED chips. Summary of the invention

[0004] In view of the above situation, it is necessary to provide a flip-chip silver mirror LED chip and a preparation method thereof to address the problem that the yield of the flip-chip silver mirror LED chip is too low when the silver reflector layer is prepared by electron beam evaporation process in the prior art.

[0005] A method for preparing a flip-chip silver mirror light-emitting diode chip comprises the following steps: Providing a substrate, depositing an N-type semiconductor layer, an active light-emitting layer, and a P-type semiconductor layer on the substrate in sequence, etching part of the active light-emitting layer and part of the P-type semiconductor layer to form a conductive step of the N-type semiconductor layer, and sputtering to form a current spreading layer on the P-type semiconductor layer to form a first-stage chip; Depositing a first insulating layer on the upper surface of the first-stage chip, forming a Bragg reflection layer on the first insulating layer by evaporation, etching a portion of the Bragg reflection layer to form an N-type Bragg reflection layer through hole and a P-type Bragg reflection layer through hole penetrating the Bragg reflection layer on the Bragg reflection layer, and opening an N-type first insulating layer through hole and a P-type first insulating layer through hole on the first insulating layer, wherein the N-type first insulating layer through hole corresponds to the position of the N-type Bragg reflection layer through hole, and the P-type first insulating layer through hole corresponds to the position of the P-type Bragg reflection layer through hole, so as to form a second-stage chip; Placing the second-stage chip in a plasma cleaning machine, introducing Ar into the plasma cleaning machine to perform a primary etching with gradually increasing etching power, and introducing O2 into the plasma cleaning machine to perform a secondary etching to clean the second-stage chip; Placing the cleaned second-stage chip in a vapor deposition furnace, introducing an Ar ion source into the vapor deposition path, and alternately vapor-depositing a first silver metal layer on the second-stage chip with a first vapor deposition power and a second vapor deposition power, wherein the first vapor deposition power is less than the second vapor deposition power, stopping introducing the Ar ion source, and alternately vapor-depositing a second silver metal layer on the first silver metal layer with a third vapor deposition power and a fourth vapor deposition power, wherein the third vapor deposition power is greater than the fourth vapor deposition power, and vapor-depositing a nickel metal layer on the second silver metal layer with a fifth vapor deposition power to form a silver reflector layer; Depositing a second insulating layer on the silver reflective mirror layer, and opening an N-type second insulating layer through hole and a P-type second insulating layer through hole on the second insulating layer to form a third-stage chip; On the chip in the third stage, an N-type connection metal layer and a P-type connection metal layer are formed by vapor deposition, a third insulating layer is deposited on the N-type connection metal layer and the P-type connection metal layer, and an N-type pad layer connected to the N-type connection metal layer and a P-type pad layer connected to the P-type connection metal layer are vapor deposited on the third insulating layer.

[0006] Beneficial effects of the present invention: The present invention forms an N-type semiconductor layer, an active light-emitting layer, a P-type semiconductor layer, a current expansion layer, a first insulating layer and a Bragg reflection layer on a substrate in sequence, and forms a first-stage chip and a second-stage chip in sequence. Ar and O2 are introduced into a plasma cleaning machine in sequence for etching, and impurities on the formed second-stage chip are cleaned, and then the chip is changed into a hydrophilic state. Finally, CO2 and deionized water are used to form a water-gas two-fluid to clean and remove the impurities, thereby providing good attachment conditions for a subsequent evaporated silver reflector layer. After completion, the silver reflector layer is formed by evaporation, and in the process of preparing a flip-chip silver mirror light-emitting diode, the silver reflector is prepared by an electron beam evaporation process, thereby reducing the use of a magnetron sputtering process, and greatly reducing the preparation process of the flip-chip silver mirror light-emitting diode chip. Cost, during the evaporation process, an Ar ion source is used to assist in the plating of the first silver metal layer to increase the adhesion between the silver metal layer and the wafer. In addition, different evaporation powers are used during the evaporation process to alternately evaporate the first silver metal layer and the second silver metal layer, and then evaporate to form a nickel metal layer on the second silver metal layer. The silver reflector layer is composed of the first silver metal layer, the second silver metal layer and the nickel metal layer. The first silver metal layer is a base layer, the second silver metal layer is a connecting layer, and the nickel metal layer is a protective layer. This structure reduces the stress of the entire silver reflector layer, and then forms a second insulating layer, an N-type connecting metal layer and a P-type connecting metal layer, an N-type pad layer and a P-type pad layer on the silver reflector layer. The interaction between the multiple layers greatly improves the problem of shedding of the silver reflector layer prepared by the electron beam evaporation process.

[0007] Furthermore, the step of depositing a first insulating layer on the upper surface of the first-stage chip is specifically: placing the first-stage chip in a reaction chamber, and depositing a SiO2 layer on the upper surface of the first-stage chip to form a first insulating layer, the temperature of the reaction chamber is between 200°C and 300°C, and the thickness of the first insulating layer is greater than 5000Å.

[0008] Furthermore, the Bragg reflection layer includes M periodic stacked structures, and the periodic stacked structures include TiO2 layers and SiO2 layers arranged from bottom to top.

[0009] Furthermore, the value range of M is 2-10.

[0010] Further, the initial power of the etching is 200W, the time of the etching is 40min-60min, the power increase rate of the etching is 5W / min-10W / min, and the flow rate of the Ar is between 150sccm-200sccm; The power of the secondary etching is 600w-1000w, the time of the secondary etching is 10min-15min, and the flow rate of the O2 is between 200sccm-300sccm; The second-stage chip is cleaned by using CO2 and deionized water to form a water-gas dual fluid.

[0011] Further, the first evaporation power is 1000W-2500W, the second evaporation power is 3000W-3500W, the third evaporation power is 2000W-3000W, and the fourth evaporation power is 1000W-2000W. The first evaporation power and the second evaporation power are alternately used to evaporate the first silver metal layer on the second-stage chip, the first evaporation power is less than the second evaporation power, the Ar ion source is stopped, the third evaporation power and the fourth evaporation power are alternately used to evaporate the second silver metal layer on the first silver metal layer, the third evaporation power is greater than the fourth evaporation power, and a nickel metal layer is evaporated on the second silver metal layer with a fifth evaporation power to form a silver reflector layer. The step includes: Performing evaporation at an evaporation power between 1000W and 1500W to form a first silver metal sublayer with a thickness of 10Å on the second-stage chip, performing evaporation at an evaporation power between 3000W and 3500W to form a second silver metal sublayer with a thickness of 100Å to 150Å on the first silver metal sublayer, performing evaporation at an evaporation power between 2000W and 2500W to form a third silver metal sublayer with a thickness of 40Å to 90Å on the second silver metal sublayer, wherein the first silver metal sublayer, the second silver metal sublayer and the third silver metal sublayer constitute a first silver metal layer; In other embodiments, the first silver metal layer may also be formed into more multiple silver metal sub-layers by alternately evaporating with the first evaporation power and the second evaporation power.

[0012] Stop introducing the Ar ion source into the evaporation furnace, perform evaporation on the third silver metal sublayer at an evaporation power of 2000W-2500W to form a fourth silver metal sublayer with a thickness of 400Å-500Å, perform evaporation on the fourth silver metal sublayer at an evaporation power of 2500W-3000W to form a fifth silver metal sublayer with a thickness of 400Å-500Å, perform evaporation on the fifth silver metal sublayer at an evaporation power of 1000W-1500W to form a sixth silver metal sublayer with a thickness of 500Å-2000Å, perform evaporation on the sixth silver metal sublayer at an evaporation power of 1500W-2000W to form a seventh silver metal sublayer with a thickness of 500Å-2000Å, and the fourth silver metal sublayer, the fifth silver metal sublayer, the sixth silver metal sublayer and the seventh silver metal sublayer constitute a second silver metal layer; In other embodiments, the second silver metal layer may also be formed into more multiple silver metal sub-layers by alternately evaporating with the third evaporation power and the fourth evaporation power.

[0013] On the seventh silver metal sublayer, evaporation is performed at an evaporation power between 3500W and 4000W to form a nickel metal layer with a thickness between 1000Å and 1500Å. The first silver metal layer, the second silver metal layer and the nickel metal layer constitute a silver reflector layer.

[0014] Further, the steps of vapor-depositing an N-type connection metal layer and a P-type connection metal layer on the chip in the third stage, depositing a third insulating layer on the N-type connection metal layer and the P-type connection metal layer, vapor-depositing an N-type pad layer connected to the N-type connection metal layer on the third insulating layer, and vapor-depositing a P-type pad layer connected to the P-type connection metal layer on the third insulating layer include: Vapor-depositing an N-type connection metal layer and a P-type connection metal layer on the third-stage chip, wherein the N-type connection metal layer is located in the through hole of the N-type second insulating layer, and a portion of the N-type connection metal layer is located on the second insulating layer, and the P-type connection metal layer is located in the through hole of the second insulating layer, and a portion of the P-type connection metal layer is located on the second insulating layer, to form a fourth-stage chip; Depositing a SiO2 layer on the fourth-stage chip to form a third insulating layer, and opening an N-type third insulating layer through hole and a P-type third insulating layer through hole on the third insulating layer to form a fifth-stage chip; An N-type pad layer and a P-type pad layer are formed on the fifth-stage chip by vapor deposition, wherein the N-type pad layer is connected to the N-type connection metal layer, and the P-type pad layer is connected to the N-type connection metal layer.

[0015] Furthermore, the step of vapor-depositing an N-type connection metal layer and a P-type connection metal layer on the chip of the third stage to form a chip of the fourth stage is specifically as follows: vapor-depositing an Al layer with a thickness of 3000Å, a Ti layer with a thickness of 1000Å, an Al layer with a thickness of 3000Å, a Ti layer with a thickness of 1000Å, a Ti layer with a thickness of 3000Å, an Al layer with a thickness of 1000Å, a Ti layer with a thickness of 3000Å, a Pt layer with a thickness of 2000Å and a Ti layer with a thickness of 50Å on the chip of the third stage to form an N-type connection metal layer and a P-type connection metal layer, and the vapor deposition power is between 2000W and 4000W.

[0016] Furthermore, the step of evaporating to form an N-type pad layer and a P-type pad layer on the fifth-stage chip is specifically as follows: evaporating in sequence on the fifth-stage chip a 1000Å Al layer, a 1000Å Ti layer, a 1000Å Al layer, a 1000Å Ti layer, a 1000Å Ni layer, a 1000Å Ti layer, a 1000Å Ni layer, a 1000Å Ti layer, a 1000Å Ni layer and a 3800Å AuSn layer with thicknesses respectively to form an N-type pad layer and a P-type pad layer, and the evaporation power is between 2000W-4000W.

[0017] The present invention also provides a flip-chip silver mirror light-emitting diode chip, which is prepared by the above-mentioned method for preparing the flip-chip silver mirror light-emitting diode chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0019] Figure 1 It is a flow chart of the method for preparing the flip-chip silver mirror light-emitting diode chip of the present invention; Figure 2 for Figure 1 The structural diagram after step S1 in FIG. Figure 3 for Figure 1 The structural diagram after step S2; Figure 4 for Figure 1 The structural diagram after step S4; Figure 5 for Figure 1The structural diagram after step S5; Figure 6 for Figure 1 Schematic diagram of the structure after step S6.

[0020] Explanation of the reference numerals: 10, substrate; 111, N-type semiconductor layer; 112, active light-emitting layer; 113, P-type semiconductor layer; 114, N-type semiconductor layer conductive step; 12, current spreading layer; 13, first insulating layer; 131, P-type first insulating layer through hole; 132, N-type first insulating layer through hole; 14, Bragg reflection layer; 141, P-type Bragg reflection layer through hole; 142, N-type Bragg reflection layer through hole; 15, silver reflector layer; 16, second insulating layer; 161, P-type second insulating layer through hole; 162, N-type second insulating layer through hole; 171, P-type connecting metal layer; 172, N-type connecting metal layer; 18, third insulating layer; 181, P-type third insulating layer through hole; 182, N-type third insulating layer through hole; 191, P-type pad layer; 192, N-type pad layer.

[0021] The embodiments of the present invention will be further described below with reference to the accompanying drawings. DETAILED DESCRIPTION

[0022] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the embodiments of the present invention, and should not be construed as limiting the present invention.

[0023] In the description of the embodiments of the present invention, it should be understood that the terms "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside" and "outside" etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the embodiments of the present invention and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present invention.

[0024] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0025] Embodiment 1 Reference Figures 1 to 6As shown, the present invention provides a method for preparing a flip-chip silver mirror light-emitting diode chip, comprising the following steps: S1: providing a substrate 10, depositing an N-type semiconductor layer 111, an active light-emitting layer 112, and a P-type semiconductor layer 113 on the substrate 10 in sequence, etching a portion of the active light-emitting layer 112 and a portion of the P-type semiconductor layer 113 to form an N-type semiconductor layer conductive step 114, and sputtering to form a current spreading layer 12 on the P-type semiconductor layer 113 to form a first-stage chip; Specifically, the substrate 10 is one of GaN, Al2O3, and Si. An N-type semiconductor layer 111, an active light-emitting layer 112, and a P-type semiconductor layer 113 are sequentially deposited on the substrate 10 by using a MOCVD (metal organic chemical vapor deposition) process. A photoresist is coated on the surface of the P-type semiconductor layer 113. Then, a part of the photoresist is removed by using an exposure and development process to expose a part of the P-type semiconductor layer 113. Then, an inductively coupled plasma etching process is used to remove the exposed P-type semiconductor layer 113 and the active light-emitting layer 112 thereunder. An N-type semiconductor layer conductive step 114 is formed above one side of the conductor layer 111, and then the photoresist is removed. Indium tin oxide is deposited on the surface of the P-type semiconductor layer 113 and the N-type semiconductor layer conductive step 114 using a magnetron sputtering process, and then photoresist is coated on the surface of the indium tin oxide. Then, part of the photoresist is removed by exposure and development to expose part of the indium tin oxide. Then, an indium tin oxide etching solution is used to remove the exposed indium tin oxide. Then, the photoresist is removed, and a current spreading layer 12 is formed above the P-type semiconductor layer 113 to form a first-stage chip.

[0026] S2: depositing a first insulating layer 13 on the upper surface of the first-stage chip, forming a Bragg reflection layer 14 on the first insulating layer 13 by evaporation, etching a portion of the Bragg reflection layer 14, forming an N-type Bragg reflection layer through hole 142 and a P-type Bragg reflection layer through hole 141 penetrating the Bragg reflection layer 14 on the Bragg reflection layer 14, opening an N-type first insulating layer through hole 132 and a P-type first insulating layer through hole 131 on the first insulating layer 13, the N-type first insulating layer through hole 132 corresponds to the N-type Bragg reflection layer through hole 142, and the P-type first insulating layer through hole 131 corresponds to the P-type Bragg reflection layer through hole 141, so as to form a second-stage chip; Specifically, a SiO2 layer is deposited on the surface of the first-stage chip by using a PECVD (plasma enhanced chemical vapor deposition) process, and a first insulating layer 13 is formed on the first-stage chip. The thickness of the first insulating layer 13 is 5500Å. The temperature of the reaction chamber during the deposition of the SiO2 layer is 260°C. Five groups of periodic stacked structures are evaporated on the surface of the first insulating layer 13 by evaporation. The periodic stacked structures include TiO2 layers and SiO2 layers arranged from bottom to top. Bragg inversion is formed on the first insulating layer 13. The first insulating layer 13 is provided with a first photoresist layer 14, wherein the first insulating layer 13 is provided with five groups of periodic stacked structures by evaporation, wherein the power of the TiO2 layer is set to 232W, the power of the SiO2 layer is set to 166W, the thickness of the Bragg reflector layer 14 is 5000Å, a photoresist is coated on the surface of the Bragg reflector layer 14, and then the photoresist on the Bragg reflector layer 14 is partially removed by exposure and development, and then the exposed Bragg reflector layer 14 is removed by inductively coupled plasma etching process, and a Bragg reflector layer 14 is formed on the Bragg reflector layer 14. The N-type Bragg reflection layer through hole 142 and the P-type Bragg reflection layer through hole 141 are formed to penetrate the Bragg reflection layer 14, and the first insulating layer 13 below the N-type Bragg reflection layer through hole 142 and the P-type Bragg reflection layer through hole 141 is exposed. Then, the photoresist is removed. A photoresist is applied to the surface of the Bragg reflection layer 14 and the N-type Bragg reflection layer through hole 142 and the P-type Bragg reflection layer through hole 141. Then, the photoresist is removed from the surface of the N-type Bragg reflection layer through hole 142 and the P-type Bragg reflection layer through hole 141 by exposure and development. Photoresist is used to expose the first insulating layer 13 below the N-type Bragg reflection layer through hole 142 and the P-type Bragg reflection layer through hole 141, and then the exposed first insulating layer 13 is removed by using BOE etching solution to form an N-type first insulating layer through hole 132 and a P-type first insulating layer through hole 131, and then the photoresist is removed, the N-type first insulating layer through hole 132 corresponds to the N-type Bragg reflection layer through hole 142, and the P-type first insulating layer through hole 131 corresponds to the P-type Bragg reflection layer through hole 141, so as to form a second-stage chip.

[0027] S3: placing the second-stage chip in a plasma cleaning machine, introducing Ar into the plasma cleaning machine to perform a primary etching with gradually increasing etching power, introducing O2 into the plasma cleaning machine to perform a secondary etching to clean the second-stage chip; Specifically, the following steps are included: S11: placing the second-stage chip in a plasma cleaning machine, introducing Ar into the plasma cleaning machine, the starting power of one etching is 200 W, the time of one etching is 60 min, and the power increase rate of one etching is 7 W / min as the etching time increases. The flow rate of the introduced Ar is 200 sccm. After this step is completed, the surface impurities of the second-stage chip are cleaned; S12: using the O2 of the plasma cleaning machine to etch the surface of the second-stage chip, the power of the secondary etching is 800w, the time of the secondary etching is 15min, and the flow rate of the introduced O2 is 260sccm. After this step is completed, the surface impurities of the second-stage chip become hydrophilic; S13: Use CO2 and deionized water to form a water-gas two-fluid to clean the second-stage chip. After this step is completed, the surface impurities of the second-stage chip are removed.

[0028] S4: placing the cleaned second-stage chip in an evaporation furnace, introducing an Ar ion source into the evaporation path, and alternately evaporating a first silver metal layer on the second-stage chip with a first evaporation power and a second evaporation power, wherein the first evaporation power is less than the second evaporation power, stopping introducing the Ar ion source, and alternately evaporating a second silver metal layer on the first silver metal layer with a third evaporation power and a fourth evaporation power, wherein the third evaporation power is greater than the fourth evaporation power, and evaporating a nickel metal layer on the second silver metal layer with a fifth evaporation power to form a silver reflector layer 15; Specifically, the cleaned second-stage chip is placed in a vapor deposition furnace, including coating photoresist on the Bragg reflection layer 14, the N-type Bragg reflection layer through hole 142, the P-type Bragg reflection layer through hole 141, the N-type first insulation layer through hole 132 and the P-type first insulation layer through hole 131, and the exposed parts of the N-type first insulation layer through hole 132 and the P-type first insulation layer through hole 131, then exposing and developing to remove part of the photoresist, then vapor-depositing the first silver metal layer and the second silver metal layer, the first silver metal layer has a thickness of 200Å, and the second silver metal layer has a thickness of 1800-5000Å, vapor-depositing a nickel metal layer on the second silver metal layer, and then using a blue film stripping process to remove the metal layer on the photoresist, the first silver metal layer, the second silver metal layer and the nickel metal layer constitute a silver reflector layer 15, and then removing the photoresist; Furthermore, evaporating the silver reflector layer 15 comprises the following steps: S21: placing the second-stage chip in an evaporation furnace, and introducing an Ar ion source into the evaporation furnace, the flow rate of the Ar ion source is 30 sccm, the power of the Ar ion source is 500 W, firstly setting the first evaporation power to 1500 W to form a first silver metal sublayer with a thickness of 10Å, and then setting the second evaporation power to 3500 W to form a second silver metal sublayer with a thickness of 150Å on the first silver metal layer, and then setting the first evaporation power to 2000 W to form a third silver metal sublayer with a thickness of 40Å on the second silver metal layer. The first silver metal sublayer, the second silver metal sublayer and the third silver metal sublayer constitute the first silver metal layer. Using an Ar ion source to assist evaporation can increase the adhesion between the silver metal layer and the wafer. In addition, different powers are used during the evaporation process, and the evaporation power is alternately formed to form a first silver metal layer of 200Å, thereby reducing the stress of the first silver metal layer; S22: stop introducing the Ar ion source into the evaporation furnace, set the third evaporation power to 2000 W, form a fourth silver metal sublayer with a thickness of 500 Å on the third silver metal sublayer, then set the third evaporation power to 2800 W, form a fifth silver metal sublayer with a thickness of 500 Å on the fourth silver metal sublayer, set the fourth evaporation power to 1000 W, form a sixth silver metal sublayer with a thickness of 1200 Å on the fifth silver metal sublayer, then set the fourth evaporation power to 2000 W, form a seventh silver metal sublayer with a thickness of 2000 Å on the sixth silver metal sublayer, the fourth silver metal sublayer, the fifth silver metal sublayer, the sixth silver metal sublayer and the seventh silver metal sublayer constitute a second silver metal layer; S23: The evaporation power is set to 3500W to form a nickel metal layer with a thickness of 1000Å on the seventh silver metal layer. The first silver metal layer, the second silver metal layer and the nickel metal layer constitute a silver reflector layer 15.

[0029] S5: depositing a second insulating layer 16 on the silver reflective mirror layer 15, and opening an N-type second insulating layer through hole 162 and a P-type second insulating layer through hole 161 on the second insulating layer 16 to form a third-stage chip; Specifically, a SiO2 layer is deposited on the silver reflector layer 15 using a PECVD process to form a second insulating layer 16, and then a photoresist is coated on the surface of the second insulating layer 16. Then, a portion of the photoresist is removed by exposure and development to expose a portion of the second insulating layer 16. Then, a BOE etching solution is used to remove the exposed second insulating layer 16, and then the photoresist is removed, and an N-type second insulating layer through hole 162 and a P-type second insulating layer through hole 161 are opened to form a third-stage chip.

[0030] S6: On the chip of the third stage, an N-type connection metal layer 172 and a P-type connection metal layer 171 are formed by evaporation, a third insulating layer 18 is deposited on the N-type connection metal layer 172 and the P-type connection metal layer 171, and an N-type pad layer 192 connected to the N-type connection metal layer 172 and a P-type pad layer 191 connected to the P-type connection metal layer 171 are evaporated on the third insulating layer 18; Specifically, on the chip of the third stage, an N-type connection metal layer 172 and a P-type connection metal layer 171 are formed by evaporation, the N-type connection metal layer 172 is located in the N-type second insulating layer through hole 162, and a portion of the N-type connection metal layer 172 is located on the second insulating layer 16, and the P-type connection metal layer 171 is located in the P-type second insulating layer through hole 161, and a portion of the P-type connection metal layer 171 is located on the second insulating layer 16, so as to form a chip of the fourth stage; A SiO2 layer is deposited on the fourth-stage chip to form a third insulating layer 18, and an N-type third insulating layer through hole 182 and a P-type third insulating layer through hole 181 are opened on the third insulating layer 18 to form a fifth-stage chip; In the fifth stage chip, an N-type pad layer 192 and a P-type pad layer 191 are formed by vapor deposition. The N-type pad layer 192 is connected to the N-type connection metal layer 172 , and the P-type pad layer 191 is connected to the P-type connection metal layer 171 .

[0031] Further, a photoresist is coated on the surface of the chip in the third stage, and then a part of the photoresist is removed by exposure and development, and then an N-type connection metal layer 172 and a P-type connection metal layer 171 are formed by evaporation, respectively, to form a fourth-stage chip, the steps of: setting the evaporation power to 3000W, and sequentially evaporating a 3000Å ​​Al layer, a 1000Å Ti layer, a 3000Å ​​Al layer, a 1000Å Ti layer, a 3000Å ​​Al layer, a 1000Å Ti layer, a 2000Å Pt layer and a 50Å Ti layer to form an N-type connection metal layer 172 and a P-type connection metal layer 171, removing the metal on the photoresist by a blue film stripping process, and then removing the photoresist to form a fourth-stage chip, and using a PECVD process to deposit a SiO2 layer as a third insulating layer 18 on the upper surface of the fourth-stage chip, and then coating the third insulating layer 18 with photoresist, and then exposing and developing. A portion of the photoresist is removed to expose a portion of the third insulating layer 18, and then the exposed third insulating layer 18 is removed using a BOE etching solution, and a P-type third insulating layer through hole 181 and an N-type third insulating layer through hole 182 are opened on the third insulating layer 18 to form a fifth-stage chip. The specific steps of evaporating an N-type pad layer 192 and a P-type pad layer 191 on the upper surface of the fifth-stage chip include: the evaporation power is set to 4000W, and the evaporation thickness is 1 000Å Al layer, 1000Å Ti layer, 1000Å Al layer, 1000Å Ti layer, 1000Å Ni layer, 1000Å Ti layer, 1000Å Ni layer, 1000Å Ti layer, 1000Å Ni layer and 3800Å AuSn layer are formed to form an N-type pad layer 192 and a P-type pad layer 191, and then the metal on the photoresist is removed through a blue film stripping process, and then the photoresist is removed.

[0032] The photoelectric performance test of the flip-chip silver mirror light-emitting diode chip prepared by the preparation method of this embodiment and the flip-chip silver mirror light-emitting diode chip prepared by the control example shows that the product yield is improved by 87.3% compared with the existing method, as shown in Table 1.

[0033] Embodiment 2 The difference from the first embodiment is that; In step S2: the thickness of the first insulating layer 13 is 5200Å, the temperature of the reaction chamber during the deposition of the SiO2 layer is 200°C, and the first electron beam evaporation method includes the following steps: evaporating two groups of periodically stacked TiO2 layers and SiO2 layers on the surface of the first insulating layer 13, the power for evaporating the TiO2 layer is set to 235W, the power for evaporating the SiO2 layer is set to 170W, and the thickness of the Bragg reflection layer 14 is 2000Å.

[0034] In step S11, the etching time is 40 minutes, the power increase rate is 5 W / min, and the flow rate of Ar is 170 sccm.

[0035] In step S12, the secondary etching time is 12 minutes, the secondary etching power is 600 W, and the flow rate of O2 is 200 sccm.

[0036] In step S21, the first evaporation power is first set to 1200W to evaporate a first silver metal sublayer with a thickness of 10Å, and then the second evaporation power is set to 3200W to evaporate a second silver metal sublayer with a thickness of 100Å. Then, the first evaporation power is set to 2200W to evaporate a third silver metal sublayer with a thickness of 40Å, and the second evaporation power is set to 3000W to evaporate a fourth silver metal sublayer with a thickness of 50Å. The first silver metal sublayer, the second silver metal sublayer, the third silver metal sublayer and the fourth silver metal sublayer constitute a first silver metal layer. During the evaporation process, an Ar ion source is used to assist the evaporation, the Ar ion source flow rate is 50sccm, and the Ar ion source power is 800W.

[0037] In step S22, the third evaporation power is first set to 2500W, and the fifth silver metal sublayer with a thickness of 400Å is evaporated. Then, the third evaporation power is set to 3000W, and the sixth silver metal sublayer with a thickness of 500Å is evaporated. The fourth evaporation power is set to 1200W, and the seventh silver metal sublayer with a thickness of 500Å is evaporated. Then, the fourth evaporation power is set to 1500W, and the eighth silver metal sublayer with a thickness of 1800Å is evaporated. The third evaporation power is set to 2300W, and the ninth silver metal sublayer with a thickness of 1000Å is evaporated. The fifth silver metal sublayer, the sixth silver metal sublayer, the seventh silver metal sublayer, the eighth silver metal sublayer and the ninth silver metal sublayer constitute the second silver metal layer.

[0038] In step S23, the evaporation power is set to 3700W, and a nickel metal layer with a thickness of 1200Å is evaporated. The first silver metal layer, the second silver metal layer and the nickel metal layer constitute the silver reflector layer 15.

[0039] In step S6 , the power for evaporating the N-type connection metal layer 172 and the P-type connection metal layer 171 is set to 2000W, and the power for evaporating the N-type pad layer 192 and the P-type pad layer 191 is set to 3000W.

[0040] The photoelectric performance test of this embodiment shows that the yield rate of the finished product is improved by 86.6% compared with the existing method, as shown in Table 1.

[0041] Embodiment 3 The difference from the first embodiment is that: In step S2: the thickness of the first insulating layer 13 is 6000Å, the temperature of the reaction chamber during the deposition of the SiO2 layer is 230°C, and the first electron beam evaporation method includes the following steps: 10 groups of periodically stacked TiO2 layers and SiO2 layers are evaporated on the surface of the first insulating layer 13, the power of the TiO2 layer is set to 238W, the power of the SiO2 layer is set to 165W, and the thickness of the Bragg reflection layer 14 is 10000Å.

[0042] In step S11, the etching time is 50 minutes, the power increase rate is 10 W / min, and the flow rate of Ar is 200 sccm.

[0043] In step S12, the secondary etching time is 15 minutes, the secondary etching power is 1000 W, and the flow rate of O2 is 300 sccm.

[0044] In step S21, the first evaporation power is first set to 1300W to evaporate a first silver metal sublayer with a thickness of 10Å, and then the second evaporation power is set to 3000W to evaporate a second silver metal sublayer with a thickness of 70Å, and then the first evaporation power is set to 2500W to evaporate a third silver metal sublayer with a thickness of 70Å, and the second evaporation power is first set to 3300W to evaporate a fourth silver metal sublayer with a thickness of 30Å, and then the first evaporation power is set to 2200W to evaporate a fifth silver metal sublayer with a thickness of 20Å. The first silver metal sublayer, the second silver metal sublayer, the third silver metal sublayer, the fourth silver metal sublayer and the fifth silver metal sublayer constitute a first silver metal layer. During the evaporation process, an Ar ion source is used to assist in the plating of the silver metal layer, the Ar ion source flow rate is 20sccm, and the Ar ion source power is 1000W.

[0045] In step S22, the third evaporation power is set to 2300 W, and the sixth silver metal sublayer with a thickness of 450 Å is evaporated, and then the third evaporation power is set to 2900 W, and the seventh silver metal sublayer with a thickness of 450 Å is evaporated, and the fourth evaporation power is set to 1500 W, and the eighth silver metal sublayer with a thickness of 500 Å is evaporated, and then the fourth evaporation power is set to 1800 W, and the ninth silver metal sublayer with a thickness of 500 Å is evaporated. The sixth silver metal sublayer, the seventh silver metal sublayer, the eighth silver metal sublayer and the ninth silver metal sublayer constitute the second silver metal layer.

[0046] In step S23, the evaporation power is set to 4000 W, and a nickel metal layer with a thickness of 1500Å is evaporated. The first silver metal layer, the second silver metal layer and the nickel metal layer constitute the silver reflector layer 15.

[0047] In step S6 , the power for evaporating the N-type connection metal layer 172 and the P-type connection metal layer 171 is set to 3500W, and the power for evaporating the N-type pad layer 192 and the P-type pad layer 191 is set to 2000W.

[0048] According to the photoelectric performance test, the yield of the finished product of this embodiment is improved by 86.3% compared with the existing method, as shown in Table 1.

[0049] Embodiment 4 The difference from the first embodiment is that; In step S2: the thickness of the first insulating layer 13 is 5600Å, the temperature of the reaction chamber during the deposition of the SiO2 layer is 300°C, and the first electron beam evaporation method includes the following steps: evaporating 6 groups of periodically stacked TiO2 layers and SiO2 layers on the surface of the first insulating layer 13, the power for evaporating the TiO2 layer is set to 240W, the power for evaporating the SiO2 layer is set to 162W, and the thickness of the Bragg reflection layer 14 is 6000Å.

[0050] In step S11, the etching time is 40 minutes, the power increase rate is 8 W / min, and the flow rate of Ar is 150 sccm.

[0051] In step S12, the secondary etching time is 10 minutes, the secondary etching power is 600 W, and the flow rate of O2 is 220 sccm.

[0052] In step S21, the first evaporation power is first set to 1000W, and the first silver metal sublayer with a thickness of 10Å is evaporated. Then, the second evaporation power is set to 3400W, and the second silver metal sublayer with a thickness of 100Å is evaporated. Then, the first evaporation power is set to 2300W, and the third silver metal sublayer with a thickness of 90Å is evaporated. The first silver metal sublayer, the second silver metal sublayer and the third silver metal sublayer constitute a first silver metal layer. During the evaporation process, an argon ion source is used to assist in the plating of the silver metal layer. The Ar ion source flow rate is 20sccm, and the Ar ion source power is 600W.

[0053] In step S22, the third evaporation power is first set to 2200W to evaporate a fourth silver metal sublayer with a thickness of 400Å, and then the third evaporation power is set to 2500W to evaporate a fifth silver metal sublayer with a thickness of 400Å, the fourth evaporation power is set to 1300W to evaporate a sixth silver metal sublayer with a thickness of 2000Å, and then the fourth evaporation power is set to 2000W to evaporate a seventh silver metal sublayer with a thickness of 2000Å, the eighth evaporation power is set to 1800W to evaporate an eighth silver metal sublayer with a thickness of 1000Å, the third evaporation power is set to 2100W to evaporate a ninth silver metal sublayer with a thickness of 400Å, and then the third evaporation power is set to 2500W to evaporate a tenth silver metal sublayer with a thickness of 400Å. The fourth silver metal sublayer, the fifth silver metal sublayer, the sixth silver metal sublayer, the seventh silver metal sublayer, the eighth silver metal sublayer, the ninth silver metal sublayer and the tenth silver metal sublayer constitute a second silver metal layer.

[0054] In step S23, the evaporation power is set to 3600W, and a nickel metal layer with a thickness of 1300Å is evaporated. The first silver metal layer, the second silver metal layer and the nickel metal layer constitute the silver reflector layer 15.

[0055] In step S6 , the power for evaporating the N-type connection metal layer 172 and the P-type connection metal layer 171 is set to 4000W, and the power for evaporating the N-type pad layer 192 and the P-type pad layer 191 is set to 3200W.

[0056] According to the photoelectric performance test, the yield rate of the finished product of this embodiment is improved by 84.7% compared with the existing method, as shown in Table 1.

[0057] Specifically, each finished product includes 7360 light-emitting diode chips, and a current of 65 mA and a voltage between 2.6 V and 3.0 V are passed through the light-emitting diode chips. Then, a photoelectric performance test is performed using a photoelectric performance test device, and a yield test is performed on the finished products. The voltage of the qualified chips is between 2.6 V and 3.0 V, and the brightness is between 80 mW and 130 mW. The following Table 1 shows the relevant data of the yield of the finished products of the existing method and each embodiment: Table 1

[0058] In summary, the present invention forms an N-type semiconductor layer 111, an active light-emitting layer 112, a P-type semiconductor layer 113, a current spreading layer 12, a first insulating layer 13 and a Bragg reflection layer 14 on a substrate 10 in sequence, and forms a first-stage chip and a second-stage chip in sequence. Ar and O2 are introduced into a plasma cleaning machine for etching in sequence to clean impurities on the formed second-stage chip, and then the chip is changed into a hydrophilic state. Finally, CO2 and deionized water are used to form a water-gas two-fluid to clean and remove impurities, thereby providing good adhesion conditions for the subsequent evaporated silver reflector layer 15. After completion, the silver reflector layer 15 is prepared by evaporation, and the electron beam evaporation process is used multiple times in the process of preparing the flip-chip silver mirror light-emitting diode, thereby reducing the use of the magnetron sputtering process and greatly reducing the preparation cost of the flip-chip silver mirror light-emitting diode chip. During the evaporation, an Ar ion source is used to assist in plating the first silver metal layer to increase the adhesion between the silver metal layer and the wafer. In addition, different evaporation powers are used in the evaporation process to alternately evaporate the first silver metal layer and the second silver metal layer, and then evaporate to form a nickel metal layer on the second silver metal layer, the first silver metal layer, the second silver metal layer and the nickel metal layer constitute a silver reflector layer 15, the first silver metal layer is a base layer, the second silver metal layer is a connecting layer, and the nickel metal layer is a protective layer, wherein the first silver metal layer and the second silver metal layer each include a plurality of silver metal sublayers. It can be seen from Table 1 that the number of layers of the first silver metal layer and the second silver metal layer is set in Example 1, and the inverted silver mirror light-emitting diode chip yield of the silver reflector layer 15 formed at last is the best, and the stress of the overall silver reflector layer 15 is reduced, and then the second insulating layer 16, the N-type connecting metal layer 172 and the P-type connecting metal layer 171, the N-type pad layer 192 and the P-type pad layer 191 are respectively formed on the silver reflector layer 15, and the interaction between the multiple layers greatly improves the problem of shedding of the silver reflector layer 15 prepared by the electron beam evaporation process.

[0059] In addition, compared with Embodiment 2, Embodiment 3 and Embodiment 4, Embodiment 1 has a higher finished product yield and relatively shorter production time, which effectively improves production efficiency.

[0060] The present invention also provides a flip-chip silver mirror light-emitting diode chip, which is prepared by the above-mentioned method for preparing the flip-chip silver mirror light-emitting diode chip.

[0061] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0062] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the attached claims.

Claims

1. A method for preparing a flip-chip silver mirror light-emitting diode chip, characterized in that: The following steps are involved: Providing a substrate, depositing an N-type semiconductor layer, an active light-emitting layer, and a P-type semiconductor layer on the substrate in sequence, etching part of the active light-emitting layer and part of the P-type semiconductor layer to form a conductive step of the N-type semiconductor layer, and sputtering to form a current spreading layer on the P-type semiconductor layer to form a first-stage chip; Depositing a first insulating layer on the upper surface of the first-stage chip, forming a Bragg reflection layer on the first insulating layer by evaporation, etching a portion of the Bragg reflection layer to form an N-type Bragg reflection layer through hole and a P-type Bragg reflection layer through hole penetrating the Bragg reflection layer on the Bragg reflection layer, and opening an N-type first insulating layer through hole and a P-type first insulating layer through hole on the first insulating layer, wherein the N-type first insulating layer through hole corresponds to the position of the N-type Bragg reflection layer through hole, and the P-type first insulating layer through hole corresponds to the position of the P-type Bragg reflection layer through hole, so as to form a second-stage chip; Placing the second-stage chip in a plasma cleaning machine, introducing Ar into the plasma cleaning machine to perform a primary etching with gradually increasing etching power, and introducing O2 into the plasma cleaning machine to perform a secondary etching to clean the second-stage chip; Placing the cleaned second-stage chip in a vapor deposition furnace, introducing an Ar ion source into the vapor deposition furnace, vapor-depositing a first silver metal layer on the second-stage chip alternately with a first vapor deposition power and a second vapor deposition power, wherein the first vapor deposition power is less than the second vapor deposition power, stopping introducing the Ar ion source, vapor-depositing a second silver metal layer on the first silver metal layer alternately with a third vapor deposition power and a fourth vapor deposition power, wherein the third vapor deposition power is greater than the fourth vapor deposition power, and vapor-depositing a nickel metal layer on the second silver metal layer with a fifth vapor deposition power to form a silver reflector layer; Depositing a second insulating layer on the silver reflective mirror layer, and opening an N-type second insulating layer through hole and a P-type second insulating layer through hole on the second insulating layer to form a third-stage chip; On the chip in the third stage, an N-type connection metal layer and a P-type connection metal layer are formed by vapor deposition, a third insulating layer is deposited on the N-type connection metal layer and the P-type connection metal layer, and an N-type pad layer connected to the N-type connection metal layer and a P-type pad layer connected to the P-type connection metal layer are vapor deposited on the third insulating layer.

2. The method for preparing a flip-chip silver mirror light-emitting diode chip according to claim 1, characterized in that: The step of depositing a first insulating layer on the upper surface of the first-stage chip is specifically: placing the first-stage chip in a reaction chamber, and depositing a SiO2 layer on the upper surface of the first-stage chip to form a first insulating layer, the temperature of the reaction chamber is between 200°C and 300°C, and the thickness of the first insulating layer is greater than 5000Å.

3. The method for preparing a flip-chip silver mirror light-emitting diode chip according to claim 1, characterized in that: The Bragg reflection layer includes M periodic stacked structures, and the periodic stacked structure includes a TiO2 layer and a SiO2 layer arranged from bottom to top.

4. The method for preparing a flip-chip silver mirror light-emitting diode chip according to claim 3, characterized in that: The value range of M is 2-10.

5. The method for preparing a flip-chip silver mirror light-emitting diode chip according to claim 1, characterized in that: The starting power of the first etching is 200W, the time of the first etching is 40min-60min, the power increase rate of the first etching is 5W / min-10W / min, and the flow rate of the Ar is between 150sccm-200sccm; the power of the second etching is 600w-1000w, the time of the second etching is 10min-15min, and the flow rate of the O2 is between 200sccm-300sccm.

6. The method for preparing a flip-chip silver mirror light-emitting diode chip according to claim 1, characterized in that: The first evaporation power is 1000W-2500W, the second evaporation power is 3000W-3500W, the third evaporation power is 2000W-3000W, and the fourth evaporation power is 1000W-2000W. The first evaporation power and the second evaporation power are alternately used to evaporate the first silver metal layer on the second-stage chip. The first evaporation power is less than the second evaporation power. The Ar ion source is stopped. The third evaporation power and the fourth evaporation power are alternately used to evaporate the second silver metal layer on the first silver metal layer. The third evaporation power is greater than the fourth evaporation power. A nickel metal layer is evaporated on the second silver metal layer with a fifth evaporation power. The step of forming a silver reflector layer includes: Performing evaporation at an evaporation power between 1000W and 1500W to form a first silver metal sublayer with a thickness of 10Å on the second-stage chip, performing evaporation at an evaporation power between 3000W and 3500W to form a second silver metal sublayer with a thickness of 100Å to 150Å on the first silver metal sublayer, performing evaporation at an evaporation power between 2000W and 2500W to form a third silver metal sublayer with a thickness of 40Å to 90Å on the second silver metal sublayer, wherein the first silver metal sublayer, the second silver metal sublayer and the third silver metal sublayer constitute a first silver metal layer; Stop introducing the Ar ion source into the evaporation furnace, perform evaporation on the third silver metal sublayer at an evaporation power of 2000W-2500W to form a fourth silver metal sublayer with a thickness of 400Å-500Å, perform evaporation on the fourth silver metal sublayer at an evaporation power of 2500W-3000W to form a fifth silver metal sublayer with a thickness of 400Å-500Å, perform evaporation on the fifth silver metal sublayer at an evaporation power of 1000W-1500W to form a sixth silver metal sublayer with a thickness of 500Å-2000Å, perform evaporation on the sixth silver metal sublayer at an evaporation power of 1500W-2000W to form a seventh silver metal sublayer with a thickness of 500Å-2000Å, and the fourth silver metal sublayer, the fifth silver metal sublayer, the sixth silver metal sublayer and the seventh silver metal sublayer constitute a second silver metal layer; On the seventh silver metal sublayer, evaporation is performed at an evaporation power between 3500W and 4000W to form a nickel metal layer with a thickness between 1000Å and 1500Å. The first silver metal layer, the second silver metal layer and the nickel metal layer constitute a silver reflector layer.

7. The method for preparing a flip-chip silver mirror light-emitting diode chip according to claim 1, characterized in that: The steps of vapor-depositing an N-type connection metal layer and a P-type connection metal layer on the chip in the third stage, depositing a third insulating layer on the N-type connection metal layer and the P-type connection metal layer, and vapor-depositing an N-type pad layer connected to the N-type connection metal layer and a P-type pad layer connected to the P-type connection metal layer on the third insulating layer include: Vapor-depositing an N-type connection metal layer and a P-type connection metal layer on the third-stage chip, wherein the N-type connection metal layer is located in the through hole of the N-type second insulating layer, and a portion of the N-type connection metal layer is located on the second insulating layer, and the P-type connection metal layer is located in the through hole of the second insulating layer, and a portion of the P-type connection metal layer is located on the second insulating layer, to form a fourth-stage chip; Depositing a SiO2 layer on the fourth-stage chip to form a third insulating layer, and opening an N-type third insulating layer through hole and a P-type third insulating layer through hole on the third insulating layer to form a fifth-stage chip; An N-type pad layer and a P-type pad layer are formed on the fifth-stage chip by vapor deposition, wherein the N-type pad layer is connected to the N-type connection metal layer, and the P-type pad layer is connected to the N-type connection metal layer.

8. The method for preparing a flip-chip silver mirror light-emitting diode chip according to claim 7, characterized in that: The steps of vapor-depositing an N-type connection metal layer and a P-type connection metal layer on the chip of the third stage to form the chip of the fourth stage are specifically as follows: An Al layer, a Ti layer, an Al layer, a Ti layer, an Al layer, a Ti layer, a Pt layer and a Ti layer are sequentially evaporated on the third-stage chip to form an N-type connection metal layer and a P-type connection metal layer, and the evaporation power is between 2000W and 4000W.

9. The method for preparing a flip-chip silver mirror light-emitting diode chip according to claim 7, characterized in that: The steps of evaporating and forming an N-type pad layer and a P-type pad layer on the chip in the fifth stage are specifically as follows: An Al layer, a Ti layer, an Al layer, a Ti layer, a Ni layer, a Ti layer, a Ni layer, a Ti layer, a Ni layer and an AuSn layer are sequentially evaporated on the fifth-stage chip to form an N-type pad layer and a P-type pad layer, and the evaporation power is between 2000W and 4000W.

10. A flip-chip silver mirror light-emitting diode chip, characterized in that: The invention is prepared by the method for preparing the flip-chip silver mirror light-emitting diode chip according to any one of claims 1 to 9.

Images