Cross-water-surface multi-channel visible light communication real-time system based on FPGA

Abstract

The invention discloses a cross-water-surface multi-channel visible light communication real-time system based on an FPGA (Field Programmable Gate Array), which adopts the FPGA as a real-time signal processing unit and processes signal transmission and reception at the same time. By integrating low density even check (LDPC) codes from 5G new radio, the system significantly improves its ability to detect dynamic W2A-OWC scenarios. The system also optimizes the use of FPGA resources by time multiplexing of the IP core of the LDPC decoder. The system not only supports monochromatic light transmission, but also supports polychromatic light transmission, and can cover LEDs with different wavelengths so as to meet various service requirements and adapt to complex environments. The light source array serves as a transmitting end, the detector array serves as a receiving end, a multi-channel transmitting and receiving module is achieved, the rate of a communication system can be increased, simultaneous transmission of multiple data streams is promoted, and the overall throughput is improved.

Description

Technical Field

[0001] The present invention belongs to the field of cross-surface visible light communication and FPGA real-time system, and in particular relates to a cross-surface multi-channel visible light communication real-time system based on FPGA. Background Art

[0002] In recent years, underwater activities and related wireless communications have attracted great interest from academia and industry. In order to explore and acquire ocean data efficiently and safely, communication links must be established between underwater platforms (such as underwater unmanned vehicles (UUVs) and sensors) and land platforms (such as unmanned aerial vehicles (UAVs) and base stations). Reliable cross-surface communications play an important role in various applications such as underwater monitoring and underwater rescue missions.

[0003] Radio frequency waves, acoustic waves, and light waves are three existing wireless carriers for transmission in air and water. Although radio frequency signals can propagate over long distances (up to tens of kilometers) and achieve high transmission rates (up to hundreds of Mbps) in air, they can only propagate a few meters in water due to high absorption and attenuation. Acoustic waves can propagate for several kilometers in water and have always been the first choice for underwater communications. However, the transmission rate of acoustic communication systems is only in the order of kilobits per second, which cannot meet the requirements of potential applications. In addition, most of the sound waves will be reflected by the water surface and attenuate greatly in the air. In summary, neither radio frequency nor acoustic waves can be used alone for communication across dynamic water surfaces.

[0004] Recent advances in optical wireless communications (OWC) have promoted the use of light waves as an alternative for cross-dynamic water surface communications. It has been demonstrated that water exhibits acceptable attenuation of light in the blue-green window (from 450 nm to 570 nm), laying the foundation for underwater optical wireless communications. Compared with RF waves and sound waves, light waves have several obvious advantages: first, the propagation attenuation of light waves in both water and air media is acceptable; second, according to the Fresnel formula, for small and medium incident angles, most of the light energy can pass through the W2A interface; third, OWC can provide high transmission rates at relatively low costs. These attractive properties make OWC a promising technology for cross-W2A interface communications.

[0005] In actual communication scenarios, the communication system is required to have the characteristics of high speed, high precision, real-time processing, good system stability and a large number of channels. Under these conditions, FPGA has become the preferred choice for performing real-time high-speed data acquisition and processing in communication systems due to its advantages such as high clock frequency, small internal delay, pure hardware parallel control, fast computing speed, flexible programming configuration, short development cycle, strong anti-interference ability and rich internal resources. Summary of the invention

[0006] In view of this, the present invention provides a cross-surface multi-channel visible light communication real-time system based on FPGA, which can effectively improve communication efficiency.

[0007] In order to achieve the above object, the technical solution adopted by the present invention is as follows: A real-time system for multi-channel visible light communication across water surface based on FPGA, the system comprises a transmitting end development board, a bias device, a light source array, a cross-water surface channel system, a detector array, and a receiving end development board arranged in sequence along a communication link; wherein, The transmitting end development board is used to receive the data from the host computer and pre-process it to couple the AC signal of the bias device with the DC signal from the DC power supply to drive the light source array to emit a light signal; After the optical signal reaches the detector array via the cross-surface channel system, it is received by the receiving end development board; The transmitting end development board and the receiving end development board both use FPGA as a real-time signal processing unit to perform real-time signal transmission and reception, and the receiving end development board uses the IP core of the LDPC decoder in a time-division manner.

[0008] Furthermore, the light source array is an LED array, the detector array is a photodetector array, the number of LED light sources in the LED array is the same as the number of photodetectors in the photodetector array, both are n, n≥3, and are placed in one-to-one correspondence.

[0009] Furthermore, the transmitting development board receives data from the FPGA transmitted downstream by the host computer, and successively adds address information, CRC check bits, LDPC encoding, synchronization headers and frames the data, and outputs the data through n channels of the digital-to-analog converter of the FPGA expansion board after OOK modulation, wherein the address information of the n output data channels is different.

[0010] Furthermore, the data frames of the n data channels output by the transmitting development board are not sent out simultaneously, and the latter data channel is delayed relative to the former data channel, so that the n data channels received by the receiving development board serially use one LDPC decoder IP core.

[0011] Furthermore, the receiving end development board converts the electrical signal from the detector array into a digital signal. After the digital signal passes through the initialization module, merging, downsampling, synchronization, channel estimation and log-likelihood ratio mapping, it is sent to the LDPC decoding IP core for decoding. The decoded data is subjected to CRC check and address information check. If the received data frame address information is the same as the sent data frame address information, the data is uploaded to the host computer and displayed.

[0012] The beneficial effects of the present invention are: The present invention provides a real-time system based on FPGA, which uses multi-channel communication to improve the rate of the communication system; the system not only supports monochromatic light transmission, but also supports multi-color light transmission, covering LEDs of different wavelengths to meet various service requirements and adapt to complex environments; the hardware logic of FPGA can directly process signals, reducing the delay of software processing, which is crucial for communication systems that require fast response; in addition, the received three-way data serially use one LDPC decoder together, realizing efficient use of FPGA resources. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 This is a block diagram of a real-time system for multi-channel visible light communication across water surface based on FPGA; Figure 2 This is a schematic diagram of the communication principle of each component of the transmitter; Figure 3 It is a schematic diagram of the structure of the data frame transmitted by the physical layer link of the transmitter; Figure 4 This is a schematic diagram of the timing of 3-way data transmission at the transmitter; Figure 5 Schematic diagram of the communication principle of each component at the receiving end. DETAILED DESCRIPTION

[0014] The present invention will be further described below in conjunction with the accompanying drawings and embodiments.

[0015] The present invention provides a real-time system for multi-channel visible light communication across water surface based on FPGA, which has a simple structure, can effectively improve the rate of the communication system, reduce the delay of software processing, and realize the efficient use of FPGA resources.

[0016] Specifically, Figure 1 The figure shows a schematic diagram of a real-time system for cross-surface multi-channel visible light communication based on FPGA, including a transmitting development board, a bias device, a light source array, a cross-surface channel system, a detector array, and a receiving development board arranged in sequence along the communication link. Among them, the transmitting development board is an AX7021 development board, and the receiving development board is an AX7325 development board. The light source array uses an LED array as the transmitting end, and the detector array uses a photodetector (APD) array as the receiving end to realize a multi-channel transmission transceiver module. Both the transmitting development board and the receiving development board use FPGA as a real-time signal processing unit to perform real-time signal transmission and reception, and the IP core of the LDPC decoder is used in time division to achieve efficient use of FPGA resources.

[0017] It should be noted that the wavelength range of the LED array can be selected arbitrarily, including but not limited to blue-green light sources. The wavelength range needs to be selected according to actual needs.

[0018] In one embodiment, the LED array is n (n≥3) LEDs with wavelengths between 450nm and 570nm, where n is preferably 3. The light emitted by the LED array underwater passes through the water-atmosphere interface of the cross-surface channel system and reaches the effective detection surface of the detector array.

[0019] It should be noted that when there are n LED arrays, there are also n APD arrays, the data sent by the transmitting development board is n channels, and the data received by the receiving development board is also n channels.

[0020] Among them, the wavelength of the LED array is in the blue-green window of 450nm to 570nm, which is used to reduce the attenuation of light in the underwater channel and ensure the transmission distance of the communication system.

[0021] In the experiment, the water tank is 3 meters long, 1 meter wide, and 0.6 meters high. Three LEDs are placed underwater in a triangle, 1 meter apart and 0.2 meters from the bottom of the water tank. The water depth in the water tank is maintained at 0.27 meters. The three APDs at the receiving end are installed on a rack 0.8 meters above the water surface, corresponding to the three LEDs, and placed in the air facing each other.

[0022] Specifically, the function of the transmitter is mainly to receive the data of the FPGA from the host computer through the serial port. After the data reaches the FPGA, it is stored in the first-in-first-out (FIFO) queue. When the data in the FIFO accumulates to the specified bit length, it is read out, and the address information, CRC check bits, LDPC encoding, synchronization header and framing are added to the data, and OOK modulation is performed. Finally, the signal is output through the three channels of the expansion board digital-to-analog converter (DAC) on the FPGA. After that, these three signals are respectively coupled with the DC signal from the DC power supply as the AC signal of the bias device to drive three LEDs (CREE XHP70) to control the LED light emission. The light signal emitted by the LED array passes through the water body, through the fluctuating water surface, and then through the atmospheric channel, and finally reaches the receiving end. Among them, the address information of the three data channels is different, which facilitates the receiver to distinguish the three data channels.

[0023] At the receiving end, first, the light signal emitted by the LED array reaches the photosensitive surface of the APD through the water-atmosphere interface. The light signal is received by three APDs and converted into corresponding three electrical signals. After that, the receiving end FPGA (ALINX AX7325B) uses a 3-channel analog-to-digital converter (ADC) to convert the electrical signals from the three APDs into digital signals respectively. At the receiving end FPGA, the digital signal is sent to the LDPC decoding IP core for decoding after the initialization module, merging, downsampling, synchronization, channel estimation and log-likelihood ratio (LLR) mapping. The decoded data is also subjected to CRC check and address information check. If the received data frame address is the same as the sending address, the data is uploaded to the host computer and displayed.

[0024] Example Figure 2 The following is a detailed schematic diagram of the transmitter. The USB of the host computer transmits uncoded file data to the FPGA (ALINX AX7021) through the USB to TTL module. FIFO is used as a buffer to handle the mismatch of data rates between the host computer and the FPGA. The baud rate of the host computer is 1953250 bps. To prevent FIFO overflow due to rate mismatch, the hardware flow control method RTS / CTS is used to control the write rate: the development board monitors the remaining space of the FIFO in real time. When the remaining space is less than a fixed value, the development board pulls the CTS pin high. After the host computer sends the content of the buffer area, it will stop sending. The total size of the FIFO is 2048 Bytes. After that, when the data in the FIFO accumulates to the specified bit length, it is read out, and address information, CRC check bits, LDPC encoding, synchronization headers, framing, and OOK modulation are added to the data. After the DAC output, the AC signal as a biaser is coupled with the DC signal to drive the LED to emit light.

[0025] like Figure 3 As shown in the figure, the data frame structure of the physical layer link transmission is used. The data physical layer transmission adopts LDPC coding of (2176, 1280), which is the standard channel coding used in 5G communication. The encoding and decoding are realized by the LDPC IP core in vivado.

[0026] It should be noted that due to the limited FPGA resources at the receiving end, if three LDPC decoder IP cores are used simultaneously when processing three data channels, the FPGA resources at the receiving end will be insufficient. Therefore, the data frames of the three data channels at the transmitting end are not sent out at the same time, but the second channel is delayed by 80 microseconds relative to the first channel, and the third channel is delayed by 80 microseconds relative to the second channel, ensuring that the three received data channels serially use one LDPC decoder IP core to achieve efficient use of FPGA resources. The transmission timing of the three data channels is as follows: Figure 4 .

[0027] Figure 5 The figure is a schematic diagram of the receiving end. The optical signal is received by three APDs and converted into three corresponding electrical signals, which are then sent to the receiving end FPGA for processing. After the digital signal passes through the initialization module, merging, downsampling, synchronization, channel estimation and log likelihood ratio (LLR) mapping, it is sent to the LDPC decoding IP core for decision decoding. Then, the address information of the decoded output data is extracted. If the received data frame address matches the sending address, the decoded data from the three channels are separated and then CRC check is performed. According to the CRC check result, the count of successfully decoded data frames in the register is updated. The number of received data frames can be determined by the synchronized frame count. Among them, the initialization module is different from the photon counting method. It receives the pulse signal through threshold selection; the synchronization module makes a decision based on the correlation value and energy value of the synchronization header. During LDPC decoding, in order to save resources, the three data are serialized; after decoding, the three data are separated by the address information, and then CRC check and error frame statistics are performed.

[0028] In order to simulate the underwater dynamic environment, a wave maker is placed in the underwater channel to make the channel dynamic. The system performance is tested under calm water surface conditions and wave water surface conditions.

[0029] Table 1 shows the number of frames sent, received, and CRC-corrected by the three channels under calm water conditions at the receiving end. It can be seen that under calm water conditions, the data frame transmission accuracy is 100%; Table 2 shows the number of frames sent, received, and CRC-corrected by the three channels under wave surface conditions at the receiving end. It can be seen that under wave surface conditions, the data frame transmission accuracy is 99.932%; Table 1

[0030]

[0031] Table 2

[0032]

[0033] This shows that the scheme can realize real-time multi-channel visible light communication for dynamic cross-water channels with lower complexity.

[0034] The specific embodiments described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A real-time system for multi-channel visible light communication across water surface based on FPGA, characterized in that: The system includes a transmitting end development board, a bias device, a light source array, a cross-surface channel system, a detector array, and a receiving end development board arranged in sequence along the communication link; wherein, The transmitting end development board is used to receive the data from the host computer and pre-process it to couple the AC signal of the bias device with the DC signal from the DC power supply to drive the light source array to emit a light signal; After the optical signal reaches the detector array via the cross-surface channel system, it is received by the receiving end development board; The transmitting end development board and the receiving end development board both use FPGA as a real-time signal processing unit to perform real-time signal transmission and reception, and the receiving end development board uses the IP core of the LDPC decoder in a time-division manner.

2. According to the FPGA-based real-time system for cross-surface multi-channel visible light communication according to claim 1, it is characterized in that: The light source array is an LED array, the detector array is a photodetector array, the number of LED light sources in the LED array is the same as the number of photodetectors in the photodetector array, both are n, n≥3, and are placed in one-to-one correspondence.

3. According to the FPGA-based real-time system for cross-surface multi-channel visible light communication according to claim 2, it is characterized in that: The transmitting development board receives the FPGA data transmitted downstream from the host computer, and successively adds address information, CRC check bits, LDPC encoding, synchronization headers and frames the data, and outputs the data through n channels of the FPGA expansion board digital-to-analog converter after OOK modulation, wherein the address information of the n output data channels is different.

4. According to the FPGA-based real-time system for cross-surface multi-channel visible light communication according to claim 3, it is characterized in that: The data frames of the n data paths output by the transmitting end development board are not sent out at the same time, and the latter data path is delayed relative to the former data path, so that the n data paths received by the receiving end development board serially use one LDPC decoder IP core.

5. According to the FPGA-based real-time system for cross-surface multi-channel visible light communication according to claim 1, it is characterized in that: The receiving end development board converts the electrical signal from the detector array into a digital signal. After the digital signal passes through the initialization module, merging, downsampling, synchronization, channel estimation and log-likelihood ratio mapping, it is sent to the LDPC decoding IP core for decoding. The decoded data is subjected to CRC check and address information check. If the received data frame address information is the same as the sent data frame address information, the data is uploaded to the host computer and displayed.

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