Circuit board and manufacturing method thereof

Abstract

The invention discloses a circuit board and a manufacturing method of the circuit board. The circuit board comprises at least one circuit structure unit; the circuit structure unit comprises at least one circuit unit; the circuit unit comprises an integrated circuit substrate, a first packaging layer, a second packaging layer and a plurality of semiconductor devices; the integrated circuit substrate comprises a plurality of accommodating holes arranged at intervals; the first packaging layer is located at one side of the integrated circuit substrate, and the second packaging layer is located at one side, far away from the first packaging layer, of the integrated circuit substrate; the first packaging layer comprises a plurality of first blind holes and first conductive structures located in the first blind holes; the second packaging layer comprises a plurality of second blind holes and second conductive structures located in the second blind holes; the vertical projection of the first blind hole on the integrated circuit substrate is located in the vertical projection of the semiconductor device on the integrated circuit substrate. According to the invention, the circuit board can be developed towards the miniaturization direction, the heat dissipation performance of the circuit board can be improved, and parasitic parameters generated by the circuit board can be reduced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a circuit board and a method for manufacturing the circuit board. Background Art

[0002] With the rapid development of technologies such as AI, 5G, IoT, cloud computing, and big data, the demand for communication and data transmission between electronic devices has also shown explosive growth. The increase in demand for I / O ports has become another key factor in promoting the development of semiconductor technology. Taking AI, which is currently the hottest technology, as an example, AI servers are generally equipped with graphics processing units (GPU) modules compared to traditional servers, which increases the area of ​​the circuit board, the number of layers, and the corresponding increase in the volume of the circuit board, resulting in a decrease in the space utilization of the server. In addition, with the increase of GPU modules, the system will have more serious parasitic parameter problems under high power conditions. With the increase in computing power, more GPU modules will be integrated in the future, and improvements in circuit board volume and parasitic parameters are imminent. Summary of the invention

[0003] The present invention provides a circuit board and a method for manufacturing the circuit board, which can not only make the circuit board develop in the direction of miniaturization, but also improve the heat dissipation performance of the circuit board and reduce the parasitic parameters generated by the circuit board.

[0004] According to one aspect of the present invention, there is provided a circuit board, the circuit board comprising: at least one circuit structure unit; the circuit structure unit comprises at least one circuit unit;

[0005] The circuit unit includes an integrated circuit substrate, a first packaging layer, a second packaging layer and a plurality of semiconductor devices;

[0006] The integrated circuit substrate comprises a plurality of spaced-apart accommodation holes, and each of the semiconductor devices is located in a corresponding accommodation hole;

[0007] The first packaging layer is located on one side of the integrated circuit substrate, and the second packaging layer is located on a side of the integrated circuit substrate away from the first packaging layer;

[0008] The first packaging layer comprises a plurality of first blind holes and a first conductive structure located in each of the first blind holes; the second packaging layer comprises a plurality of second blind holes and a second conductive structure located in each of the second blind holes;

[0009] The vertical projection of the first blind hole on the integrated circuit substrate is located within the vertical projection of the semiconductor device on the integrated circuit substrate, and the vertical projection of the second blind hole on the integrated circuit substrate is located within the vertical projection of the semiconductor device on the integrated circuit substrate;

[0010] Each of the first conductive structures and each of the second conductive structures are electrically connected to the semiconductor device.

[0011] Optionally, the circuit board includes at least two of the circuit structure units and at least one bracket unit;

[0012] The bracket unit is used to connect two adjacent circuit structure units, and make the angle between the two connected circuit structure units be a set angle.

[0013] Optionally, the circuit structure unit includes at least two stacked circuit units and an interlayer insulating layer located between two adjacent layers of the circuit units, wherein the circuit units in the same circuit structure unit are electrically connected.

[0014] Optionally, the circuit structure unit includes at least one third blind hole and a third conductive structure located in the third blind hole;

[0015] The third blind hole passes through the circuit structure unit;

[0016] The circuit units in the same circuit structure unit are electrically connected via the third conductive structure.

[0017] Optionally, the first packaging layer further includes a first insulating layer and a first metal layer, the first insulating layer is located between the integrated circuit substrate and the first metal layer, and the first conductive structure is electrically connected to the first metal layer;

[0018] The second packaging layer further includes a second insulating layer and a second metal layer, the second insulating layer is located between the integrated circuit substrate and the second metal layer, and the second conductive structure is electrically connected to the second metal layer.

[0019] Optionally, the semiconductor device includes a packaging film and a chip module;

[0020] The packaging film wraps the side surface of the chip module;

[0021] The chip module includes a chip structure, a first metal electrode layer and a second metal electrode layer;

[0022] The first metal electrode layer is located on the top surface of the chip structure, and the second metal electrode layer is located on the bottom surface of the chip structure.

[0023] Optionally, a shape of a vertical projection of the first metal electrode layer on the chip structure is different from a shape of a vertical projection of the second metal electrode layer on the chip structure.

[0024] Optionally, the thickness of the semiconductor device ranges from 0.25 mm to 0.35 mm.

[0025] Optionally, the integrated circuit substrate includes at least three first alignment holes;

[0026] The first packaging layer further includes at least three second alignment holes;

[0027] The second packaging layer further includes at least three third alignment holes;

[0028] The vertical projection of the first alignment hole on the first packaging layer does not completely overlap with the second alignment hole;

[0029] A vertical projection of the first alignment hole on the second packaging layer does not completely overlap with the third alignment hole.

[0030] Optionally, the circuit board further includes a heat dissipation structure;

[0031] The heat dissipation structure surrounds each of the circuit structure units.

[0032] According to another aspect of the present invention, a method for manufacturing a circuit board is provided, and the method for manufacturing a circuit board is used to manufacture the circuit board provided by any embodiment of the present invention.

[0033] An embodiment of the present invention provides a circuit board, which includes at least one circuit structure unit, and the circuit structure unit includes at least one circuit unit. The circuit unit includes an integrated circuit substrate, a first packaging layer, a second packaging layer and a plurality of semiconductor devices. The integrated circuit substrate includes a plurality of spaced accommodation holes, and the accommodation holes are used to accommodate semiconductor devices. In this embodiment, the semiconductor device is embedded in the integrated circuit substrate, which can realize the secondary packaging of the semiconductor device, and can also avoid placing the semiconductor device on the surface of the integrated circuit substrate to increase the volume of the circuit board, and can also make the surface of the integrated circuit substrate electrically connected to more other devices, thereby improving the integration of the circuit board. In this embodiment, the first packaging layer is located on one side of the integrated circuit substrate, and the second packaging layer is located on the side of the integrated circuit substrate away from the first packaging layer. The first packaging layer includes a plurality of first blind holes and a first conductive structure located in each of the first blind holes, and the second packaging layer includes a plurality of second blind holes and a second conductive structure located in each of the second blind holes. The external device can be electrically connected to the semiconductor device through the first conductive structure in the first blind hole and / or the second conductive structure in the second blind hole. Compared with the current connection with semiconductor devices through bonding wires, the blind hole connection method used in this embodiment generates smaller parasitic parameters, and the first blind hole and the second blind hole can conduct the heat generated by the semiconductor device to the outside of the circuit board to achieve double-sided heat dissipation. In summary, the circuit board provided in this example can not only make the circuit board develop in the direction of miniaturization, but also improve the heat dissipation performance of the circuit board, and can also reduce the parasitic parameters generated by the circuit board.

[0034] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0036] Figure 1 is a schematic structural diagram of a circuit board provided according to an embodiment of the present invention;

[0037] Figure 2 is a schematic structural diagram of a circuit unit provided according to an embodiment of the present invention;

[0038] Figure 3 is a structural schematic diagram of another circuit unit provided according to an embodiment of the present invention;

[0039] Figure 4 is a schematic cross-sectional structure diagram of an integrated circuit substrate provided according to an embodiment of the present invention;

[0040] Figure 5 is a schematic diagram of a top view of an integrated circuit substrate provided according to an embodiment of the present invention;

[0041] Figure 6 is a schematic structural diagram of another circuit board provided according to an embodiment of the present invention;

[0042] Figure 7 is a schematic diagram of a top surface structure of a semiconductor device provided according to an embodiment of the present invention;

[0043] Figure 8 is a schematic diagram of the bottom structure of a semiconductor device provided according to an embodiment of the present invention;

[0044] Fig. 9 is a schematic structural diagram of a first encapsulation layer provided according to an embodiment of the present invention;

[0045] Fig.10 is a schematic structural diagram of another circuit board provided according to an embodiment of the present invention;

[0046] Fig.11 The present invention is a schematic diagram of a circuit board manufacturing process according to an embodiment of the present invention. DETAILED DESCRIPTION

[0047] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0048] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0049] Figure 1 is a schematic diagram of the structure of a circuit board provided according to an embodiment of the present invention, Figure 2 is a schematic structural diagram of a circuit unit provided according to an embodiment of the present invention, Figure 3 is a schematic structural diagram of another circuit unit provided according to an embodiment of the present invention, Figure 4 is a schematic cross-sectional structure diagram of an integrated circuit substrate provided according to an embodiment of the present invention, Figure 5 is a schematic diagram of a top view of an integrated circuit substrate provided according to an embodiment of the present invention, with reference to Figure 1-Figure 5 The circuit board provided in this embodiment includes: at least one circuit structure unit 100; the circuit structure unit 100 includes at least one circuit unit 110 (refer to Figure 1 The circuit unit 110 includes an integrated circuit substrate 3, a first packaging layer 120, a second packaging layer 130 and a plurality of semiconductor devices 140 (see Figure 2 and Figure 3 The integrated circuit substrate 3 includes a plurality of spaced-apart accommodation holes 4 (see Figure 4 and Figure 5Each semiconductor device 140 is located in a corresponding accommodation hole 4; the first packaging layer 120 is located on one side of the integrated circuit substrate 3, and the second packaging layer 130 is located on the side of the integrated circuit substrate 3 away from the first packaging layer 120; the first packaging layer 120 includes a plurality of first blind holes 121 and a first conductive structure 124 located in each first blind hole 121 (see Figure 3 ), the second packaging layer 130 includes a plurality of second blind holes 131 and a second conductive structure 134 located in each of the second blind holes 131 (see Figure 3 ); the vertical projection of the first blind hole 121 on the integrated circuit substrate 3 is located within the vertical projection of the semiconductor device 140 on the integrated circuit substrate 3, and the vertical projection of the second blind hole 131 on the integrated circuit substrate 3 is located within the vertical projection of the semiconductor device 140 on the integrated circuit substrate 3; each first conductive structure 124 and each second conductive structure 134 are electrically connected to the semiconductor device 140.

[0050] Specifically, the circuit board may include multiple circuit structure units 100, and a single circuit structure unit 100 may include multiple circuit units 110, so that multiple semiconductor devices 140 can be integrated in one circuit board. The circuit board may also include one circuit structure unit 100, and the circuit structure unit 100 may also include one circuit unit 110, so that the heat dissipation performance of the circuit board can be improved.

[0051] Figure 2 The circuit unit 110 shown is not provided with the first conductive structure and the second conductive structure. Figure 3 The circuit unit 110 shown includes a first conductive structure 124 and a second conductive structure 134. The first conductive structure 124 may cover the sidewall of the first blind hole 121 and be electrically connected to the semiconductor device 140, the second conductive structure 134 may cover the sidewall of the second blind hole 131 and be electrically connected to the semiconductor device 140, the first conductive structure 124 may also fill the first blind hole 121 and be electrically connected to the semiconductor device 140, and the second conductive structure 134 may also fill the second blind hole 131 and be electrically connected to the semiconductor device 140. Figure 3 The first conductive structure 124 fills up the first blind hole, and the second conductive structure 134 fills up the second blind hole.

[0052] The integrated circuit substrate 3 may be a printed circuit board (PCB) substrate, and the semiconductor device 140 may be a panel level package (PLP) device, a logic device, a metal oxide semiconductor (MOS) device, a capacitor, an inductor, a resistor, a diode, a triode, and an insulated gate bipolar transistor (IGBT). The functions of the semiconductor devices 140 in the same circuit unit 110 may be different. A semiconductor device 140 may be placed in each receiving hole 4 in the integrated circuit substrate 3. The size of the receiving hole 4 may be slightly larger than the size of the semiconductor device 140, or may be equal to the size of the semiconductor device 140.

[0053] Before the first conductive structure 124 and the second conductive structure 134 are provided, the first blind hole 121 exposes the first surface of the semiconductor device 140, the second blind hole 131 exposes the second surface of the semiconductor device 140, the first surface of the semiconductor device 140 is arranged opposite to the second surface of the semiconductor device 140, and the first surface of the semiconductor device 140 is a surface adjacent to the first packaging layer 120. The semiconductor device 140 may be a packaged chip, and illustratively, the semiconductor device 140 may be packaged once using a polymer.

[0054] The semiconductor devices 140 can be connected in parallel through the first conductive structure 124 in the first blind hole 121 and / or the second conductive structure 134 in the second blind hole 131. The semiconductor device 140 can also be electrically connected to an external device through the first conductive structure 124 and the second conductive structure 134. The number of the first blind holes 121 and the number of the second blind holes 131 can be set according to actual needs. The first blind holes 121 and the second blind holes 131 can conduct the heat generated by the semiconductor device 140 to the outside of the circuit board to achieve double-sided heat dissipation.

[0055] The first encapsulation layer 120 and the second encapsulation layer 130 are used to protect the semiconductor device 140 from being contaminated and damaged by foreign substances.

[0056] The present embodiment provides a circuit board, which includes at least one circuit structure unit, and the circuit structure unit includes at least one circuit unit. The circuit unit includes an integrated circuit substrate, a first packaging layer, a second packaging layer and a plurality of semiconductor devices. The integrated circuit substrate includes a plurality of spaced accommodation holes, and the accommodation holes are used to accommodate semiconductor devices. The present embodiment embeds the semiconductor device into the integrated circuit substrate, which can realize the secondary packaging of the semiconductor device, and can also avoid placing the semiconductor device on the surface of the integrated circuit substrate to increase the volume of the circuit board, and can also make the surface of the integrated circuit substrate electrically connected to more other devices, thereby improving the integration of the circuit board. In the present embodiment, the first packaging layer is located on one side of the integrated circuit substrate, and the second packaging layer is located on the side of the integrated circuit substrate away from the first packaging layer. The first packaging layer includes a plurality of first blind holes and a first conductive structure located in each of the first blind holes, and the second packaging layer includes a plurality of second blind holes and a second conductive structure located in each of the second blind holes. External devices can be electrically connected to the semiconductor device through the first conductive structure in the first blind hole and / or the second conductive structure in the second blind hole. Compared with the current connection with semiconductor devices through bonding wires, the blind hole connection method used in this embodiment generates smaller parasitic parameters, and the first blind hole and the second blind hole can conduct the heat generated by the semiconductor device to the outside of the circuit board to achieve double-sided heat dissipation. In summary, the circuit board provided in this example can not only make the circuit board develop in the direction of miniaturization, but also improve the heat dissipation performance of the circuit board, and can also reduce the parasitic parameters generated by the circuit board.

[0057] Optional, Figure 6 is a schematic diagram of the structure of another circuit board provided according to an embodiment of the present invention, referring to Figure 6 The circuit board provided in this embodiment includes at least two circuit structure units 100 and at least one bracket unit 12; the bracket unit 12 is used to connect two adjacent circuit structure units 100, and make the angle between the two connected circuit structure units 100 a set angle.

[0058] Specifically, the number of bracket units 12 can be one less than the number of circuit structure units 100. The angle can be set to be about 90°, specifically 90°, so that multiple circuit structure units 100 can be combined in a three-dimensional manner, thereby improving the integration of the entire circuit board. The angle between two circuit structure units 100 connected by the bracket unit 12 can be understood as: the angle between the first surface and the second surface, wherein the first surface is the surface where one of the two circuit structure units 100 is connected to the bracket unit 12, and the second surface is the surface where the other of the two circuit structure units 100 is connected to the bracket unit 12.

[0059] Optional, continue to refer to Figure 1The circuit structure unit 100 includes at least two stacked circuit units 110 and an interlayer insulating layer 150 located between two adjacent layers of circuit units 110, wherein the circuit units 110 in the same circuit structure unit 100 are electrically connected.

[0060] Specifically, at least two stacked circuit units 110 are provided in a circuit structure unit 100, so that more semiconductor devices 140 can be integrated into the circuit board, thereby improving the integration of the circuit board. Two adjacent layers of circuit units 110 are insulated by an interlayer insulating layer 150, so that short circuits between two adjacent layers of circuit units 110 can be avoided. The circuit units 110 in the same circuit structure unit 100 are electrically connected, so that electrical signals can be transmitted between the circuit units 110, and each circuit unit 110 can also be electrically connected to an external device.

[0061] Optional, continue to refer to Figure 1 The circuit structure unit 100 includes at least one third blind hole 11 and a third conductive structure located in the third blind hole 11; the third blind hole 11 passes through the circuit structure unit 100; and each circuit unit 110 in the same circuit structure unit 100 is electrically connected through the third conductive structure.

[0062] Specifically, the third blind hole 11 can improve the heat dissipation performance of the circuit structure unit 100. The third conductive structure is arranged in the third blind hole 11, and multiple circuit units 110 are electrically connected without bonding wires, thereby further reducing parasitic parameters of the circuit board.

[0063] Continue to refer Figure 1 The circuit structure unit 100 further includes at least one fourth blind hole 10 and a fourth conductive structure located in the fourth blind hole 10. The fourth blind hole 10 can further improve the heat dissipation performance of the circuit board. The fourth conductive structure can be arranged in the fourth blind hole 10 to achieve electrical connection between the circuit units 110. The depth of the fourth blind hole 10 can be less than the depth of the third blind hole. The depth of the fourth blind hole 10 can be set according to actual needs.

[0064] Optional, continue to refer to Figure 2 The first packaging layer 120 also includes a first insulating layer 122 and a first metal layer 123, the first insulating layer 122 is located between the integrated circuit substrate 3 and the first metal layer 123, and the first conductive structure 124 is electrically connected to the first metal layer 123; the second packaging layer 130 also includes a second insulating layer 132 and a second metal layer 133, the second insulating layer 132 is located between the integrated circuit substrate 3 and the second metal layer 133, and the second conductive structure 134 is electrically connected to the second metal layer 133.

[0065] Specifically, the gap between the semiconductor device 140 and the receiving hole 4 may be filled with the material of the first insulating layer 122 and the material of the second insulating layer 132, so as to further fix the position of the semiconductor device 140. The first conductive structure 124 is electrically connected to the first metal layer 123, so that the semiconductor device 140 can be electrically connected to external devices and other semiconductor devices 140. The second conductive structure 134 is electrically connected to the second metal layer 133, so that the semiconductor device 140 can be electrically connected to external devices and other semiconductor devices 140. The first metal layer 123 includes a first metal pattern, and the second metal layer 133 includes a second metal pattern. The first metal pattern and the second metal pattern can be patterned according to actual needs.

[0066] Optional, Figure 7 is a schematic diagram of a top surface structure of a semiconductor device provided according to an embodiment of the present invention, Figure 8 is a schematic diagram of the bottom structure of a semiconductor device provided according to an embodiment of the present invention, with reference to Figure 7 and Figure 8 The semiconductor device includes a packaging film 141 and a chip module; the packaging film 141 wraps the side of the chip module; the chip module includes a chip structure, a first metal electrode layer 142 and a second metal electrode layer 143; the first metal electrode layer 142 is located on the top surface of the chip structure, and the second metal electrode layer 143 is located on the bottom surface of the chip structure.

[0067] Specifically, the material of the packaging film 141 may be a polymer, the material of the first metal electrode layer 142 and the material of the second metal electrode layer 143 may include copper, the first metal electrode layer 142, the chip structure and the second metal electrode layer 143 are stacked in sequence, the first metal electrode layer 142 can be electrically connected to each first conductive structure in the same circuit unit, and the second metal electrode layer 143 can be electrically connected to each second conductive structure in the same circuit unit.

[0068] Optional, continue to refer to Figure 7 and Figure 8 , a shape of a vertical projection of the first metal electrode layer 142 on the chip structure is different from a shape of a vertical projection of the second metal electrode layer 143 on the chip structure.

[0069] Specifically, the shape of the first metal electrode layer 142 is different from the shape of the second metal electrode layer 143, which can facilitate the distinction between the front and back sides of the semiconductor device. Figure 7 and Figure 8 The first metal electrode layer 142 may be a square electrode including four raised rounded corners, and the second metal electrode layer 143 may be a square electrode with a notch. This arrangement can be used to prevent fooling.

[0070] Optionally, the thickness of the semiconductor device ranges from 0.25 mm to 0.35 mm.

[0071] Specifically, the semiconductor device provided in this embodiment is relatively thin, which can reduce the thickness of the circuit board and make the circuit board even thinner.

[0072] Optional, continue to refer to Figure 5 , the integrated circuit substrate includes at least three first alignment holes 11.

[0073] Specifically, the integrated circuit substrate may include four first alignment holes 11. The multiple first alignment holes 11 are arranged in the integrated circuit substrate, so that the semiconductor device can be accurately placed after aligning the multiple first alignment holes 11 during the process of manufacturing the circuit board, and it is also convenient to align the first alignment holes 11 to make multiple second alignment holes in the first packaging layer and multiple third alignment holes in the second packaging layer.

[0074] Optional, Fig. 9 is a schematic diagram of the structure of a first encapsulation layer provided according to an embodiment of the present invention, with reference to Fig. 9 The first packaging layer further includes at least three second alignment holes 10; the second packaging layer further includes at least three third alignment holes.

[0075] Specifically, the first packaging layer may include four second alignment holes 10, and the second packaging layer may include four third alignment holes. The second alignment holes 10 and the third alignment holes may be made by aligning the first alignment holes 11 using X-ray. Providing a plurality of second alignment holes facilitates making the first blind hole by aligning the plurality of second alignment holes 10 in the process of making the circuit board, and also facilitates making the second blind hole by aligning the plurality of third alignment holes in the process of making the circuit board, thereby improving the position accuracy of the first blind hole and the position accuracy of the second blind hole.

[0076] Optionally, the vertical projection of the first alignment hole on the first packaging layer does not completely overlap with the second alignment hole; the vertical projection of the first alignment hole on the second packaging layer does not completely overlap with the third alignment hole. With this arrangement, during the process of manufacturing the circuit board, there is no need to ensure that the size and position of the first alignment hole correspond to the size and position of the second alignment hole, nor is there any need to ensure that the size and position of the first alignment hole correspond to the size and position of the third alignment hole, thereby improving the manufacturing efficiency of the circuit board.

[0077] Optionally, the thickness of the integrated circuit substrate is equal to the thickness of the semiconductor device. This arrangement allows the first surface of the semiconductor device to be flush with the first surface of the integrated circuit substrate, and the second surface of the semiconductor device to be flush with the second surface of the integrated circuit substrate, thereby further reducing the thickness of the circuit board.

[0078] Fig.10is a schematic diagram of the structure of another circuit board provided according to an embodiment of the present invention, referring to Fig.10 The circuit board provided in this embodiment also includes a heat dissipation structure 13; the heat dissipation structure 13 surrounds each circuit structure unit.

[0079] Specifically, the heat dissipation structure 13 includes a heat sink 14 and a connection film 15 connected to each circuit structure unit. A heat sink 14 is provided near each circuit structure unit, and the heat sink 14 can be arranged in a zigzag manner. The heat sink 14 also includes a heat dissipation port 17. The heat dissipation structure 13 adopts a multi-faceted fluid heat sink, which has a better heat dissipation effect and optimizes the reliability and stability of the circuit board during use.

[0080] This embodiment also provides a method for manufacturing a circuit board, and the circuit board manufacturing method is used to manufacture the circuit board provided by any embodiment of the present invention.

[0081] A method for manufacturing a circuit board will be specifically introduced below. The method comprises the following steps:

[0082] S110, manufacturing an integrated circuit substrate.

[0083] The integrated circuit substrate includes a plurality of accommodating holes and a plurality of first alignment holes.

[0084] S120, embedding a plurality of semiconductor devices into the receiving holes of the integrated circuit substrate at the same time.

[0085] S130, placing a first thin prepreg and a first metal foil on one side of an integrated circuit substrate including a plurality of semiconductor devices, placing a second thin prepreg and a second metal foil on the other side of the integrated circuit substrate including a plurality of semiconductor devices, and laminating them using a special lamination procedure.

[0086] Fig.11 is a schematic diagram of a circuit board manufacturing process according to an embodiment of the present invention, with reference to Fig.11 , Fig.11 The structure shown is the structure formed after step S130, which includes a first metal foil 1, a first thin prepreg 2, an integrated circuit substrate 3 including a plurality of semiconductor devices 140, a second thin prepreg 5 and a second metal foil 6 stacked in sequence.

[0087] S140, making a plurality of second alignment holes in the first thin prepreg and the first metal foil through the first alignment holes, and making a plurality of third alignment holes in the second thin prepreg and the second metal foil through the first alignment holes.

[0088] S150, manufacturing a first blind hole by aligning the second alignment hole, and manufacturing a second blind hole by aligning the third alignment hole.

[0089] S160, manufacturing a first conductive structure in each first blind hole, manufacturing a second conductive structure in each second blind hole, patterning the first metal foil to form a first metal layer, and patterning the second metal foil to form a second metal layer, thereby manufacturing a circuit unit.

[0090] S170, stacking a plurality of circuit units, and placing an interlayer insulating layer between two adjacent circuit units for lamination.

[0091] S180 , manufacturing a third through hole and a third conductive structure in the third through hole to form a circuit structure unit.

[0092] S190, combining a plurality of circuit structure units through a bracket unit, and connecting them with a heat dissipation structure, thereby forming a circuit board.

[0093] It should be noted that the first thin prepreg after treatment is the first insulating layer, and the second thin prepreg after treatment is the second insulating layer.

[0094] This embodiment also provides an electronic device, which includes the circuit board provided by any embodiment of the present invention.

[0095] The electronic device provided by this embodiment can be developed in the direction of miniaturization, and also has stronger heat dissipation performance and fewer parasitic parameters.

[0096] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0097] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A circuit board, characterized in that: include: At least one circuit structure unit; the circuit structure unit includes at least one circuit unit; The circuit unit includes an integrated circuit substrate, a first packaging layer, a second packaging layer and a plurality of semiconductor devices; The integrated circuit substrate comprises a plurality of spaced-apart accommodation holes, and each of the semiconductor devices is located in a corresponding accommodation hole; The first packaging layer is located on one side of the integrated circuit substrate, and the second packaging layer is located on a side of the integrated circuit substrate away from the first packaging layer; The first packaging layer comprises a plurality of first blind holes and a first conductive structure located in each of the first blind holes; the second packaging layer comprises a plurality of second blind holes and a second conductive structure located in each of the second blind holes; The vertical projection of the first blind hole on the integrated circuit substrate is located within the vertical projection of the semiconductor device on the integrated circuit substrate, and the vertical projection of the second blind hole on the integrated circuit substrate is located within the vertical projection of the semiconductor device on the integrated circuit substrate; Each of the first conductive structures and each of the second conductive structures are electrically connected to the semiconductor device.

2. The circuit board according to claim 1, characterized in that: comprising at least two of the circuit structure units and at least one bracket unit; The bracket unit is used to connect two adjacent circuit structure units, and make the angle between the two connected circuit structure units be a set angle.

3. The circuit board according to claim 1, characterized in that: The circuit structure unit includes at least two stacked circuit units and an interlayer insulating layer between two adjacent layers of the circuit units, wherein the circuit units in the same circuit structure unit are electrically connected.

4. The circuit board according to claim 3, characterized in that: The circuit structure unit comprises at least one third blind hole and a third conductive structure located in the third blind hole; The third blind hole passes through the circuit structure unit; The circuit units in the same circuit structure unit are electrically connected via the third conductive structure.

5. The circuit board according to claim 1, characterized in that: The first packaging layer further includes a first insulating layer and a first metal layer, the first insulating layer is located between the integrated circuit substrate and the first metal layer, and the first conductive structure is electrically connected to the first metal layer; The second packaging layer further includes a second insulating layer and a second metal layer, the second insulating layer is located between the integrated circuit substrate and the second metal layer, and the second conductive structure is electrically connected to the second metal layer.

6. The circuit board according to claim 1, characterized in that: The semiconductor device comprises a packaging film and a chip module; The packaging film wraps the side surface of the chip module; The chip module includes a chip structure, a first metal electrode layer and a second metal electrode layer; The first metal electrode layer is located on the top surface of the chip structure, and the second metal electrode layer is located on the bottom surface of the chip structure.

7. The circuit board according to claim 6, characterized in that: A shape of a vertical projection of the first metal electrode layer on the chip structure is different from a shape of a vertical projection of the second metal electrode layer on the chip structure.

8. The circuit board according to claim 1, characterized in that: The thickness of the semiconductor device ranges from 0.25 mm to 0.35 mm.

9. The circuit board according to claim 1, characterized in that: The integrated circuit substrate comprises at least three first alignment holes; The first packaging layer further includes at least three second alignment holes; The second packaging layer further includes at least three third alignment holes; The vertical projection of the first alignment hole on the first packaging layer does not completely overlap with the second alignment hole; A vertical projection of the first alignment hole on the second packaging layer does not completely overlap with the third alignment hole.

10. The circuit board according to claim 1, characterized in that: Also includes a heat dissipation structure; The heat dissipation structure surrounds each of the circuit structure units.

11. A method for manufacturing a circuit board, characterized in that: The method for manufacturing a circuit board manufactures the circuit board according to any one of claims 1 to 10.

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