Printed wiring board

Abstract

Provided is a printed wiring board with improved quality. A printed wiring board (2) according to an embodiment includes: a first conductor layer (10); a resin insulating layer (20) that has a first surface (22) and a second surface (24) on the opposite side to the first surface, is formed on the first conductor layer such that the second surface faces the first conductor layer, and has a via hole (26) that exposes the first conductor layer; a second conductor layer (30) formed on the first surface of the resin insulating layer; and a via hole conductor (40) which is formed in the via hole, penetrates through the resin insulating layer, and connects the first conductor layer and the second conductor layer, and an inner wall surface (27) of the via hole has: a first inclined surface (27A) which decreases in diameter from the first surface side to an intermediate portion in the thickness direction of the resin insulating layer; a second inclined surface (27B) having a diameter smaller than that of an end portion of the first inclined surface on the intermediate portion side, the second inclined surface decreasing in diameter from the intermediate portion to the second surface side; and a step surface (27C) which is continuous with the first inclined surface and the second inclined surface.

Description

Technical Field

[0001] The technology of the present invention relates to a printed wiring board. Background Art

[0002] Patent document 1 describes a multilayer printed wiring board in which interlayer resin insulating layers and conductor circuits are alternately stacked, and the conductor circuits of the upper layer and the conductor circuits of the lower layer are connected via via holes. The via holes described in Patent document 1 are shaped to decrease in diameter from the conductor circuit of the upper layer toward the conductor circuit of the lower layer.

[0003] Patent Document 1: Japanese Patent Application Publication No. 2009-302588

[0004] It is desired that the via-hole conductor formed in the via hole of the resin insulating layer has improved connectivity with the conductor layer. Summary of the invention

[0005] The printed wiring board of the present invention comprises: a first conductor layer; a resin insulating layer, which has a first surface and a second surface on the side opposite to the first surface, and is formed on the first conductor layer in a manner that the second surface is opposite to the first conductor layer, and the resin insulating layer has a via hole that exposes the first conductor layer; a second conductor layer, which is formed on the first surface of the resin insulating layer; and a via conductor, which is formed in the via hole, penetrates the resin insulating layer, and connects the first conductor layer with the second conductor layer, wherein the inner wall surface of the via hole comprises: a first inclined surface, which decreases in diameter from the first surface side to the middle part side in the thickness direction of the resin insulating layer; a second inclined surface, whose diameter is smaller than the diameter of the end portion of the middle part side of the first inclined surface, and the second inclined surface decreases in diameter from the middle part side to the second surface side; and a step surface, which is continuous with the first inclined surface and the second inclined surface.

[0006] According to the embodiment of the present invention, the via-hole conductor can improve the connectivity with the conductor layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 It is a cross-sectional view showing a printed wiring board according to a first embodiment of the present invention.

[0008] Figure 2A It is a cross-sectional view showing a part of the printed wiring board according to the first embodiment of the present invention in an enlarged manner.

[0009] Figure 2B It is a cross-sectional view showing a part of the printed wiring board according to the first embodiment of the present invention in an enlarged manner.

[0010] Figure 2C This is a partially enlarged cross-sectional photograph showing a printed wiring board according to the first embodiment of the present invention.

[0011] Figure 3AIt is a cross-sectional view showing an example of the manufacturing process of the printed wiring board according to the first embodiment of the present invention.

[0012] Figure 3B It is a cross-sectional view showing an example of the manufacturing process of the printed wiring board according to the first embodiment of the present invention.

[0013] Figure 3C It is a cross-sectional view showing an example of the manufacturing process of the printed wiring board according to the first embodiment of the present invention.

[0014] Figure 3D It is a cross-sectional view showing an example of the manufacturing process of the printed wiring board according to the first embodiment of the present invention.

[0015] Figure 3E It is a cross-sectional view showing an example of the manufacturing process of the printed wiring board according to the first embodiment of the present invention.

[0016] Figure 3F It is a cross-sectional view showing an example of the manufacturing process of the printed wiring board according to the first embodiment of the present invention.

[0017] Figure 3G It is a cross-sectional view showing an example of the manufacturing process of the printed wiring board according to the first embodiment of the present invention.

[0018] Figure 3H It is a cross-sectional view showing an example of the manufacturing process of the printed wiring board according to the first embodiment of the present invention.

[0019] Fig. 3I It is a cross-sectional view showing an example of the manufacturing process of the printed wiring board according to the first embodiment of the present invention.

[0020] Description of symbols

[0021] 2: printed wiring board; 4: insulating layer; 6: third surface; 8: fourth surface; 10: first conductor layer; 10a: seed layer; 10b: electroplating layer; 12: signal wiring; 14: pad; 20: resin insulating layer; 22: first surface; 24: second surface; 26: via; 27: inner wall surface; 27A: first inclined surface; 27B: second inclined surface; 27C: step surface; 30: second conductor layer; 30a: seed layer; 30b: electroplating layer; 31a: first seed layer; 31b: second seed layer; 32: first signal wiring; 34: second signal wiring; 35: coating layer; 36: pad; 40: via conductor; 40B: bottom; 50: protective film; 60: anti-etching agent; 80: resin; 90: inorganic particles; 100: adhesive layer; θ1: first tilt angle; θ2: second tilt angle. DETAILED DESCRIPTION

[0022] Hereinafter, an example of an embodiment of the present invention will be described in detail with reference to the drawings.

[0023] The structural elements represented by the same reference numerals in the drawings refer to the same or identical structural elements. In the embodiments described below, repeated descriptions and reference numerals are sometimes omitted. The drawings used in the following descriptions are all schematic. The relationship between the dimensions of the elements shown in the drawings, the ratio of the elements, etc. are not necessarily consistent with reality. The relationship between the dimensions of the elements, the ratio of the elements, etc. are not necessarily consistent between multiple drawings.

[0024] Figure 1 It is a cross-sectional view showing a printed wiring board 2 according to the embodiment. Figure 2A as well as Figure 2B 2 is an enlarged cross-sectional view showing a portion of the printed wiring board 2 according to the embodiment. Figure 1 As shown, the printed wiring board 2 includes an insulating layer 4 , a first conductor layer 10 , a resin insulating layer 20 , a second conductor layer 30 , and a via conductor 40 .

[0025] The insulating layer 4 is formed of resin. The insulating layer 4 may also contain inorganic particles such as silicon dioxide. The insulating layer 4 may also contain reinforcing materials such as glass cloth. The insulating layer 4 has a third surface 6 (upper surface in the figure) and a fourth surface 8 (lower surface in the figure) opposite to the third surface 6.

[0026] The first conductor layer 10 is formed on the third surface 6 of the insulating layer 4. The first conductor layer 10 includes a signal wiring 12 and a pad 14. The first conductor layer 10 may also include a conductor circuit different from the signal wiring 12 and the pad 14. The first conductor layer 10 is mainly formed of copper. The first conductor layer 10 is formed by a seed layer 10a on the insulating layer 4 and a plating layer 10b on the seed layer 10a. The seed layer 10a is formed by a first layer 11a on the third surface 6 and a second layer 11b on the first layer 11a. The first layer 11a is formed of an alloy (copper alloy) containing copper, silicon and aluminum. The second layer 11b is formed of copper. The plating layer 10b is formed of copper. The first layer 11a is in contact with the insulating layer 4.

[0027] In the first conductor layer 10, the portion other than the portion in contact with the third surface 6 of the insulating layer 4 is the surface of the first conductor layer 10. The surface of the first conductor layer 10 includes a first surface and a second surface. The first surface is a surface exposed from the via 26 of the resin insulating layer 20. The second surface is a portion other than the first surface of the surface of the first conductor layer 10. The first surface is not covered by the adhesive layer 100. The second surface is a portion covered by the adhesive layer 100. The adhesive layer 100 is formed of a nitrogen-based organic compound. The nitrogen-based organic compound forming the adhesive layer 100 is, for example, a tetrazole compound. The nitrogen-based organic compound may be a tetrazole compound disclosed in Japanese Patent Publication No. 2015-54987. The adhesive layer 100 covers the second surface of the first conductor layer 10, but does not cover the third surface 6 exposed from the first conductor layer 10.

[0028] The resin insulating layer 20 is formed on the third surface 6 of the insulating layer 4 and the first conductor layer 10. The resin insulating layer 20 is formed with the first conductor layer 10 interposed therebetween with the adhesive layer 100. The resin insulating layer 20 has a first surface 22 (upper surface in the figure) and a second surface 24 (lower surface in the figure) on the opposite side to the first surface 22. The first conductor layer 10 enters the inner side of the second surface 24 of the resin insulating layer 20. The second surface 24 of the resin insulating layer 20 is opposed to the first conductor layer 10 through the portion in contact with the upper surface and the side surface of the first conductor layer 10 in the figure. The resin insulating layer 20 includes a resin 80 and a plurality of inorganic particles 90. For example, a thermosetting resin or a photocurable resin can be used for the resin 80. As an example, an epoxy resin can also be used for the resin 80. A plurality of inorganic particles 90 are dispersed in the resin 80. For example, silicon dioxide or aluminum oxide can be used for the inorganic particles 90. The particle size of inorganic particles 90 is, for example, 0.5 μm on average and in a range of 0.1 μm to 5.0 μm. Resin insulating layer 20 has vias 26 as through holes penetrating in the thickness direction. Inner wall surface 27 of via 26 is formed by resin 80 and inorganic particles 90 .

[0029] like Figure 2A As shown, the first surface 22 of the resin insulating layer 20 is formed only by the resin 80. The inorganic particles 90 are not exposed from the first surface 22. Specifically, the first surface 22 does not include the surface of the inorganic particles 90. No concavities and convexities are formed on the first surface 22 of the resin insulating layer 20. The first surface 22 is not roughened. The first surface 22 is formed smoothly. The arithmetic mean roughness (Ra) of the first surface 22 is, for example, not less than 0.02 μm and not more than 0.06 μm.

[0030] On the other hand, Figure 2B As shown, a portion of the inorganic particles 90 are exposed on the inner wall surface 27 of the via hole 26. The inner wall surface 27 of the via hole 26 includes the surface of the inorganic particles 90. The inner wall surface 27 of the via hole 26 has projections and depressions. The inner wall surface 27 of the via hole 26 is formed by the exposed surface of the resin 80 and the exposed surface of the inorganic particles 90. The inner wall surface 27 of the via hole 26 is a non-roughened surface and is not roughened. The arithmetic mean roughness (Ra) of the inner wall surface 27 of the via hole 26 is, for example, in the range of 0.005 μm or more and 0.1 μm or less.

[0031] The thickness of the resin insulating layer 20 is at least twice the thickness of the second conductor layer 30. The thickness T of the resin insulating layer 20 is the distance between the first surface 22 and the upper surface of the first conductor layer 10. In the resin insulating layer 20, the range where the thickness from the first surface 22 is 20% to 80% of the thickness T is the middle portion 20M in the thickness direction of the resin insulating layer 20.

[0032] like Figure 2B as well as Figure 2C As shown, the inner wall surface 27 of the via 26 includes a first slope 27A, a second slope 27B and a step surface 27C. In the first slope 27A, the inner wall surface 27 of the via 26 decreases in diameter from the first surface 22 side to the middle portion 20M. The end (the lower end in the figure) on the middle portion 20M side of the thickness direction of the resin insulation layer 20 in the first slope 27A is the end 27D. The end 27D is the part with the smallest diameter in the first slope 27A. The diameter of the second slope 27B is smaller than the diameter of the end 27D. That is, the overall diameter of the second slope 27B is smaller than the diameter of the first slope 27A. Compared with a structure without the second slope 27B, for example, the first slope 27A reaches the pad 14, the bottom of the via 26 is reduced in diameter. The bottom 40B of the via conductor 40 is also reduced in diameter. The diameter here does not necessarily refer to the diameter of the circular cross section of the via 26 parallel to the upper surface of the first conductor layer 10, but also includes Figure 1 The width of the via 26 in the cross section shown.

[0033] In the second inclined surface 27B, the inner wall surface 27 of the via 26 is reduced in diameter from the middle portion 20M to the second surface 24 side (the pad 14 side). The step surface 27C is a surface continuous with the first inclined surface 27A and the second inclined surface 27B. The step surface 27C is a step relative to the first inclined surface 27A and the second inclined surface 27B. The step surface 27C is located at the upper and lower positions of the range of the middle portion 20M.

[0034] Figure 2B It is a cross section including the center line CL of the via hole 26. In this cross section, the second inclined surface 27B is inclined relative to the upper surface of the first conductor layer 10. The first inclined surface 27A is inclined relative to the parallel plane PL parallel to the upper surface of the first conductor layer 10. In essence, the first inclined surface 27A is also inclined relative to the upper surface of the first conductor layer 10. The inclination angle of the first inclined surface 27A relative to the parallel plane PL is set to a first inclination angle θ1. The inclination angle of the second inclined surface 27B relative to the upper surface of the first conductor layer 10 is set to a second inclination angle θ2. The second inclination angle θ2 is greater than the first inclination angle θ1. The first inclination angle θ1 is, for example, greater than 75 degrees and less than 85 degrees. The second inclination angle θ2 is, for example, greater than 85 degrees and less than 89 degrees.

[0035] The second slope angle θ2 of the second slope 27B is larger than the slope angle θ1 of the first slope 27A. Compared with the structure where the second slope angle θ2 of the second slope 27B is equal to or smaller than the first slope angle θ1 of the first slope 27A, the bottom 26B of the via 26 is enlarged. The bottom 40B of the via conductor 40 is also enlarged.

[0036] exist Figure 2BIn the cross section shown, the step surface 27C is parallel to the upper surface of the first conductor layer 10. The step surface 27C may also be inclined relative to the upper surface of the first conductor layer 10. The inclination angle of the step surface 27C relative to the upper surface of the first conductor layer 10 is set to a third inclination angle. The third inclination angle is, for example, greater than 5 degrees and less than 30 degrees. When the third inclination angle is a positive value, the step surface 27C is inclined in the same direction as the first inclined surface 27A and the second inclined surface 27B. When the third inclination angle is a negative value, the step surface 27C is inclined in the opposite direction to the first inclined surface 27A and the second inclined surface 27B. When the third inclination angle θ3 is zero, the step surface 27C is parallel to the upper surface of the first conductor layer 10.

[0037] Compared with a structure in which the second slope 27B is continuous from the end 27D of the first slope 27A without the step surface 27C, the bottom of the via hole 26 is reduced in diameter. The bottom 40B of the via-hole conductor 40 is also reduced in diameter.

[0038] The inner wall surface 27 of the via hole 26 has a first slope 27A, a second slope 27B, and a step surface 27C. The second slope angle θ2 of the second slope 27B is greater than the first slope angle θ1 of the first slope 27A. Thus, the size of the bottom 40B of the via conductor 40 is optimized.

[0039] like Figure 1 As shown, the second conductor layer 30 is formed on the first surface 22 of the resin insulation layer 20. The second conductor layer 30 includes a first signal wiring 32, a second signal wiring 34 and a pad 36. The second conductor layer 30 may also include a conductor circuit different from the first signal wiring 32, the second signal wiring 34 and the pad 36. The first signal wiring 32 and the second signal wiring 34 form a pair of wirings. The second conductor layer 30 is mainly formed of copper. The second conductor layer 30 is formed by a seed layer 30a on the first surface 22 and a plating layer 30b on the seed layer 30a. The seed layer 30a is formed by a first seed layer 31a on the first surface 22 and a second seed layer 31b on the first seed layer 31a. The first seed layer 31a is formed of an alloy (copper alloy) containing copper, silicon and aluminum. The second seed layer 31b is formed of copper. The plating layer 30b is formed of copper. The first seed layer 31a is in contact with the first surface 22. The second seed layer 31b is bonded to the plating layer 30b. The surface of the second conductor layer 30 facing the first surface 22 of the resin insulating layer 20 is formed along the surface shape of the first surface 22. The second conductor layer 30 does not penetrate into the inside of the first surface 22 of the resin insulating layer 20.

[0040] The via conductor 40 is formed in the via hole 26. The via conductor 40 connects the first conductor layer 10 and the second conductor layer 30 adjacent in the stacking direction. The stacking direction refers to the direction in which the layers are stacked, and is the same direction as the thickness direction of each layer. In this embodiment, the stacking direction is the same as the up-down direction. Figure 1 In the embodiment, the via conductor 40 connects the pad 14 and the land 36. The via conductor 40 is formed by the seed layer 30a and the plating layer 30b on the seed layer 30a. The seed layer 30a forming the via conductor 40 is common to the seed layer 30a forming the second conductor layer 30. The first seed layer 31a is in contact with the inner wall surface 27.

[0041] The coating layer 35 is formed on the surfaces of the resin insulating layer 20 and the second conductor layer 30. The coating layer 35 improves the adhesion between the resin insulating layer 20 and the second conductor layer 30 and other layers stacked on the resin insulating layer 20 and the second conductor layer 30. The coating layer 35 may not be provided.

[0042] [Method for Manufacturing Printed Wiring Board 2 According to Embodiment]

[0043] Figure 3A to Figure 3I A method for manufacturing the printed wiring board 2 according to the embodiment will be described. Figure 3A to Figure 3I It is a cross-sectional view. Figure 3A The first conductor layer 10 and the adhesive layer 100 are shown. The first conductor layer 10 is formed on the insulating layer 4 and the third surface 6 of the insulating layer 4. The adhesive layer 100 covers the surface of the first conductor layer 10. The first conductor layer 10 is formed by a semi-additive method. The adhesive layer 100 is formed by immersing the insulating layer 4 and the first conductor layer 10 in a chemical solution containing a nitrogen-based organic compound. Alternatively, the adhesive layer 100 is formed by applying the above chemical solution on the first conductor layer 10.

[0044] like Figure 3B As shown, a resin insulating layer 20 and a protective film 50 are formed on the insulating layer 4 and the first conductive layer 10 covered by the adhesive layer 100. The second surface 24 of the resin insulating layer 20 is opposite to the third surface 6 of the insulating layer 4. The protective film 50 is formed on the first surface 22 of the resin insulating layer 20. The resin insulating layer 20 has a resin 80 and inorganic particles 90. The inorganic particles 90 are buried in the resin 80. The first surface 22 of the resin insulating layer 20 is formed only by the resin 80. The inorganic particles 90 are not exposed from the first surface 22. The first surface 22 does not include the surface of the inorganic particles 90. No concavo-convex is formed on the first surface 22 of the resin insulating layer 20.

[0045] The protective film 50 completely covers the first surface 22 of the resin insulating layer 20. The protective film 50 is, for example, a film made of polyethylene terephthalate (PET). A layer made of a release agent is formed between the protective film 50 and the resin insulating layer 20.

[0046] like Figure 3C As shown, laser light L is irradiated from above the protective film 50. The laser light L penetrates through the protective film 50 and the resin insulating layer 20 at the same time. A via hole 26 for a via conductor that reaches the adhesive layer 100 covering the pad 14 is formed. The laser light L is, for example, a UV laser or a CO2 laser. The via hole 26 has an inner wall surface 27C ( Figure 3D ).

[0047] The adhesive layer 100 is not completely removed by the laser light L. The adhesive layer 100 covering the pad 14 is exposed through the via hole 26. When the via hole 26 is formed, the first surface 22 of the resin insulating layer 20 is covered by the protective film 50. Therefore, when the via hole 26 is formed, even if the resin is scattered, it is possible to suppress the resin from being attached to the first surface 22. The inner wall surface 27 of the via hole 26 after laser irradiation is formed by the resin 80 and the inorganic particles 90 protruding from the resin 80.

[0048] like Figure 3D As shown, the inside of the via 26 is cleaned. By cleaning the inside of the via 26, the adhesive layer 100 exposed from the via 26 is removed. The pad 14 is exposed from the via 26. The resin residue generated when the via 26 is formed is removed. The cleaning inside the via 26 is performed using plasma P. That is, the cleaning is performed by a dry process. The gas type of the dry process is a mixed gas of a halogen gas (fluorine gas, chlorine gas, etc.) and O2 gas, or a single gas of a halogen gas (fluorine gas, chlorine gas, etc.) and O2 gas. The cleaning includes a desmear treatment. The adhesive layer 100 formed between the second surface 24 of the resin insulating layer 20 and the pad 14 is not removed. Therefore, no gap is formed between the second surface 24 of the resin insulating layer 20 and the pad 14.

[0049] The resin 80 is selectively removed by the plasma P. The plasma P removes the resin 80 faster than the inorganic particles 90. By cleaning the inside of the via hole 26, the inorganic particles 90 are exposed on the inner wall surface 27 of the via hole 26 ( Figure 3C ). The inner wall surface 27 of the via hole 26 includes the surface of the inorganic particles 90. Concavities and convexities are formed on the inner wall surface 27 of the via hole 26. On the other hand, the first surface 22 of the resin insulating layer 20 is covered with the protective film 50. The first surface 22 is not affected by the plasma P. The first surface 22 is formed only by the resin 80. The inorganic particles 90 are not exposed from the first surface 22. The first surface 22 does not include the surface of the inorganic particles 90. Concavities and convexities are not formed on the first surface 22 of the resin insulating layer 20. The first surface 22 is smoothly formed.

[0050] like Figure 3EAs shown, after cleaning the inside of the via hole 26, the protective film 50 is removed from the resin insulating layer 20. After removing the protective film 50, the first surface 22 of the resin insulating layer 20 is not roughened. The first surface 22 is formed smoothly. The arithmetic mean roughness (Ra) of the first surface 22 is, for example, 0.02 μm or more and 0.06 μm or less.

[0051] like Figure 3F As shown, a seed layer 30a is formed on the first surface 22 and the inner wall surface 27 of the resin insulating layer 20. The seed layer 30a is formed by sputtering. The seed layer 30a is a sputtered film. The formation of the seed layer 30a is performed by a dry process. A first seed layer 31a is formed on the first surface 22 by sputtering. At the same time, a first seed layer 31a is formed on the inner wall surface 27 and the pad 14 exposed from the via 26 by sputtering. Then, a second seed layer 31b is formed on the first seed layer 31a by sputtering. The first seed layer 31a and the second seed layer 31b are composed of a combination of copper alloys of different materials, or a combination of a copper alloy and copper. The first seed layer 31a is formed of a copper alloy. The adhesion of the combination of the copper alloy and the resin insulating layer 20 is higher than the adhesion of the combination of copper and the resin insulating layer 20. The second seed layer 31b is formed of a copper alloy or copper. The copper alloy of the first seed layer 31a and the second seed layer 31b is formed so that the copper content is 90% or more of the total weight. The higher the copper content, the lower the resistance can be, so the connection reliability is improved. The seed layer 30a is also formed on the upper surface of the pad 14 exposed from the via 26 and the inner wall surface 27 of the via 26. The first seed layer 31a is formed of an alloy containing copper, silicon and aluminum. The second seed layer 31b is formed of copper.

[0052] like Figure 3G As shown in FIG. 1 , a plating resist 60 is formed on the seed layer 30a. Since the first surface 22 of the resin insulating layer 20 is not roughened, the seed layer 30a can be formed as a low-roughness surface with a uniform thickness. The plating resist 60 can be closely attached to the seed layer 30a without a gap, so that the plating resist 60 can be prevented from peeling off, and short circuits between wirings can be suppressed by electroplating. The plating resist 60 has a structure for forming the first signal wiring 32, the second signal wiring 34, and the pad 36 (see FIG. 1 ). Figure 1 ) opening.

[0053] like Figure 3HAs shown, the electroplating layer 30b is formed on the seed layer 30a exposed from the plating resist 60. The electroplating layer 30b is formed of copper. The electroplating layer 30b fills the via 26. When the third inclination angle θ3 of the step surface 27C is zero or a positive value, the electroplating layer 30b is easy to fill the via 26 without a gap. The first signal wiring 32, the second signal wiring 34 and the pad 36 are formed by the seed layer 30a and the electroplating layer 30b on the first surface 22. The second conductor layer 30 is formed. The via conductor 40 is formed by the seed layer 30a and the electroplating layer 30b in the via 26. The second conductor layer 30 and the via conductor 40 are formed at the same time. The via conductor 40 connects the pad 14 to the pad 36. The first signal wiring 32 and the second signal wiring 34 form a pair of wirings.

[0054] like Fig. 3I As shown, the plating resist 60 is removed. The seed layer 30a exposed from the electroplating layer 30b is removed. The seed layer 30a on the surface of the second conductor layer 30 is removed by an etching solution, and the arithmetic mean roughness (Ra) is adjusted to a range of 0.02 μm or more and 0.5 μm or less. The first conductor layer 10 having a rough surface can reduce transmission loss. The second conductor layer 30 and the via conductor 40 are formed at the same time.

[0055] Thereafter, the first surface 22 of the resin insulating layer 20 is subjected to an O 2 ashing process as required. In the O 2 ashing process, the first surface 22 of the resin insulating layer 20 is irradiated with O 2 plasma.

[0056] After that, the second conductor layer 30 is further subjected to a chemical conversion treatment. For example, a coating layer 35 is formed on the surface of the resin insulating layer 20 and the second conductor layer 30. The printed wiring board 2 of the embodiment is obtained (see Figure 1 ).

[0057] In the printed wiring board 2 of the embodiment (see Figure 1 to Figure 2B ), the inner wall surface 27 of the via hole 26 has a first inclined surface 27A and a second inclined surface 27B. Compared with a structure in which the first inclined surface 27A reaches the pad 14 without the second inclined surface 27B, the bottom 40B of the via conductor 40 is reduced in diameter. In the structure in which the pad 14 is miniaturized, even if the position of the via conductor 40 is offset, it is possible to suppress the bottom 40B of the via conductor 40 from extending laterally relative to the upper surface of the pad 14. The bottom 40B of the via conductor 40 does not extend from the upper surface of the pad 14, thereby improving the connectivity of the via conductor 40 with respect to the pad 14. The pad 14 can be arranged at a high density by miniaturization.

[0058] In the printed wiring board 2 of the embodiment (see Figure 1 to Figure 2B), the second inclination angle θ2 of the second inclined surface 27B is larger than the inclination angle θ1 of the first inclined surface 27A. When the bottom 40B of the via-hole conductor 40 is set constant, the upper portion of the second inclined surface 27B has a small diameter compared to the structure in which the second inclination angle θ2 of the second inclined surface 27B is greater than the first inclination angle θ1 of the first inclined surface 27A. By making the upper portion of the second inclined surface 27 have a small diameter, the volume of the space of the second inclined surface 27B in the via 26 is reduced, so that the via 26 is easily filled by plating.

[0059] In the printed wiring board 2 of the embodiment (see Figure 1 to Figure 2B ), the inner wall surface 27 of the via 26 is formed by a resin 80 and inorganic particles 90. The inner wall surface 27 is not roughened and is a non-roughened surface. Since the inner wall surface 27 is a non-roughened surface, the surface of the seed layer 30a becomes smooth. As a result, the filling property of the electroplating layer 30b is improved. The formation of stress concentration sites (as an example, concave-convex portions) in the electroplating layer 30b constituting the inner layer of the via conductor 40 is suppressed. As a result, the generation of cracks in the electroplating layer 30b as the inner layer of the via conductor 40 can be suppressed. Moreover, since the inner wall surface 27 is a non-roughened surface, the generation of gaps between the inner wall surface 27 and the via conductor 40 can be suppressed.

[0060] In the printed wiring board 2 of the embodiment (see Figure 1 ), the first surface 22 of the resin insulating layer 20 is formed by the resin 80. The inorganic particles 90 are not exposed on the first surface 22. No bumps and depressions are formed on the first surface 22. The standard deviation of the relative dielectric constant of the portion near the first surface 22 of the resin insulating layer 20 is suppressed from becoming larger. The relative dielectric constant of the first surface 22 does not change significantly depending on the position. Even if the first signal wiring 32 and the second signal wiring 34 are in contact with the first surface 22, the difference in propagation speed of the electric signal between the first signal wiring 32 and the second signal wiring 34 can be reduced. Therefore, noise is suppressed in the printed wiring board 2 of the embodiment. Even if a logic IC is installed on the printed wiring board 2 of the embodiment, the data transmitted by the first signal wiring 32 and the data transmitted by the second signal wiring reach the logic IC almost without delay. It is possible to suppress malfunction of the logic IC. Even if the length of the first signal wiring 32 and the length of the second signal wiring 34 are 5 mm or more, the difference in propagation speed between the two can be reduced. Even if the length of the first signal wiring 32 and the length of the second signal wiring 34 are 10 mm or more and 20 mm or less, it is possible to suppress malfunction of the logic IC. A printed wiring board 2 having high quality is provided.

[0061] In the printed wiring board 2 of the embodiment (see Figure 1), the thickness T of the resin insulating layer 20 is more than twice the thickness of the second conductor layer 30. It is considered that when the printed wiring board 2 is subjected to a thermal cycle, the stress applied between the inner wall surface 27 of the via 26 and the via conductor 40 is greater than the stress applied between the first surface 22 and the second conductor layer 30. In addition, if the inorganic particles 90 are present on the inner wall surface 27 of the via 26, the adhesion strength between the inner wall surface 27 of the via 26 and the via conductor 40 may be reduced. However, by having the base layer 33, the reduction in the adhesion strength between the inner wall surface 27 of the via 26 and the via conductor 40 can be suppressed. The via conductor 40 is difficult to peel off from the resin insulating layer 20.

[0062] In the printed wiring board 2 of the embodiment, the seed layer 30a is formed by sputtering (see Figure 3E ). The particles forming the seed layer 30a collide with the first surface 22 perpendicularly. Therefore, the adhesion strength between the first surface 22 and the seed layer 30a is high. On the other hand, the particles forming the seed layer 30a collide with the inner wall surface 27 of the via 26 obliquely. However, the inner wall surface 27 of the via 26 has unevenness. Therefore, the adhesion strength between the seed layer 30a and the inner wall surface 27 of the via 26 is high. Even if the first surface 22 does not have unevenness and the inner wall surface 27 of the via 26 has unevenness, the difference between the adhesion strength between the second conductor layer 30 and the first surface 22 and the adhesion strength between the via conductor 40 and the inner wall surface 27 of the via 26 can be reduced. Stress is difficult to concentrate on the interface between the second conductor layer 30 and the first surface 22. Stress is difficult to concentrate on the interface between the via conductor 40 and the inner wall surface 27 of the via 26. Even if the printed wiring board 2 is subjected to a thermal cycle, the via conductor 40 is difficult to peel off from the resin insulation layer 20. A printed wiring board 2 having high quality is provided.

[0063] In the technology of the present invention, the first seed layer 31a of the seed layer 30a is formed of copper and a second element. The second element is selected from silicon, aluminum, titanium, nickel, chromium, carbon, oxygen, tin, calcium, magnesium, iron, molybdenum, and silver. The first seed layer 31a is formed of an alloy containing copper. The second seed layer 31b is formed of copper. The amount of copper (atomic weight %) forming the second seed layer 31b is 99.9% or more. 99.95% or more is preferred.

[0064] The first seed layer 31 a of the seed layer 30 a may be formed of any one of metals selected from silicon, aluminum, titanium, nickel, chromium, carbon, oxygen, tin, calcium, magnesium, iron, molybdenum, and silver.

[0065] In the printed wiring board 2 of the present invention, the resin insulating layer 20 contains the resin 80 and the inorganic particles 90, but may contain a fiber reinforcement material. As the fiber reinforcement material, for example, glass cloth, glass nonwoven fabric, or aramid nonwoven fabric may be used.

[0066] In the printed wiring board 2 of the technique of the present invention, the resin insulating layer is one layer, but two or more layers may be laminated.

[0067] The printed wiring board of the technology of the present invention is not limited to the structures illustrated in the drawings and the structures, shapes and materials illustrated in this specification. As described above, the printed wiring board of the embodiment can have any stacked structure. For example, the wiring substrate of the embodiment can also be a coreless substrate that does not include a core substrate. The printed wiring board of the embodiment can include any number of conductor layers and insulating layers.

[0068] The method for manufacturing a printed wiring board of the present invention is not limited to the method described with reference to the drawings. For example, each insulating layer is not limited to a film-shaped resin, and can be formed using a resin in any form. In the method for manufacturing a printed wiring board of the embodiment, any additional steps can be added to the above steps, and some of the above steps can be omitted.

Claims

1. A printed wiring board comprising: a first conductor layer; a resin insulating layer having a first surface and a second surface opposite to the first surface, formed on the first conductor layer in such a manner that the second surface faces the first conductor layer, and having a via hole for exposing the first conductor layer; a second conductor layer formed on the first surface of the resin insulating layer; as well as a via conductor formed in the via hole, penetrating the resin insulating layer, and connecting the first conductor layer and the second conductor layer, in, The inner wall surface of the via hole has: a first inclined surface whose diameter decreases from the first surface side to the middle portion side in the thickness direction of the resin insulating layer; a second inclined surface having a diameter smaller than a diameter of an end portion of the first inclined surface on the middle portion side and decreasing in diameter from the middle portion side to the second surface side; and A step surface is continuous with the first inclined surface and the second inclined surface.

2. The printed wiring board according to claim 1, wherein The inclination angle of the first slope relative to the first conductor layer is set to a first inclination angle, and the inclination angle of the second slope relative to the first conductor layer is set to a second inclination angle, and the second inclination angle is greater than the first inclination angle.

3. The printed wiring board according to claim 1, wherein The inner wall surface of the via hole is a non-roughened surface.

4. The printed wiring board according to claim 1, wherein The resin insulating layer comprises resin and inorganic particles, An inner wall surface of the via hole is formed by the resin and the inorganic particles.

5. The printed wiring board according to claim 1, wherein The via-hole conductor includes a seed layer formed on an inner wall surface of the via hole and a metal layer on the seed layer.

6. The printed wiring board according to claim 5, wherein The seed layer is a sputtered layer.

7. The printed wiring board according to claim 5, wherein The metal layer is an electroplating layer, The via hole is filled with the electroplating layer.

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