Silicon carbide-based lateral power semiconductor device and manufacturing method thereof

Abstract

The invention discloses a silicon carbide-based lateral power semiconductor device and a manufacturing method thereof. A silicon carbide-based lateral power semiconductor device includes: a substrate of a first conductivity type of silicon carbide material; the drift layer of the first conduction type is formed on the upper surface of the substrate, and the impurity concentration of the drift layer is lower than that of the substrate; a body region of a second conduction type formed on an upper layer portion of the drift layer; a collector region of a second conductivity type formed in an upper layer portion of the drift layer so as to be spaced apart from the body region in a lateral direction; and a trench buffer strip disposed between the body region and the collector region and configured to block an electric field from expanding in a lateral direction.

Description

Technical Field

[0001] The invention relates to a lateral power semiconductor device based on silicon carbide and a manufacturing method thereof. Background Art

[0002] Silicon carbide (SiC) has a maximum critical electric field 10 times higher and an energy band gap 3 times higher than silicon (Si), and therefore can be used to manufacture excellent power semiconductor devices with a high breakdown voltage (BV).

[0003] In order to realize silicon carbide power semiconductor devices, various studies are being conducted on processes and structures. Among them, lateral power semiconductor devices can be arranged on a plane and have the advantage of easily isolating power semiconductor devices from each other, so it is necessary to develop them.

[0004] Figure 1 It is a cross-sectional view of a lateral IGBT (Lateral Insulated Gate Bipolar Transistor; LIGBT) based on silicon carbide (SiC) in the prior art.

[0005] Reference Figure 1 (a) A SiC-based lateral IGBT may be formed using a semiconductor substrate having an N-conductivity drift layer 20 formed of SiC having an impurity concentration lower than that of the substrate 10 formed on an upper surface of an N+ conduction type substrate 10 formed of SiC and constituting a high-concentration impurity layer.

[0006] A P-conductivity type body region 30 is formed in an upper portion of the drift layer 20 , and an N+-conductivity type emitter region 40 is formed in an upper portion of the body region 30 (ie, an upper surface region of the semiconductor substrate).

[0007] In addition, a P-conductivity type collector region 50 is formed in the upper layer portion of the semiconductor substrate so as to be spaced apart from the body region 30 in the horizontal direction.

[0008] On the upper surface of the semiconductor substrate, an emitter metal layer 70 is formed in a manner covering a portion of the emitter region 40 and the body region 30 adjacent to the emitter region 40, and a collector metal layer 90 is formed in a manner covering the collector region 50. In addition, on the upper surface of the semiconductor substrate, between the emitter metal layer 70 and the collector region 50, a field insulating film 60 and a gate insulating film 65 are formed in a manner separating from the emitter metal layer 70 and the collector region 50, respectively.

[0009] The gate insulating film 65 may be formed to cover another portion of the emitter region 40, the body region 30 adjacent to the emitter region 40, and the adjacent drift layer 20. The gate insulating film 65 may be formed to be thinner than the field insulating film 60, and the field insulating film 60 and the gate insulating film 65 are connected to each other.

[0010] A polysilicon gate 80 is formed so as to cover the gate insulating film 65 and a part of the field insulating film 60 from above to form a channel.

[0011] As such, in the SiC-based lateral IGBT, the emitter and the collector are located on a plane, and therefore, there are advantages in that the power semiconductor devices can be easily arranged and isolated.

[0012] In order to ensure the target breakdown voltage of SiC-based lateral IGBT in breakdown voltage (BV) mode, as Figure 1 As shown in (b), the collector region 50 can only be located at the rear end of the position where the electric field intensity becomes 0 (zero) based on the position of the body region 30 (or the PN junction boundary).

[0013] However, in order to arrange the body region 30 and the collector region 50 with a sufficient distance (L1) in consideration of electric field diffusion, the chip size of the lateral IGBT can only be increased, and there is also a problem that the loss is reduced.

[0014] The above-mentioned background technology is technical information retained by the inventor in order to derive the present invention or obtained in the process of deriving the present invention, and it is not necessarily the known technology disclosed to the public before the application date of the present invention. Summary of the invention

[0015] Technical issues

[0016] The object of the present invention is to provide a lateral power semiconductor device based on silicon carbide and a manufacturing method thereof, which forms more than one trench buffer zone (Trench Buffer Zone) according to the breakdown voltage (BV) characteristics, so that the body region and the collector region are adjacently arranged in the horizontal direction, thereby reducing the chip size.

[0017] The object of the present invention is to provide a lateral power semiconductor device based on silicon carbide and a method for manufacturing the same, which can selectively and easily realize LIGBT (Lateral IGBT) or RC (Reverse Conducting)-LIGBT according to the ion implantation method for forming the collector region.

[0018] Other objects of the present invention can be easily understood through the following description.

[0019] Technical Solution

[0020] According to one embodiment of the present invention, there is provided a lateral power semiconductor device based on silicon carbide, comprising: a first conductivity type substrate of silicon carbide material; a first conductivity type drift layer formed on the upper surface of the substrate and having an impurity concentration lower than that of the substrate; a second conductivity type body region formed on the upper portion of the drift layer; a second conductivity type collector region formed on the upper portion of the drift layer in a manner separated from the body region in a lateral direction; and a trench buffer zone (Trench Buffer Zone) arranged between the body region and the collector region to block the electric field from expanding in the lateral direction.

[0021] The trench buffer zone may include: a buffer trench, which is formed by etching from the upper surface of the drift layer to the inside of the drift layer at a predetermined depth; a buffer insulating film, which fills the inside of the buffer trench; and a first conductive type buffer zone, which wraps at least one of the two side surfaces and the bottom surface of the buffer trench when viewed from a cross-section.

[0022] The trench buffer zone may be formed at a position relatively close to the collector region and at a predetermined position to ensure a predetermined target breakdown voltage.

[0023] The buffer trench may be formed to have a depth reaching 2 / 3 of the thickness of the drift layer.

[0024] The buffer region may be formed to have a higher impurity concentration than that of the drift layer.

[0025] The buffer region may be formed by vertically implanting and obliquely implanting ions of the first conductivity type into the buffer trench.

[0026] The buffer grooves are formed as island structures separated from each other and arranged in a direction perpendicular to the current path direction in a plan view, and the buffer zone is formed to be continuous in a direction perpendicular to the current path direction in a plan view.

[0027] The collector region is formed as an island structure separated from each other and arranged in a direction perpendicular to the current path direction in a plan view, and an anode region of the first conductivity type having an impurity concentration higher than that of the drift layer is formed between the separated collector regions.

[0028] A plurality of the trench buffer zones may be formed between the body region and the collector region, and the plurality of trench buffer zones may be in contact with each other.

[0029] The lateral power semiconductor device may further include: a field insulating film formed on the upper part of a portion of the drift layer located between the body region and the collector region and connected to the buffer insulating film; and a floating metal penetrating the field insulating film and used to connect the drift layer surface on the body region side and the drift layer surface on the collector region side separated by the groove buffer zone, and the buffer zone expands to the area where the floating metal contacts the drift layer on the body region side.

[0030] The floating metal may form a second current path, the length of the second current path being shorter than the length of the first current path in the lower region of the trench buffer zone.

[0031] When viewed in cross section, a second conductivity type electric field reduction region of a predetermined length may be formed in a surface portion of the drift layer located between the body region and the trench buffer zone.

[0032] According to another embodiment of the present invention, a method for manufacturing a lateral power semiconductor device based on silicon carbide is provided, which includes the following steps: forming a drift layer with an impurity concentration lower than that of the first conductivity type of the substrate on the upper surface of a first conductivity type substrate of silicon carbide; etching from the upper surface of the drift layer to the inside of the drift layer at a predetermined depth to form a buffer groove; injecting second conductivity type ions into the upper part of the drift layer using a preset first mask to form a second conductivity type body region separated from the buffer groove in a first direction and a second conductivity type collector region separated from the buffer groove in a second direction opposite to the first direction; and injecting first conductivity type ions into the upper part of the body region using a preset second mask to form an emitter region, and vertically and obliquely injecting first conductivity type ions into the buffer groove to form a buffer zone wrapping at least one of the two side surfaces and the bottom surface of the buffer groove.

[0033] The manufacturing method of the silicon carbide-based lateral power semiconductor device may further include the following steps: forming a buffer insulating film in a manner that fills the interior of the buffer trench, and forming a field insulating film on the upper portion of a portion of the drift layer located between the body region and the collector region, the field insulating film being connected to the buffer insulating film; and forming a floating metal in a manner that penetrates the field insulating film, the floating metal being used to connect the drift layer surface on the body region side and the drift layer surface on the collector region side, which are separated based on the trench buffer zone.

[0034] Other embodiments, features, and advantages besides those described above will become more apparent from the accompanying drawings, claims, and detailed description.

[0035] Beneficial Effects

[0036] According to the embodiments of the present invention, by forming more than one trench buffer zone according to the breakdown voltage characteristics, the body region and the collector region can be arranged adjacent to each other in the horizontal direction, thereby significantly reducing the chip size.

[0037] In addition, a LIGBT or a RC-LIGBT can be selectively and easily realized according to an ion implantation method for forming a collector region. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 It is a cross-sectional view of a lateral IGBT (Lateral Insulated Gate Bipolar Transistor; LIGBT) based on silicon carbide (SiC) in the prior art.

[0039] Figure 2 FIG. 1 is a cross-sectional view of a SiC-based LIGBT according to an embodiment of the present invention.

[0040] Figures 3 to 5 FIG. 1 is a diagram showing a manufacturing process of a SiC-based LIGBT according to an embodiment of the present invention.

[0041] Figure 6 and Figure 7 Each of them is a cross-sectional view of a SiC-based LIGBT according to another embodiment of the present invention.

[0042] Figure 8 1 is a plan view showing the shapes of groove buffer zones according to other embodiments of the present invention.

[0043] Fig. 9 1 is a top view of a SiC-based RC-LIGBT according to another embodiment of the present invention and a schematic diagram of IV characteristics.

[0044] Fig.10 FIG. 1 is a cross-sectional view of a SiC-based LIGBT according to another embodiment of the present invention and a schematic diagram of a current path when the LIGBT is turned on. DETAILED DESCRIPTION

[0045] The present invention may be subjected to various transformations and may have various embodiments, and a plurality of specific embodiments are shown in the drawings and described in detail in the specific embodiments. However, this is not intended to limit the present invention to a specific embodiment, but should be understood to include all transformations, equivalent scopes and substitutes included in the concept and technical scope of the present invention. When describing the present invention, when it is determined that the specific description of the relevant known technology may confuse the main points of the present invention, the detailed description is omitted.

[0046] The terms "first", "second" and the like may be used to describe a plurality of constituent elements, but the plurality of constituent elements should not be limited to the terms. The terms are only used to distinguish one constituent element from another constituent element.

[0047] The terms used in this application are only used to illustrate specific embodiments, rather than to limit the present invention. Unless a different meaning is clearly expressed in the text, a singular expression includes a plural expression. In this application, terms such as "including" or "having" are used to specify the existence of features, numbers, steps, operations, constituent elements, parts or combinations thereof recorded in the specification, rather than excluding in advance the possibility of the existence or addition of one or more other features or numbers, steps, operations, constituent elements, parts or combinations thereof.

[0048] When an element, such as a layer, region, or substrate, is described as being "on" or extending "onto" another element, the element may be located directly above or extending directly onto the other element, or there may be intervening elements. Conversely, when an element is described as being "directly on" or extending "directly onto" another element, there are no other intervening elements. Additionally, when an element is described as being "connected" or "coupled" to another element, the element may be directly connected or directly coupled to the other element, or there may be intervening elements. Conversely, when an element is described as being "directly connected" or "directly coupled" to another element, there are no other intervening elements.

[0049] As shown in the drawings, relative terms such as "below" or "above" or "upper" or "lower" or "horizontal" or "lateral" or "vertical" are used to describe the relationship of one element, layer or region to another element, layer or region. It should be understood that these terms are added to the orientation shown in the drawings to encompass different orientations of the device.

[0050] Hereinafter, the embodiments of the present invention will be described in detail with reference to the related drawings. Although the following description is mainly based on an insulated gate bipolar transistor (IGBT), the technical concept of the present invention can be applied or expanded to various forms of semiconductor elements such as a power metal oxide semiconductor field effect transistor (MOSFET) in the same or similar manner.

[0051] Figure 2 is a cross-sectional view of a SiC-based LIGBT according to an embodiment of the present invention, Figures 3 to 5 is a diagram showing a manufacturing process of a SiC-based LIGBT according to an embodiment of the present invention, Figure 6 and Figure 7 Each of them is a cross-sectional view of a SiC-based LIGBT according to another embodiment of the present invention. Figure 8 is a top view showing the shape of the groove buffer zone of other embodiments of the present invention, Fig. 9 1 is a top view of a SiC-based RC-LIGBT according to another embodiment of the present invention and a schematic diagram of IV characteristics. Fig.10 FIG. 1 is a cross-sectional view of a SiC-based LIGBT according to another embodiment of the present invention and a schematic diagram of a current path when the LIGBT is turned on.

[0052] Reference Figure 2 (a) A lateral IGBT (LIGBT) based on SiC (silicon carbide) can be formed using a semiconductor substrate, wherein an N-conductivity drift layer 20 formed of SiC having an impurity concentration lower than that of the substrate 10 is formed on the upper surface of an N+ conduction type substrate 10 formed of SiC and constituting a high-concentration impurity layer.

[0053] When viewed from the cross section, a P-conductivity type body region 30 is formed in the upper portion of the drift layer 20, and an N+-conductivity type emitter region 40 is formed in the upper portion of the body region 30 (i.e., the upper surface region of the semiconductor substrate). In addition, a P-conductivity type collector region 50 is further formed in the upper portion of the semiconductor substrate so as to be separated from the body region 30 in the horizontal direction.

[0054] A trench buffer zone 100 is formed between the body region 30 and the collector region 50 to block the electric field that spreads from the emitter region 40 side to the collector region 50 side (ie, the electric field spreads in the lateral direction).

[0055] The trench buffer zone 100 includes: a buffer trench 110 formed by etching from the upper surface of the semiconductor substrate to the inside of the drift layer 20 to a predetermined depth; a buffer insulating film 120 filling the inside of the buffer trench 110; and an N-conductive buffer region 130 formed to entirely wrap the side and bottom surfaces of the buffer trench 110. The buffer insulating film 120 may be formed of the same material as the field insulating film 60 described later.

[0056] For example, assuming that a 1200V-class SiC-based LIGBT has a drift layer 20 formed with a thickness about 50% less than that of a vertical IGBT of the same class, the buffer trench 110 may be formed to have a depth of about 5 μm or less. As an example, the buffer trench 110 may be formed to have a depth of 2 / 3 of the thickness of the drift layer 20 and a width of 1 μm or less.

[0057] N-conductivity type ions are implanted into the buffer trench 110 by a vertical ion implantation method and an oblique ion implantation method, thereby forming an N-conductivity type buffer region 130 .

[0058] Considering the characteristic that the slope of the electric field is proportional to the concentration, the buffer region 130 is formed as an N-conductivity region having a higher ion concentration than the drift layer 20, so that the slope of the electric field decreases sharply before reaching the collector region 50 (see Figure 2 For example, in a 1200V class power semiconductor element, when the drift layer 20 is less than 1e15 / cm 3 When the buffer area 130 is less than 1e16 / cm 3 .

[0059] The SiC-based LIGBT of the present embodiment proposes a characteristic structure in which the buffer region 130 continuously wraps around the side surface and the bottom surface of the buffer trench 110 .

[0060] This is because, for silicon carbide materials, the buffer region 130 can be formed only by ion implantation, but there is a limitation that a depth of several μm or more cannot be achieved by conventional process methods.

[0061] The buffer trench 110 may be formed first, and then a high concentration of N-conductivity type ions may be implanted using the structure of the buffer trench to form the buffer region 130 to a relatively deep position, thereby overcoming this limitation and forming the buffer region 130 at an appropriate depth.

[0062] The buffer groove 110 for receiving the buffer insulating film 120 therein may be Figure 8 The shape can be formed into a predetermined length as shown in (a), or it can be formed into a predetermined length as shown in (a). Figure 8 In this case, the plurality of buffer trenches 110 separated into the plurality of islands may be arranged in a row in a manner perpendicular to the current direction when viewed from above.

[0063] As described above, the trench buffer zone 100 formed between the body region 30 and the collector region 50 can block the electric field from spreading in the lateral direction. Therefore, the collector region 50 can be arranged at a distance ( Figure 2 L2 in (b).

[0064] For example, in a 1200 V class LIGBT, the distance between the body region 30 and the collector region 50 can be set to be less than 15 μm, which is similar to the distance between the body region 30 and the collector region 50 of the LIGBT in the prior art without the trench buffer zone 100 (see Figure 1 The L1 in Fig.

[0065] At this time, the trench buffer zone 100 may be disposed between the body region 30 and the collector region 50, at a position relatively close to the collector region 50. This is because the trench buffer zone 100 for blocking the electric field from spreading in the lateral direction should be located at a position that can ensure a preset target breakdown voltage (BV) and before a position where the electric field in the lateral direction becomes 0 (zero).

[0066] Specifically, when the trench buffer zone 100 is arranged relatively close to the body region 30, the breakdown voltage value is relatively reduced, so the trench buffer zone 100 is located at a predetermined position where the target breakdown voltage value can be obtained. In addition, by arranging the collector region 50 close to the trench buffer zone 100, while ensuring the withstand voltage characteristics, the conduction characteristics and the switching characteristics can also ensure the minimum loss.

[0067] exist Figure 2 In (a), an example is shown in which the buffer zone 130 completely wraps the side surfaces and the bottom surface of the buffer groove 110 when viewed from a cross section. However, the side surface ( Figure 2 The buffer region 130 is formed in the region Q of the LIGBT. Therefore, in the cross section of the LIGBT, the buffer region 130 may also be formed to be different from Glyph Font.

[0068] Furthermore, on the upper surface of the semiconductor substrate, an emitter metal layer 70 is formed to cover a portion of the emitter region 40 and the body region 30 adjacent to the emitter region 40 , and a collector metal layer 90 is formed to cover the collector region 50 .

[0069] On the upper surface of the semiconductor substrate, between the emitter metal layer 70 and the collector region 50 , a field insulating film 60 and a gate insulating film 65 are formed so as to be separated from the emitter metal layer 70 and the collector region 50 , respectively.

[0070] The gate insulating film 65 may be formed to cover another portion of the emitter region 40 not covered by the emitter metal layer 70, the body region 30 adjacent to the emitter region 40, and the adjacent drift layer 20. The field insulating film 60 and the gate insulating film 65 are connected to each other, and the gate insulating film 65 may be formed to have a thickness less than that of the field insulating film 60 to smoothly form a channel.

[0071] A polysilicon gate 80 is formed so as to cover the gate insulating film 65 and a part of the field insulating film 60 from above to form a channel.

[0072] exist Figure 2 FIG. 4 shows a case where the polysilicon gate 80 is a planar gate structure. Figure 7 As shown, the polysilicon gate 80 may also be a trench gate structure. Figure 7 In the figure, reference numeral 210 denotes a gate trench.

[0073] Reference Figures 3 to 5 The manufacturing process of the SiC-based LIGBT of this embodiment is briefly described as follows: a semiconductor substrate is generated, wherein an N-conductivity type drift layer 20 formed of SiC having an impurity concentration lower than that of the substrate 10 is formed by epitaxial growth on the upper surface of an N+ conduction type substrate 10 formed of SiC and constituting a high-concentration impurity layer (see Figure 3 (a)).

[0074] Next, a buffer trench 110 is formed by etching from the upper surface of the semiconductor substrate toward the inside of the drift layer 20 to a predetermined depth (see FIG. Figure 3 (b)).

[0075] Next, a predetermined first mask (not shown) is used to implant P-conductivity type ions into the upper layer of the drift layer 20, thereby forming a P-conductivity type body region 30 separated along a first direction of the buffer trench 110 and a P-conductivity type collector region 50 separated along a second direction of the buffer trench 110 which is the opposite direction to the first direction (see FIG. Figure 3 (c)).

[0076] Next, a preset second mask (not shown) is used to implant N-conductivity type ions into the upper layer of the body region 30 to form the emitter region 40, and N-conductivity type ions are implanted into the buffer trench 110 by a vertical implantation method and an inclined implantation method to form a buffer region 130 that completely surrounds both side surfaces and the bottom surface of the buffer trench 110 (see FIG. Figure 4 (d)).

[0077] As described above, the buffer zone 130 may be omitted from the side of the buffer trench 110 adjacent to the collector region 50 based on the consideration of the slope of the electric field reduction, the spacing between the trench buffer zone 100 and the collector region 50, and the like. Therefore, the buffer zone 130 may also be formed to be different from Glyph Font.

[0078] Next, the buffer insulating film 120 is formed to fill the inside of the buffer trench 110, and the field insulating film 60 is formed to cover a portion of the upper surface of the drift layer 20 between the body region 30 and the collector region 50 (see Figure 4 (e)). At this time, the buffer insulating film 120 and the field insulating film 60 may be formed of the same material and may be formed in a T-shape connected to each other.

[0079] Next, a gate insulating film 65 is formed on the upper surface of the semiconductor substrate so as to cover a portion of the emitter region 40, the body region 30 adjacent to the emitter region 40, and the adjacent drift layer 20 and to be connected to the field insulating film 60 (see Figure 4 (f)). The gate insulating film 65 may be formed to have a thickness smaller than that of the field insulating film 60 to smoothly form a channel.

[0080] Next, a polysilicon gate 80 is formed so as to cover a portion of the field insulating film 60 and the gate insulating film 65 from above (see Figure 5 (g)).

[0081] In addition, an emitter metal layer 70 is formed to cover another portion of the emitter region 40 and the body region 30 adjacent to the emitter region 40 and to be separated from the polysilicon gate 80, and a collector metal layer 90 is formed to cover the collector region 50 (see Figure 5 (h)).

[0082] As described above, the SiC-based LIGBT of this embodiment forms one or more trench buffer zones 100 between the body region 30 and the collector region 50 in a manner corresponding to the breakdown voltage characteristics, so that the body region 30 and the collector region 50 can be arranged relatively close in the horizontal direction, thereby having the characteristic of significantly reducing the chip size.

[0083] The trench buffer zone 100 formed between the body region 30 and the collector region 50 to block the electric field from spreading in the lateral direction is not limited to the following. Figure 2 As shown in the figure, only one is formed, such as Figure 6 As shown, more than two trench buffer zones 100 may be formed between the body region 30 and the collector region 50 .

[0084] When two or more groove buffer strips 100 are formed, the width and depth of the buffer grooves 110 of each groove buffer strip 100 may be the same, but the width and depth of each buffer groove 110 are not necessarily the same.

[0085] In addition, if Figure 6 As shown, each groove buffer zone 100 may be formed to be continuous or spaced apart from each other at a predetermined interval.

[0086] in addition, Figure 6 The first trench buffer zone 100 relatively close to the collector region 50 and the second trench buffer zone 100 relatively close to the body region 30 are both formed with In the case of wrapping the buffer zone 130 of the buffer groove 110 in the shape of a character, the first groove buffer zone 100 may also be formed as a buffer zone 130 configured between a plurality of buffer grooves 110 in a shared manner. The second groove buffer zone 100 is formed into a Font.

[0087] In addition, if Figure 6 and Figure 7 As shown, a P-conductivity type electric field reduction region 140 may be further formed in a surface portion of the semiconductor substrate between the body region 30 and the trench buffer zone 100 in a manner separated from the body region 30 and the trench buffer zone 100 .

[0088] The electric field reduction region 140 is formed on the surface of the semiconductor substrate to reduce the surface electric field. This is because when the surface electric field is strong, multiple mobile charges at the SiC / oxide interface move and redistribute due to the electric field, resulting in a decrease in the breakdown voltage (BV degradation) and affecting the life reliability of the power semiconductor device.

[0089] To this end, the electric field reduction region 140 should be as long as possible to effectively reduce the surface electric field, and may be formed in a shape that does not hinder a surface current path.

[0090] Fig. 9 A top view of a SiC based RC-LIGBT according to another embodiment of the present invention is shown.

[0091] like Fig. 9As shown in (a), when a P-conductivity collector region 50 is formed, a plurality of collector regions 50 separated from each other in an island form by exposing an N-conductivity drift layer 20 between them can also be formed, thereby forming a SiC-based RC (Reverse Conducting)-LIGBT in which P-conductivity regions and N-conductivity regions alternate. At this time, when viewed from above, the plurality of collector regions 50 separated from each other in an island form can be arranged in a row in a direction perpendicular to the current path.

[0092] At this time, N-conductivity type ions may be implanted into the region at a higher ion concentration than that of the drift layer 20 , so that the drift layer 20 exposed between the plurality of collector regions 50 separated into island forms may be formed into an N-conductivity type anode region 310 .

[0093] Reference Fig. 9 (b) briefly compares the characteristics of LIGBT and RC-LIGBT. LIGBT exhibits a diode-shaped turn-on characteristic that requires a diode turn-on voltage of the collector. In contrast, RC-LIGBT has the characteristics of IGBT and MOSFET. Therefore, when Vce is above 0V, the MOSFET structure turns on first, and then, when Vce increases, the IGBT structure turns on. Therefore, it can conduct current even at a Vce lower than that of LIGBT, and therefore has the characteristic of relatively small conduction loss.

[0094] Fig.10 A cross-sectional view of a SiC-based LIGBT according to another embodiment of the present invention is shown.

[0095] like Fig.10 As shown, a floating metal 1010 may be formed to penetrate the field insulating film 60 and connect the drift layer 20 on the body region 30 side and the drift layer 20 on the collector region 50 side separated by the trench buffer zone 100 .

[0096] The floating metal 1010 not only further provides a current path that detours the trench buffer zone 100, but also forms a second current path (path ②) that is shorter than the conventional first current path (path ①) in the lower region of the trench buffer zone 100. The second current path further formed by the floating metal 1010 can significantly improve the situation where the current is hindered by the formation of the trench buffer zone 100.

[0097] When the electric field reaches the area where the floating metal 1010 contacts the drift layer 20 , breakdown occurs and the floating metal 1010 cannot withstand a higher voltage. Therefore, the buffer area 130 may extend to the area where the floating metal 1010 contacts the drift layer 20 to block the electric field spreading in the lateral direction.

[0098] Fig.10The buffer zone 130 is shown to extend only to the drift layer 20 on the body region 30 side connected to the floating metal 1010. This assumes that the electric field cannot reach the drift layer 20 on the collector region 50 side due to the trench buffer zone 100. When the electric field can reach the drift layer 20 on the collector region 50 side, the buffer zone 130 can also extend to the drift layer 20 on the body region 30 side connected to the floating metal 1010.

[0099] Regardless of whether the electric field reaches or not, in order to reduce the contact resistance with the floating metal 1010 , the buffer region 130 may also extend to the drift layer 20 on the collector region 50 side.

[0100] In the above description, the power semiconductor device is an insulated gate diode transistor (IGBT) as an example, but the technical concept of the present invention can be applied and expanded to various forms of power semiconductor elements such as power metal oxide semiconductor field effect transistors in the same or similar manner.

[0101] Although the present invention has been described above with reference to the embodiments thereof, a person skilled in the art can make various modifications and changes to the present invention without departing from the scope of the present invention as described in the appended claims.

Claims

1. A lateral power semiconductor device based on silicon carbide, characterized in that: include: a substrate of a first conductivity type of silicon carbide material; A drift layer of a first conductivity type is formed on the upper surface of the substrate and has an impurity concentration lower than that of the substrate; A body region of a second conductivity type formed in an upper portion of the drift layer; A collector region of a second conductivity type is formed in an upper layer portion of the drift layer in a manner spaced apart from the body region in a lateral direction; as well as The groove buffer zone is arranged between the body region and the collector region, and is used to prevent the electric field from expanding in the lateral direction.

2. The silicon carbide-based lateral power semiconductor device according to claim 1, characterized in that: The groove buffer zone comprises: a buffer trench formed by etching from the upper surface of the drift layer to the inside of the drift layer to a predetermined depth; a buffer insulating film filling the interior of the buffer trench; and The first conductive buffer region surrounds at least one of the two side surfaces and the bottom surface of the buffer groove when viewed in cross section.

3. The silicon carbide-based lateral power semiconductor device according to claim 2, characterized in that: The trench buffer zone is formed at a position relatively close to the collector region and at a predetermined position to ensure a predetermined target breakdown voltage.

4. The silicon carbide-based lateral power semiconductor device according to claim 2, characterized in that: The buffer trench is formed to have a depth reaching 2 / 3 of the thickness of the drift layer.

5. The silicon carbide-based lateral power semiconductor device according to claim 2, characterized in that: The buffer region is formed to have a higher impurity concentration than the drift layer.

6. The silicon carbide-based lateral power semiconductor device according to claim 2, characterized in that: The buffer region is formed by vertically implanting and obliquely implanting ions of the first conductivity type into the buffer trench.

7. The silicon carbide-based lateral power semiconductor device according to claim 2, characterized in that: The buffer grooves are formed as island structures separated from each other and arranged in a direction perpendicular to the current path direction in a plan view. The buffer zone is formed to be continuous in a direction perpendicular to the current path direction in a plan view.

8. The silicon carbide-based lateral power semiconductor device according to claim 1, characterized in that: The collector region is formed as an island structure separated from each other and arranged in a direction perpendicular to the current path direction when viewed from above. An anode region of the first conductivity type having an impurity concentration higher than that of the drift layer is formed between collector regions separated from each other.

9. The silicon carbide-based lateral power semiconductor device according to claim 1, characterized in that: A plurality of the trench buffer zones are formed between the body region and the collector region, and the plurality of trench buffer zones are in contact with each other.

10. The silicon carbide-based lateral power semiconductor device according to claim 2, characterized in that: The lateral power semiconductor device further comprises: a field insulating film formed on an upper portion of a portion of the drift layer between the body region and the collector region and connected to the buffer insulating film; and A floating metal penetrates the field insulating film and is used to connect the drift layer surface on the body region side and the drift layer surface on the collector region side separated by the trench buffer zone. The buffer zone expands to a region where the floating metal contacts the drift layer on the body region side.

11. The silicon carbide-based lateral power semiconductor device according to claim 10, characterized in that: The floating metal forms a second current path, and the length of the second current path is shorter than the length of the first current path in the lower region of the trench buffer zone.

12. The silicon carbide-based lateral power semiconductor device according to claim 1, characterized in that: When viewed in cross section, a second conductivity type electric field reduction region of a predetermined length is formed in a surface portion of the drift layer located between the body region and the trench buffer zone.

13. A method for manufacturing a lateral power semiconductor device based on silicon carbide, characterized in that: The steps include: forming a drift layer of the first conductivity type having an impurity concentration lower than that of the first conductivity type of the substrate on an upper surface of the first conductivity type substrate of silicon carbide; Etching from the upper surface of the drift layer to the inside of the drift layer to a predetermined depth to form a buffer trench; Implanting ions of the second conductivity type into the upper portion of the drift layer through a preset first mask to form a body region of the second conductivity type separated from the buffer trench in a first direction and a collector region of the second conductivity type separated from the buffer trench in a second direction opposite to the first direction; as well as The first conductive type ions are injected into the upper portion of the body region through a preset second mask to form an emission region, and the first conductive type ions are vertically and obliquely injected into the buffer groove to form a buffer zone covering at least one of the two side surfaces and the bottom surface of the buffer groove.

14. The method for manufacturing a lateral power semiconductor device based on silicon carbide according to claim 13, characterized in that: Further comprising the steps of: forming a buffer insulating film so as to fill the inside of the buffer trench, and forming a field insulating film on the upper portion of a portion of the drift layer located between the body region and the collector region, the field insulating film being connected to the buffer insulating film; as well as A floating metal is formed to penetrate the field insulating film, the floating metal being used to connect a surface of the drift layer on the body region side and a surface of the drift layer on the collector region side separated by the trench buffer zone.

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