Test structure and method for testing design rule of semiconductor device
Through multiple sets of parallel structure testing units and shared pads, the problems of long testing time and large area in the existing technology are solved, rapid testing and resource savings are achieved, and development efficiency is improved.
Patent Information
- Application Number
- CN202310779816.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-06-28
- Publication Date
- 2024-12-31
AI Technical Summary
In the prior art, the test structure of semiconductor device design rules has a long test time and a large area occupies, resulting in extended development cycle and waste of resources.
Multiple groups of test units are adopted, each group of test units includes multiple transistors in parallel structures, which are derived through the splitting of the parallel structure and common pads to achieve rapid testing and area savings.
It realizes rapid testing and evaluation of the impact of the minimum value structure of different design rules on device characteristics, shortens testing time, reduces development costs, and improves resource utilization.
Smart Images
Figure CN119224511A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor device manufacturing and testing, and in particular to a test structure and method for checking semiconductor device design rules. Background Art
[0002] In the process of logic technology integrated circuit design and layout design, it is necessary to comply with the design rules. In order to implement the design rule check and modification, the minimum structure (Sub-rule) in different design rules needs to be placed as the test structure of the corresponding design rule. In the prior art, a separate structure is usually used to monitor the minimum structure (Sub-rule) in different design rules. This test structure takes a long time to test, affects the product development cycle, and leads to waste of manpower, machines and materials. Moreover, a separate test structure requires a separate pad for lead-out, resulting in a large area occupied by the overall test structure, which is not conducive to full utilization of the layout area.
[0003] It should be noted that the above introduction to the technical background is only for the convenience of providing a clear and complete description of the technical solutions of the present application and for the convenience of understanding by those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because they are described in the background technology section of the present application. Summary of the invention
[0004] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a test structure and method for verifying the design rules of semiconductor devices, so as to solve the problems of long test time and large occupied area of the test structure in the prior art.
[0005] To achieve the above-mentioned purpose and other related purposes, the present invention provides a test structure for verifying the design rules of semiconductor devices, the test structure comprising: one or more groups of test units, each group of test units comprising a plurality of transistors arranged according to different design rules, several transistors among the plurality of transistors forming one or more parallel structures in a manner of connecting gate terminals and drain terminals in parallel, the one or more groups of test units being arranged in sequence, and when there are more than two groups of test units, compared with the current group of test units, at least one parallel structure in the previous group of test units is split into two or more parallel sub-structures and arranged in the current group of test units.
[0006] Optionally, the parallel structure is split by splitting the parallel connection lines between the gate terminal and the drain terminal of the transistor.
[0007] Optionally, the channel widths of the plurality of transistors in the test unit are set to be different from each other, or / and the channel lengths of the plurality of transistors are set to be different from each other.
[0008] Optionally, the gate terminal and the drain terminal of the transistors in each parallel structure or parallel sub-structure are respectively connected to the corresponding common gate pad and the common drain pad to achieve extraction.
[0009] Optionally, source terminals and body terminals of all transistors in the test unit are respectively connected in parallel, and the source terminals and body terminals are respectively connected to corresponding common source pads and common body pads to achieve lead-out.
[0010] Optionally, the test structure is arranged in a scribe line area of a wafer.
[0011] Optionally, the gate terminals and drain terminals of all transistors of the first group of test units are respectively connected in parallel to form a parallel structure.
[0012] The present invention also provides a test method for verifying the design rules of semiconductor devices, and the test method includes the following steps: 1) providing a test structure for verifying the design rules of semiconductor devices as described in any one of claims 1 to 6; 2) testing a first group of test units, wherein the gate terminals and drain terminals of all transistors in the first group of test units are respectively connected in parallel to form a parallel structure, and voltage is applied to the parallel gate terminals and the parallel drain terminals to open the channels of each transistor and perform a first electrical parameter measurement; 3) comparing the first electrical parameter with the design value, if they are consistent, the design rules of all transistors in the parallel structure are applicable; if they are inconsistent, continuing to test the next group of test units; 4) in the next group of test units, the parallel structure in the first group of test units is split into two parallel sub-structures, and the gate terminals and drain terminals of the transistors in the two parallel sub-structures are connected in parallel. The two parallel substructures are connected in parallel; 5) voltage is applied to the parallel gate terminals and the parallel drain terminals of the two parallel substructures to open the channel of each transistor and the electrical parameter measurement of the two parallel substructures is performed for the second time; 6) the second electrical parameter is compared with the design value. If the electrical parameter of one of the parallel substructures is consistent, the design rules of all transistors in the parallel substructure are available. At this time, according to step 4), the other parallel substructure is split in the next group of test units and the electrical parameter measurement is performed until the abnormal transistor with inconsistent electrical parameters is found; if the electrical parameters of the two parallel substructures are inconsistent, according to step 4), the two parallel substructures are split at the same time in the next group of test units and the electrical parameter measurement is performed until all abnormal transistors with inconsistent electrical parameters are found, and the design rules corresponding to the abnormal transistors are unavailable.
[0013] Optionally, the electrical parameter includes one, multiple or a function of multiple of a linear region drain current Idlin, a saturation region drain current Idsat, an off current Ioff, a linear region threshold voltage Vtlin, and a saturation region threshold voltage Vtsat.
[0014] Optionally, the testing method further comprises the steps of: comparing electrical parameters of the abnormal transistor that are inconsistent with design values, and adjusting corresponding design rules according to the inconsistent electrical parameters to ultimately make the design rules usable.
[0015] As described above, the test structure and method for verifying the design rules of semiconductor devices of the present invention have the following beneficial effects:
[0016] The present invention uses multiple sets of parallel structures with different connection rules. Compared with discrete structures, the present invention can simultaneously measure multiple transistor devices, and can quickly test and evaluate the impact of the minimum structure (Sub-rule) in different design rules on device characteristics. At the same time, the present invention can effectively reduce the area occupied by the test structure through a shared pad.
[0017] The test structure of the present invention has a simple test process, and can quickly locate abnormal transistors according to the test results, accurately determine the parameters that affect device characteristics, and then adjust the corresponding design rules according to the parameters of the abnormal transistors.
[0018] The present invention can effectively shorten the test evaluation time, thereby saving the development cycle and reducing the development cost. BRIEF DESCRIPTION OF THE DRAWINGS
[0019] The included drawings are used to provide a further understanding of the embodiments of the present application, which constitute a part of the specification, are used to illustrate the implementation of the present application, and together with the text description, explain the principles of the present application. Obviously, the drawings described below are only some embodiments of the present application.
[0020] Figure 1 to Figure 3 Shown are structural schematic diagrams of multiple groups of test units in a test structure for verifying a semiconductor device design rule according to an embodiment of the present invention.
[0021] Figure 4 The diagram shows a test flow diagram of a test method for verifying design rules of a semiconductor device according to an embodiment of the present invention.
[0022] Component number description
[0023] 1 First test unit
[0024] 10. Transistor
[0025] 11 Parallel structure
[0026] 112 Gate terminal
[0027] 113 Source
[0028] 114 Drain
[0029] 115 Body end
[0030] 116 Common gate pad
[0031] 117 Shared drain pad
[0032] 118 shared source pad
[0033] 119 Shared body pad
[0034] 2 Second test unit
[0035] 21 First parallel substructure
[0036] 22 Second parallel substructure
[0037] 211 first shared sub-gate pad
[0038] 212 first common sub-drain pad
[0039] 221 second shared sub-gate pad
[0040] 222 Second shared sub-drain pad
[0041] 3. The third test unit
[0042] 31 The third parallel substructure
[0043] 32 Fourth parallel substructure
[0044] 311 third shared sub-gate pad
[0045] 312 The third shared sub-drain pad
[0046] 331 fourth common sub-gate pad
[0047] 332 fourth common sub-drain pad
[0048] Steps S11 to S17 DETAILED DESCRIPTION
[0049] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.
[0050] It should be emphasized that the term “include / comprises” when used herein refers to the presence of features, integers, steps or components, but does not exclude the presence or addition of one or more other features, integers, steps or components.
[0051] Features described and / or illustrated with respect to one embodiment may be used in the same or similar manner in one or more other embodiments, combined with features in other embodiments, or substituted for features in other embodiments.
[0052] For example, when describing the embodiments of the present invention in detail, for the sake of convenience, the cross-sectional view showing the device structure will not be partially enlarged according to the general scale, and the schematic view is only an example, which should not limit the scope of protection of the present invention. In addition, in actual production, the three-dimensional space dimensions of length, width and depth should be included.
[0053] For ease of description, spatially relative terms such as "under", "below", "below", "below", "above", "on", etc. may be used herein to describe the relationship of one element or feature shown in the drawings to other elements or features. It will be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the drawings. In addition, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.
[0054] In the context of the present application, a structure in which a first feature is described as being "above" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.
[0055] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and therefore the illustrations only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.
[0056] In the prior art, a separate structure is usually used to monitor the minimum structure (Sub-rule) in different design rules. This test structure takes a long time to test, affects the product development cycle, and causes waste of manpower, equipment, and materials. Moreover, a separate test structure requires a separate pad for lead-out, resulting in a large area occupied by the overall test structure, which is not conducive to fully utilizing the layout area.
[0057] like Figure 1 to Figure 3As shown, the present application provides a test structure for verifying the design rules of a semiconductor device, the test structure comprising: one or more groups of test units, each group of test units comprising a plurality of transistors arranged according to different design rules, several transistors among the plurality of transistors forming one or more parallel structures in a manner of connecting gate terminals and drain terminals in parallel, wherein one or more groups of test units are arranged in sequence, and when there are more than two groups of test units, compared with the current group of test units, at least one parallel structure in the previous group of test units is split into two or more parallel sub-structures and arranged in the current group of test units.
[0058] In one embodiment, gate terminals and drain terminals of a plurality of transistors connected in parallel are respectively connected to corresponding common gate pads and common drain pads to achieve extraction.
[0059] In one embodiment, for multiple transistors in the same group of test units, the source terminals and body terminals of all transistors in the test unit are connected in parallel. Preferably, the source terminals and body terminals after parallel connection can be brought out through a common source pad and a common body pad to facilitate the connection of subsequent tests.
[0060] In one embodiment, the parallel connection of the gate and drain terminals of the transistor is split to achieve the splitting of the parallel structure. In a specific example, the split gate and drain terminals are respectively connected to independent common gate pads and common drain pads to achieve separate lead-out of each parallel substructure, so as to facilitate the connection of subsequent tests.
[0061] In one embodiment, the transistor may be, for example, a metal-oxide semiconductor field effect transistor (MOS).
[0062] In one embodiment, each group of test units of the test structure is disposed in a scribe line region of a wafer, thereby saving the area actually occupied by the test structure and improving the utilization rate of the wafer area.
[0063] In one embodiment, in the test unit, the channel widths of multiple transistors set according to different design rules are set to be different from each other, or / and the channel lengths of multiple transistors are set to be different from each other. Preferably, the design rules of the semiconductor devices used on the wafer are all provided with transistors corresponding to the design rules in the test unit, so that the semiconductor devices designed according to all the design rules used on the wafer can be tested simultaneously through the test unit.
[0064] In one embodiment, no matter for one group or more than two groups of test units, the gate terminals and drain terminals of all transistors of the first group of test units are respectively connected in parallel to form a parallel structure.
[0065] Figure 1 to Figure 3A schematic diagram showing the structure of three groups of test units for testing the design rules of semiconductor devices is shown below. Figure 1 to Figure 3 Take the test structure of this application as an example to describe in detail.
[0066] See also Figure 1 , Figure 1 The structure shown is the first test unit 1, which consists of Figure 1 It can be seen that a plurality of transistors 10 are provided in the first test unit 1, as shown in the figure, there are 5 transistors 10, and the 5 transistors 10 are set according to different design rules, for example, the channel widths of the 5 transistors 10 are different from each other. In the first test unit, the gate terminal 112, the drain terminal 114, the source terminal 113 and the body terminal 115 of the 5 transistors 10 are respectively connected in parallel to form a parallel structure 11, and are respectively connected to a common common gate pad 116, a common drain pad 117, a common source pad 118 and a common body pad 119 for subsequent test connection. During the test, the 5 transistors can be turned on at the same time by applying voltage to the common gate pad 116 and the common drain pad 117, and the electrical parameters of the 5 transistors after superposition can be tested, so that it can be quickly and preliminarily judged whether the design rules corresponding to the 5 transistors are all available or the design rules corresponding to some transistors are not available.
[0067] See also Figure 2 , Figure 2 The structure shown is the second test unit 2, which consists of Figure 2 It can be seen that the transistors set in the second test unit 2 are the same as those in the first test unit 1, wherein the five transistors are divided into two parallel substructures, namely a first parallel substructure 21 comprising two transistors and a second parallel substructure 22 comprising three transistors. The parallel gate terminals of the first parallel substructure 21 are led out through the first common sub-gate pad 211, and the parallel drain terminals are led out through the first common sub-drain pad 212. The parallel gate terminals of the second parallel substructure 22 are led out through the second common sub-gate pad 221, and the parallel drain terminals are led out through the second common sub-drain pad 222.
[0068] See also Figure 3 , Figure 3 The structure shown is the third test unit 3, which consists of Figure 2It can be seen that the transistors set in the third test unit 3 are the same as those in the second test unit 2, wherein, compared with the second test unit 2, its second parallel substructure is further split into two parallel substructures, namely a third parallel substructure 31 comprising two transistors and a fourth parallel substructure 32 comprising one transistor. Furthermore, the gate and drain terminals of the third parallel substructure can continue to be connected to the first parallel substructure 21 through the shared third shared sub-gate pad 311 and the third shared sub-drain pad 312, and the gate and drain terminals of the fourth parallel substructure are connected through the fourth shared sub-gate pad 331 and the fourth shared sub-drain pad 332.
[0069] The testing process of verifying the design rules of the semiconductor device through the above-mentioned multiple groups of test units will be presented in detail in the following testing method.
[0070] like Figure 1 to Figure 4 As shown, Figure 4 The figure shows a flow chart of the steps of the test method for checking the design rules of semiconductor devices of the present application. The present embodiment provides a test method for checking the design rules of semiconductor devices. The test method includes the following steps:
[0071] First, a test structure for verifying the design rules of a semiconductor device as described in the above embodiment is provided;
[0072] Then, if Figure 1 and Figure 4 As shown, step S11 is performed to test the first group of test units, the gate terminals and drain terminals of all transistors of the first group of test units are respectively connected in parallel to form a parallel structure, voltage is applied to the parallel gate terminals and parallel drain terminals to open the channel of each transistor and perform the first electrical parameter measurement;
[0073] Then, if Figure 4 As shown, step S12 is performed to compare the first electrical parameter with the design value to determine whether the first electrical parameter is consistent with the design value. If they are consistent, the design rules of all transistors in the parallel structure are applicable; if they are inconsistent, it means that there is at least one abnormal transistor that makes the electrical parameter abnormal, and step S13 is performed;
[0074] Then, if Figure 2 and Figure 4 As shown, step S13 is performed to continue testing the next group of test units; in the next group of test units, the parallel structure in the first group of test units is split into two parallel sub-structures, and the gate terminals and drain terminals of the transistors in the two parallel sub-structures are respectively connected in parallel;
[0075] Then, if Figure 4As shown, step S14 is performed to apply voltage to the parallel gate terminals and parallel drain terminals of the two parallel substructures to open the channel of each transistor and perform a second electrical parameter measurement on the two parallel substructures respectively;
[0076] Then, if Figure 4 As shown, step S15 is performed, the second electrical parameter is compared with the design value to determine whether the second electrical parameter is consistent with the design value. If the electrical parameters of one of the parallel substructures are consistent, the design rules of all transistors in the parallel substructure are applicable, which means that the abnormal transistor exists and only exists in the other parallel substructure. At this time, step S16 is performed; if the electrical parameters of the two parallel substructures are inconsistent, it means that abnormal transistors exist in both parallel substructures, and step S17 is performed;
[0077] Then, if Figure 4 As shown, when the electrical parameters of one of the parallel substructures are consistent, step S16 is performed, and the other parallel substructure is split in the next group of test units according to step 4) and the electrical parameters are measured until the abnormal transistor with inconsistent electrical parameters is found; for example, Figure 2-Figure 3 As shown, if it is measured that an abnormal transistor exists in the parallel substructure 22, the parallel substructure 22 is further split to obtain the parallel substructure 31 and the parallel substructure 32, and then the electrical parameters of the parallel substructure 31 and the parallel substructure 32 are measured respectively. If the electrical parameters of the parallel substructure 31 are consistent with the design values, it can be determined that there is an abnormal transistor in the parallel substructure 32. At this time, the parallel substructure 32 only contains one transistor, then it can be determined that the transistor in the parallel substructure 32 is an abnormal transistor.
[0078] Or, if Figure 4 As shown, when the electrical parameters of the two parallel substructures are inconsistent, step S17 is performed, and the two parallel substructures are simultaneously split in the next group of test units according to step 4) and the electrical parameters are measured until all abnormal transistors with inconsistent electrical parameters are found, and the design rules corresponding to the abnormal transistors are unavailable. Among them, the specific step of finding all abnormal transistors with inconsistent electrical parameters can be performed by the method of the above step S16 to find all abnormal transistors with inconsistent electrical parameters.
[0079] In the above embodiment, the electrical parameter includes one, multiple or multiple functions of the linear region drain current Idlin, the saturation region drain current Idsat, the off current Ioff, the linear region threshold voltage Vtlin, and the saturation region threshold voltage Vtsat. For example, in a specific example, the electrical parameter is selected as the ratio of the saturation region drain current Idsat to the saturation region threshold voltage Vtsat, Idsat / Vtsat.
[0080] Furthermore, the testing method may also include the steps of: comparing electrical parameters of the abnormal transistor that are inconsistent with the design values, and adjusting corresponding design rules according to the inconsistent electrical parameters to ultimately make the design rules usable.
[0081] As described above, the test structure and method for verifying semiconductor device design rules of the present invention have the following beneficial effects:
[0082] The present invention uses multiple sets of parallel structures with different connection rules. Compared with discrete structures, the present invention can simultaneously measure multiple transistor devices, and can quickly test and evaluate the impact of the minimum structure (Sub-rule) in different design rules on device characteristics. At the same time, the present invention can effectively reduce the area occupied by the test structure through a shared pad.
[0083] The test structure of the present invention has a simple test process, and can quickly locate abnormal transistors according to the test results, accurately determine the parameters that affect device characteristics, and then adjust the corresponding design rules according to the parameters of the abnormal transistors.
[0084] The present invention can effectively shorten the test evaluation time, thereby saving the development cycle and reducing the development cost.
[0085] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.
Claims
1. A test structure for verifying the design rules of a semiconductor device, characterized in that: The test structure includes: one or more groups of test units, each group of test units includes multiple transistors set according to different design rules, several transistors among the multiple transistors form one or more parallel structures in a manner of connecting gate terminals and drain terminals in parallel, and one or more groups of test units are arranged in sequence. When there are more than two groups of test units, compared with the current group of test units, at least one parallel structure in the previous group of test units is split into two or more parallel sub-structures and set in the current group of test units.
2. The test structure for verifying the design rule of a semiconductor device according to claim 1, characterized in that: The parallel structure is split by splitting the parallel connection lines between the gate terminal and the drain terminal of the transistor.
3. The test structure for verifying the design rule of a semiconductor device according to claim 1, characterized in that: The channel widths of the plurality of transistors in the test unit are set to be different from each other, or / and the channel lengths of the plurality of transistors are set to be different from each other.
4. The test structure for verifying the design rule of a semiconductor device according to claim 1, characterized in that: The gate terminal and the drain terminal of each transistor in the parallel structure or the parallel sub-structure are respectively connected to the corresponding common gate pad and the common drain pad to achieve extraction.
5. The test structure for verifying the design rule of a semiconductor device according to claim 1, characterized in that: The source terminals and body terminals of all transistors in the test unit are respectively connected in parallel, and the source terminals and body terminals are respectively connected to corresponding common source pads and common body pads to achieve extraction.
6. The test structure for verifying the design rule of a semiconductor device according to claim 1, characterized in that: The test structure is arranged in the scribe line area of the wafer.
7. The test structure for verifying the design rule of a semiconductor device according to claim 1, characterized in that: The gate terminals and drain terminals of all transistors of the first group of test units are respectively connected in parallel to form a parallel structure.
8. A test method for verifying the design rules of a semiconductor device, characterized in that: Includes steps: 1) Providing a test structure for verifying semiconductor device design rules as described in any one of claims 1 to 7; 2) testing a first group of test units, wherein the gate terminals and drain terminals of all transistors of the first group of test units are connected in parallel to form a parallel structure, applying voltage to the parallel gate terminals and parallel drain terminals to open the channel of each transistor and perform a first electrical parameter measurement; 3) Compare the first electrical parameters with the design values. If they are consistent, the design rules of all transistors in the parallel structure are applicable; if they are inconsistent, proceed to the next set of test unit tests; 4) In the next group of test units, the parallel structure in the first group of test units is split into two parallel sub-structures, and the gate terminals and drain terminals of the transistors in the two parallel sub-structures are respectively connected in parallel; 5) applying voltage to the parallel gate terminals and parallel drain terminals of the two parallel substructures to open the channels of each transistor and performing a second electrical parameter measurement on the two parallel substructures respectively; 6) The electrical parameters are compared with the design values for the second time. If the electrical parameters of one of the parallel substructures are consistent, the design rules of all transistors in the parallel substructure are applicable. At this time, according to step 4), another parallel substructure is split in the next group of test units and the electrical parameters are measured until the abnormal transistor with inconsistent electrical parameters is found; 7) If the electrical parameters of the two parallel substructures are inconsistent, the two parallel substructures are simultaneously split in the next group of test units according to step 4) and the electrical parameters are measured until all abnormal transistors with inconsistent electrical parameters are found, and the design rules corresponding to the abnormal transistors are unavailable.
9. The test method for verifying the design rules of a semiconductor device according to claim 8, characterized in that: The electrical parameters include one, multiple or a function of multiple of a linear region drain current Idlin, a saturation region drain current Idsat, an off current Ioff, a linear region threshold voltage Vtlin, and a saturation region threshold voltage Vtsat.
10. The test method for verifying the design rule of a semiconductor device according to claim 8, characterized in that: The method also includes the steps of: comparing electrical parameters of abnormal transistors that are inconsistent with design values, and adjusting corresponding design rules according to the inconsistent electrical parameters to ultimately make the design rules usable.