Low-ripple quick-response digital LDO (Low Dropout Regulator) circuit and control method

Abstract

The invention relates to the technical field of integrated circuits, in particular to a low-ripple quick-response digital LDO circuit and a control method. The clock control comparator is used for monitoring the deviation between a feedback voltage VFB and a reference voltage VREF in real time and outputting a comparison signal; the partial stability detection circuit comprises a counter and a sequence detector which are both in digital design; the counter sends out a Cnt signal based on the continuity of the comparison signal and is used for detecting the continuity of the output signal; the sequence detector sends out a mode signal based on an output mode of the output signal and is used for evaluating whether the output signal reaches a preset target stable state or not; and the shift control circuit dynamically controls and adjusts the PMOS switch array according to a Cnt signal and a mode signal provided by the partial stability detection circuit to realize voltage adjustment. According to the digital LDO, the ripple problem of a traditional digital LDO can be solved, the precision of output voltage is improved while quick response is guaranteed, a window comparator and multiple reference voltages are prevented from being used, and errors caused by imbalance among multiple comparators are eliminated.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a low-ripple fast-response digital LDO circuit and a control method. Background Art

[0002] Digital LDO (DLDO) has attracted much attention due to its low voltage working capability and good process scalability. Compared with traditional analog LDO (ALDO), digital LDO requires a smaller power tube area when handling the same load current and has less stability issues. However, although digital LDO is widely used in high-efficiency power management systems for digital circuits, it still has problems with steady-state ripple and low power supply rejection ratio.

[0003] At present, in order to solve the steady-state ripple and power supply suppression problems in digital LDO, the following two main technical solutions are mainly adopted: The first is to add a large capacitor at the output end on the basis of the traditional digital LDO to effectively buffer the voltage fluctuation caused by load changes, thereby reducing the steady-state ripple. However, although this solution is useful, it brings about large space occupation, limited dynamic response and potential stability problems. The second is to use a coarse and fine loop adjustment mode in the digital LDO to achieve the goals of fast response and low ripple through two groups of PMOS arrays of different sizes, but this solution increases the complexity and power consumption of the design and may affect the accuracy of the system. Summary of the invention

[0004] The purpose of the present invention is to solve the above technical problems and to propose a low-ripple fast-response digital LDO circuit and control method, which can solve the ripple problem of traditional digital LDO and improve the accuracy of output voltage while ensuring fast response. The purpose of the present invention can be achieved through the following technical solutions:

[0005] The present invention provides a low-ripple fast-response digital LDO circuit, comprising: a clock control comparator, a partial stability detection circuit, a shift control switch circuit and an asynchronous control loop;

[0006] A clock-controlled comparator, used for real-time monitoring of the deviation between the feedback voltage VFB and the reference voltage VREF, and outputting a comparison signal;

[0007] The partial stability detection circuit, including a counter and a sequence detector, is digitally designed; the counter sends a Cnt signal based on the continuity of the comparison signal to detect the continuity of the output signal; the sequence detector sends a mode signal based on the output mode of the output signal to evaluate whether the output signal reaches a preset target stable state;

[0008] The shift control circuit dynamically controls the coarse and fine loops and adjusts the PMOS switch array to achieve voltage regulation according to the Cnt signal and the mode signal provided by the partial stability detection circuit and the internal carry signal FD. When the shift control circuit detects the carry signal FD, it switches from fine loop regulation to coarse loop regulation to speed up the regulation speed.

[0009] The input end of the clock control comparator is respectively connected to the feedback voltage VFB and the reference voltage VREF, and the output end is respectively connected to the shift control circuit and the counter and sequence detector in the partial stability monitoring circuit for outputting a comparison signal; the shift control circuit is connected to the partial stability monitoring circuit and the clock control comparator, and determines whether the voltage state is stable according to the output mode signal and Cnt signal. When the voltage state does not reach the stable state, the small-size array of the PMOS switch is fine-loop regulated. When the small-size array of the PMOS switch is regulated and has not reached the stable state, the carry signal FD is triggered, and the output voltage is coarse-loop regulated in combination with the large-size array of the PMOS switch to quickly respond to the change of the feedback voltage VFB, and switch to fine-loop regulation according to the mode signal to reach the stable state.

[0010] The input end of the asynchronous control loop is connected to the output voltage VOUT, and the output end of the asynchronous control loop is connected to the shift controller. When the output voltage variation reaches a preset value, a large undershoot is detected, and an asynchronous control signal AS_ctrl is output. The asynchronous control signal AS_ctrl directly sets the coarse-ring PMOS large-size array to half of the maximum adjustment range. The asynchronous control signal has no effect on the current state of the shift controller and is used to quickly provide a large current.

[0011] Furthermore, the negative input terminal of the clock-controlled comparator is connected to the reference voltage VREF, and the positive input terminal is connected to the feedback voltage VFB; the output terminal is based on a comparison signal of the reference voltage VREF and the feedback voltage VFB, and the comparison signal is signal 0 or signal 1, signal 0 means that the feedback voltage VFB is less than the reference voltage VREF, otherwise signal 1 is output; wherein the feedback voltage VFB is the voltage obtained by the voltage regulator from the output voltage VOUT to the ground.

[0012] Further, the counter in the partial stability detection circuit receives the comparison signal of the clock control comparator and monitors the consistency of the comparison signal in two consecutive clock cycles;

[0013] When the comparison signal is inconsistent in two consecutive clock cycles, the count value of the counter is reset to 0; when the comparison signal is continuously consistent, the counter increases its count value; based on whether the count value exceeds the preset threshold, the corresponding Cnt signal is output, and the shift control circuit is quickly or slowly adjusted according to the Cnt signal.

[0014] Furthermore, the sequence detector in the partial stability detection circuit is used to analyze the comparison signal of the clock control comparator, determine whether the set sequence state is met according to the output sequence of the comparison signal, and output the corresponding mode signal to analyze the stability state of the circuit.

[0015] Furthermore, the shift control circuit includes a shift controller, a small-size array of PMOS switches and a large-size array of PMOS switches; the input end of the shift controller is respectively connected to a counter, a sequence detector and a clock control comparator, for obtaining a current comparison signal, a Cnt signal and a mode signal; the output end of the shift controller is connected to the PMOS switch array, wherein a coarse-loop adjustment control in the shift controller is connected to the large-size array of PMOS switches, and a fine-loop adjustment control is connected to the small-size array of PMOS switches; and when the small-size array of PMOS switches is adjusted, a carry signal FD is triggered, and the coarse-loop adjustment control is entered to perform coarse-loop adjustment until the mode signal enters a stable state, and the fine-loop adjustment control is switched back to perform fine-loop adjustment.

[0016] Furthermore, the fine loop adjustment control includes a fine loop slow adjustment unit and a fine loop fast adjustment unit, and when the carry signal FD is not triggered or the coarse loop adjustment is switched to the fine loop adjustment, fast adjustment and slow adjustment are performed according to the Cnt signal; wherein,

[0017] When the Cnt signal does not reach the preset threshold, slow adjustment is performed, and the adjustment step of the small-size array of PMOS switches is reset to a minimum step of 1 according to the comparison signal;

[0018] When the Cnt signal reaches a preset threshold, a rapid adjustment is performed, and the adjustment step length of the PMOS switch small-size array is set to a fixed step length according to the comparison signal, and the fixed step length is a natural number greater than 1.

[0019] Furthermore, the coarse loop adjustment control includes a coarse loop slow adjustment unit and a coarse loop fast adjustment unit. When the carry signal FD is triggered, fast adjustment and slow adjustment are performed according to the Cnt signal; wherein,

[0020] When the Cnt signal does not reach the preset threshold, slow adjustment is performed, and the adjustment step of the large-size array of PMOS switches is reset to the minimum step of 1 according to the comparison signal, and the step of the small-size array of PMOS switches is set to half of the total step;

[0021] When the Cnt signal reaches the preset threshold, rapid adjustment is performed. The adjustment step of the large-size array of PMOS switches is set to a fixed step according to the comparison signal, and the fixed step is a natural number greater than 1; and the step of the small-size array of PMOS switches is set to half of the total step.

[0022] Furthermore, two groups of feedforward auxiliary PMOS are included, and corresponding small-sized or large-sized feedforward auxiliary PMOS are used according to the fine-loop adjustment unit or the coarse-loop adjustment unit in the shift control circuit to prevent the oscillation mode from being too high to be detected by the sequence detector.

[0023] Furthermore, a load capacitor and a load resistor are included to smooth the output voltage VOUT and reduce high-frequency noise.

[0024] Based on the same inventive concept, the present invention provides a low-ripple fast-response digital LDO circuit control method, which uses the fast-response digital LDO circuit as described above for control, and the method includes:

[0025] Step S1: obtaining a comparison signal of a clock-controlled comparator comparing a feedback voltage VFB and a reference voltage VREF, wherein the feedback voltage VFB is obtained by dividing the output voltage VOUT; a counter and a sequence detector in a partial stability detection circuit obtain corresponding Cnt signals and mode signals according to the comparison signal;

[0026] Step S2: Determine whether the mode signal output by the sequence detection is 1;

[0027] Step S3: When the mode signal is 1, the circuit is in a stable state; when the mode signal is 0, the shift control circuit performs fine loop regulation, determines the regulation speed and logic according to the Cnt signal and the comparison signal, and suppresses steady-state oscillation through a small-sized feedforward auxiliary PMOS; wherein,

[0028] When the Cnt signal is 0, the counter value does not reach the preset threshold value and performs slow adjustment, resetting the adjustment step of the PMOS switch small-size array to the minimum step of 1; until the mode signal is 1 to reach a stable state or the Cnt signal is 1 to enter the fast adjustment of the fine loop adjustment;

[0029] When the Cnt signal is 1, the value of the counter reaches the preset threshold value for rapid adjustment, and the adjustment step of the PMOS switch small-size array is set to a fixed step length, which is a natural number greater than 1, and the step length is the number of switches; until the Cnt signal is 0 and enters the slow adjustment of the fine loop adjustment or the switches in the PMOS switch small-size array are all in the open state, the carry signal FD is triggered;

[0030] Step S3: the shift control circuit switches from fine loop regulation to coarse loop regulation according to the detected carry signal FD; determines the regulation speed and logic according to the Cnt signal and the comparison signal, and suppresses steady-state oscillation through a large-size feedforward auxiliary PMOS; wherein,

[0031] When the Cnt signal is 0, the counter value does not reach the preset threshold value for slow adjustment, and the adjustment step of the large-size array of PMOS switches is reset to the minimum step of 1; and the number of switches in the small-size array of PMOS switches is set to half of the total number; until the Cnt signal is 1 to enter the fast adjustment of the coarse loop adjustment or the mode signal is 1 to return to the fine loop adjustment, and a stable state is reached.

[0032] When the Cnt signal is 1, the value of the counter reaches the preset threshold and is quickly adjusted. The adjustment step of the small-size array of PMOS switches is set to a fixed step, the fixed step is a natural number greater than 1, and the number of switches in the small-size array of PMOS switches is set to half of the total number; it is adjusted to the slow adjustment of the coarse loop adjustment until the mode signal is 1 and returns to the fine loop adjustment to reach a stable state.

[0033] Step S4: During the adjustment process, the asynchronous control loop outputs an asynchronous control signal AS_ctrl according to the detected output voltage VOUT drop reaching a preset value, and directly sets the large-size array of PMOS switches to open half without affecting the state of the shift controller.

[0034] Compared with the prior art, the present invention has at least one of the following technical effects:

[0035] The present invention can solve the ripple problem of traditional digital LDO, and improve the accuracy of output voltage while ensuring fast response. The sequence detector realized by digital circuit determines whether to enter a stable state, so as to switch the coarse loop regulation to the fine loop regulation with lower ripple, and realize low ripple output; the magnitude of load change is determined by counting the number of Comp_out signals of the same comparator output result through the counter, and then the step size of the corresponding loop shift control logic is adaptively adjusted to realize fast response. The use of window comparators and multiple reference voltages is avoided, the design difficulty is simplified, and the error caused by the offset between multiple comparators is eliminated. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the technical solution of the embodiment of the present invention, the following is a brief introduction to the drawings required for describing the embodiment:

[0037] Figure 1 A circuit diagram of a low-ripple fast-response digital LDO circuit of the present invention;

[0038] Figure 2 The figure is a flowchart of the steps of the fast response digital LDO circuit control method of the present invention. DETAILED DESCRIPTION

[0039] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and specific implementation methods. It should be understood that the specific implementation methods described herein are only used to explain the present invention and are not used to limit the present invention.

[0040] Example 1

[0041] Digital LDOs play a key role in modern electronic devices, especially in applications that require precise voltage control. Compared with traditional analog LDOs (ALDOs), digital LDOs are favored because they require a smaller power tube area, better process scalability, and fewer stability issues when handling the same load current. However, a major challenge facing digital LDOs is their high steady-state ripple and relatively low power supply rejection ratio (PSRR), which limits their application in high-precision power management systems.

[0042] Traditional digital LDO consists of a clock-controlled comparator, a bidirectional shift register, and a PMOS switch array. The output voltage VOUT is compared with the reference voltage VREF through a clock-controlled comparator, and the comparison result is output to the bidirectional shift register, which controls the shift direction of the bidirectional shift register and outputs a digital '0' or '1'; thus, one PMOS in the PMOS array is turned on or off each time to adjust the output voltage. The PMOS array consists of PMOS of the same size, which is in the linear region when turned on and in the cut-off region when turned off.

[0043] In view of the limitations of existing technologies, there are currently two technical solutions to solve this problem:

[0044] The first solution is to add a large capacitor to the output end to reduce ripple based on the traditional digital LDO. Although this method is simple and effective, it has an obvious disadvantage that the capacitor occupies a large area. If it is implemented inside the chip, it will take up more chip space; and the external large capacitor may affect the convenience of customers using the IP. In addition, the added output capacitor may also change the pole position of the circuit and affect stability.

[0045] The second solution is a low-ripple fast-response digital LDO. On the basis of the traditional digital LDO, it usually adds a coarse and fine loop adjustment mode and uses two groups of PMOS arrays of different sizes. The coarse loop uses a large-size PMOS to obtain a fast response, and the fine loop uses a small-size PMOS to obtain a low ripple; the mode switching uses a voltage window detector composed of two clocked comparators and an XOR gate control. The output voltage VOUT is coarsely regulated when it is outside the voltage window, and finely regulated when it is within the voltage window. Although this method improves performance and reduces ripple, it also brings problems of increased design complexity and power consumption, especially the need for additional reference voltages and multiple comparators, which increases the overall cost and implementation difficulty of the circuit. For example, two additional clock-controlled comparators are required, which increases power consumption, and there are different offset voltages between the clock-controlled comparators, which will lead to reduced accuracy. Secondly, two additional reference voltages VREFH and VREFL are required as inputs of additional clock-controlled comparators, and the additional reference voltages need to be obtained through other circuits, which increases the complexity of the design.

[0046] Based on the in-depth analysis and understanding of the problems in the prior art, the inventors proposed a low-ripple, fast-response digital LDO circuit and control method. Digital control logic is used, combined with a clock-controlled comparator, a partial stability detection circuit, a shift switch circuit and an asynchronous control loop to improve the response speed and stability while reducing ripple. The core idea of ​​the invention is to dynamically adjust the coarse and fine loops of voltage regulation through digital signal processing, so as to quickly adapt to load changes and maintain voltage stability. Through the analysis of the counter and sequence detector, it is possible to more accurately judge whether the current state is stable, and select the most appropriate regulation strategy (thin loop or coarse loop regulation) to achieve efficient voltage management. In addition, the use of complex window comparators and multiple reference voltages is avoided, which simplifies the circuit design and reduces the number of components. The specific implementation plan is as follows:

[0047] like Figure 1 As shown, the present invention provides a low-ripple fast-response digital LDO circuit, comprising: a clock-controlled comparator, a partial stability detection circuit, a shift-control switch circuit and an asynchronous control loop;

[0048] A clock-controlled comparator, used for real-time monitoring of the deviation between the feedback voltage VFB and the reference voltage VREF, and outputting a comparison signal;

[0049] The partial stability detection circuit, including a counter and a sequence detector, is digitally designed; the counter sends a Cnt signal based on the continuity of the comparison signal to detect the continuity of the output signal; the sequence detector sends a mode signal based on the output mode of the output signal to evaluate whether the output signal reaches a preset target stable state;

[0050] The shift control circuit dynamically controls the coarse and fine loops and adjusts the PMOS switch array to achieve voltage regulation according to the Cnt signal and the mode signal provided by the partial stability detection circuit and the internal carry signal FD. When the shift control circuit detects the carry signal FD, it switches from fine loop regulation to coarse loop regulation to speed up the regulation speed.

[0051] The input end of the clock control comparator is respectively connected to the feedback voltage VFB and the reference voltage VREF, and the output end is respectively connected to the shift control circuit and the counter and sequence detector in the partial stability monitoring circuit for outputting a comparison signal; the shift control circuit is connected to the partial stability monitoring circuit and the clock control comparator, and determines whether the voltage state is stable according to the output mode signal and Cnt signal. When the voltage state does not reach the stable state, the small-size array of the PMOS switch is fine-loop regulated. When the small-size array of the PMOS switch is regulated and has not reached the stable state, the carry signal FD is triggered, and the output voltage is coarse-loop regulated in combination with the large-size array of the PMOS switch to quickly respond to the change of the feedback voltage VFB, and switch to fine-loop regulation according to the mode signal to reach the stable state.

[0052] The input end of the asynchronous control loop is connected to the output voltage VOUT, and the output end of the asynchronous control loop is connected to the shift controller. When the output voltage variation reaches a preset value, a large undershoot is detected, and an asynchronous control signal AS_ctrl is output. The asynchronous control signal AS_ctrl directly sets the coarse-ring PMOS large-size array to half of the maximum adjustment range. The asynchronous control signal has no effect on the current state of the shift controller and is used to quickly provide a large current.

[0053] Furthermore, the negative input terminal of the clock-controlled comparator is connected to the reference voltage VREF, and the positive input terminal is connected to the feedback voltage VFB; the output terminal is based on a comparison signal of the reference voltage VREF and the feedback voltage VFB, and the comparison signal is signal 0 or signal 1, signal 0 means that the feedback voltage VFB is less than the reference voltage VREF, otherwise signal 1 is output; wherein the feedback voltage VFB is the voltage obtained by the voltage regulator from the output voltage VOUT to the ground.

[0054] Further, the counter in the partial stability detection circuit receives the comparison signal of the clock control comparator and monitors the consistency of the comparison signal in two consecutive clock cycles;

[0055] When the comparison signal is inconsistent in two consecutive clock cycles, the count value of the counter is reset to 0; when the comparison signal is continuously consistent, the counter increases its count value; based on whether the count value exceeds the preset threshold, the corresponding Cnt signal is output, and the shift control circuit is quickly or slowly adjusted according to the Cnt signal.

[0056] Furthermore, the sequence detector in the partial stability detection circuit is used to analyze the comparison signal of the clock control comparator, determine whether the set sequence state is met according to the output sequence of the comparison signal, and output the corresponding mode signal to analyze the stability state of the circuit.

[0057] Furthermore, the shift control circuit includes a shift controller, a small-size array of PMOS switches and a large-size array of PMOS switches; the input end of the shift controller is respectively connected to a counter, a sequence detector and a clock control comparator, for obtaining a current comparison signal, a Cnt signal and a mode signal; the output end of the shift controller is connected to the PMOS switch array, wherein a coarse-loop adjustment control in the shift controller is connected to the large-size array of PMOS switches, and a fine-loop adjustment control is connected to the small-size array of PMOS switches; and when the small-size array of PMOS switches is adjusted, a carry signal FD is triggered, and the coarse-loop adjustment control is entered to perform coarse-loop adjustment until the mode signal enters a stable state, and the fine-loop adjustment control is switched back to perform fine-loop adjustment.

[0058] Furthermore, the fine loop adjustment control includes a fine loop slow adjustment unit and a fine loop fast adjustment unit, and when the carry signal FD is not triggered or the coarse loop adjustment is switched to the fine loop adjustment, fast adjustment and slow adjustment are performed according to the Cnt signal; wherein,

[0059] When the Cnt signal does not reach the preset threshold, slow adjustment is performed, and the adjustment step of the small-size array of PMOS switches is reset to a minimum step of 1 according to the comparison signal;

[0060] When the Cnt signal reaches a preset threshold, a rapid adjustment is performed, and the adjustment step length of the PMOS switch small-size array is set to a fixed step length according to the comparison signal, and the fixed step length is a natural number greater than 1.

[0061] Furthermore, the coarse loop adjustment control includes a coarse loop slow adjustment unit and a coarse loop fast adjustment unit. When the carry signal FD is triggered, fast adjustment and slow adjustment are performed according to the Cnt signal; wherein,

[0062] When the Cnt signal does not reach the preset threshold, slow adjustment is performed, and the adjustment step of the large-size array of PMOS switches is reset to the minimum step of 1 according to the comparison signal, and the step of the small-size array of PMOS switches is set to half of the total step;

[0063] When the Cnt signal reaches the preset threshold, rapid adjustment is performed. The adjustment step of the large-size array of PMOS switches is set to a fixed step according to the comparison signal, and the fixed step is a natural number greater than 1; and the step of the small-size array of PMOS switches is set to half of the total step.

[0064] Furthermore, two groups of feedforward auxiliary PMOS are included, and corresponding small-sized or large-sized feedforward auxiliary PMOS are used according to the fine-loop adjustment unit or the coarse-loop adjustment unit in the shift control circuit to prevent the oscillation mode from being too high to be detected by the sequence detector.

[0065] Furthermore, a load capacitor and a load resistor are included to smooth the output voltage VOUT and reduce high-frequency noise.

[0066] Example 2

[0067] Based on the same inventive concept, the present invention provides a low-ripple fast-response digital LDO circuit control method, which uses the fast-response digital LDO circuit as described above for control, and the method includes:

[0068] Step S1: obtaining a comparison signal of a clock-controlled comparator comparing a feedback voltage VFB and a reference voltage VREF, wherein the feedback voltage VFB is obtained by dividing the output voltage VOUT; a counter and a sequence detector in a partial stability detection circuit obtain corresponding Cnt signals and mode signals according to the comparison signal;

[0069] Step S2: Determine whether the mode signal output by the sequence detection is 1;

[0070] Step S3: When the mode signal is 1, the circuit is in a stable state; when the mode signal is 0, the shift control circuit performs fine loop regulation, determines the regulation speed and logic according to the Cnt signal and the comparison signal, and suppresses steady-state oscillation through a small-sized feedforward auxiliary PMOS; wherein,

[0071] When the Cnt signal is 0, the counter value does not reach the preset threshold value and performs slow adjustment, resetting the adjustment step of the PMOS switch small-size array to the minimum step of 1; until the mode signal is 1 to reach a stable state or the Cnt signal is 1 to enter the fast adjustment of the fine loop adjustment;

[0072] When the Cnt signal is 1, the value of the counter reaches the preset threshold value for rapid adjustment, and the adjustment step of the PMOS switch small-size array is set to a fixed step length, which is a natural number greater than 1, and the step length is the number of switches; until the Cnt signal is 0 and enters the slow adjustment of the fine loop adjustment or the switches in the PMOS switch small-size array are all in the open state, the carry signal FD is triggered;

[0073] Step S3: the shift control circuit switches from fine loop regulation to coarse loop regulation according to the detected carry signal FD; determines the regulation speed and logic according to the Cnt signal and the comparison signal, and suppresses steady-state oscillation through a large-size feedforward auxiliary PMOS; wherein,

[0074] When the Cnt signal is 0, the counter value does not reach the preset threshold value for slow adjustment, and the adjustment step of the large-size array of PMOS switches is reset to the minimum step of 1; and the number of switches in the small-size array of PMOS switches is set to half of the total number; until the Cnt signal is 1 to enter the fast adjustment of the coarse loop adjustment or the mode signal is 1 to return to the fine loop adjustment, and a stable state is reached.

[0075] When the Cnt signal is 1, the value of the counter reaches the preset threshold and is quickly adjusted. The adjustment step of the small-size array of PMOS switches is set to a fixed step, the fixed step is a natural number greater than 1, and the number of switches in the small-size array of PMOS switches is set to half of the total number; it is adjusted to the slow adjustment of the coarse loop adjustment until the mode signal is 1 and returns to the fine loop adjustment to reach a stable state.

[0076] Step S4: During the adjustment process, the asynchronous control loop outputs an asynchronous control signal AS_ctrl according to the detected output voltage VOUT drop reaching a preset value, and directly sets the large-size array of PMOS switches to open half without affecting the state of the shift controller.

[0077] Example 3

[0078] like Figure 1 , 2 As shown, referring to the step flow chart showing an embodiment of the present invention, the present invention will be described in more detail below. This embodiment is proposed to fully and completely disclose the present technology so that those skilled in the art can fully understand the application scope and implementation details of the present invention, and more people related to the technical field can fully understand the scope of the present invention.

[0079] like Figure 1 As shown, this embodiment 1 proposes a low ripple fast response digital LDO circuit, which includes: a clock control comparator, a counter, a sequence detector, a shift controller (a coarse loop adjustment control and a fine loop adjustment control), two groups of PMOS switch arrays, two groups of feedforward auxiliary PMOS (the number is 2 each), an asynchronous control loop, and a load capacitor and a load resistor; wherein,

[0080] Counters, sequence detectors and shift controllers are designed using digital code, specifically:

[0081] The clock-controlled comparator has a negative input terminal connected to a reference voltage VREF, a positive input terminal connected to a feedback voltage VFB, and an output terminal connected to a counter, a sequence detector, a shift controller, and a feedforward auxiliary PMOS; the clock-controlled comparator compares the input feedback voltage and the reference voltage according to a predetermined clock cycle, and generates an output signal according to the comparison result. This process is triggered based on a specific time point of each clock cycle to determine the synchronization and timing accuracy of the operation.

[0082] The counter counts cumulatively according to the output signal comp_out of the clock control comparator. If the comparison results are the same, the counter is incremented by 1. When the count value exceeds the set value, a cnt='1' signal is output to increase the shift step of the shift control logic. If the Comp_out of the two clock cycles before and after is different, cnt='0', and the step is reset to the minimum step of 1. The step is directly related to the switching operation of the PMOS switch array, that is, the step indicates the number of PMOS switches adjusted in each adjustment cycle, thereby adjusting the fast or slow changes in the output voltage.

[0083] The feedforward auxiliary PMOS is used to reduce the oscillation mode in steady state to prevent the oscillation mode from being too high to be detected by the sequence detector. According to the control running in the shift controller, a large or small feedforward PMOS is selected, that is, a large feedforward PMOS is selected for the coarse loop adjustment control, and a small feedforward PMOS is selected for the fine loop adjustment control;.

[0084] The sequence detector is used to detect whether the comp_out signal meets the set sequence state, such as: if the comparison result meets the sequence 101010, the Mode = '1' signal is output to determine whether it has entered a stable state; the shift controller selects the coarse loop adjustment control or the fine loop adjustment control to shift and outputs the corresponding Ctrl signal according to the Mode signal and whether the carry signal FD is triggered, changes the switch state of the corresponding PMOS array, and selects the shift step according to the Cnt signal; the PMOS array has two different sizes, the large PMOS_L size is used for fast adjustment, and the small PMOS_S size is used to achieve low ripple. The asynchronous control loop belongs to an asynchronous loop and is used to monitor the changes of VOUT in real time.

[0085] The shift controller dynamically adjusts the coarse and fine loop control and adjusts the PMOS switch array to achieve voltage regulation based on the Cnt signal and the mode signal provided by the partial stability detection circuit. When the carry signal FD is detected, it can quickly switch from the fine loop regulation to the coarse loop regulation, significantly improving the regulation speed and reducing the ripple. The digital LDO circuit of the present invention significantly reduces the output voltage ripple while providing a fast response, and optimizes the overall performance of the circuit, especially in terms of low ripple and fast response. In addition, the design simplifies the circuit structure, reduces the manufacturing cost, and improves the reliability and stability of the circuit.

[0086] It should be specifically explained that, in this circuit diagram, the signal for switching the coarse and thin rings is based on the mode signal and the carry signal FD. When switching from the thin ring to the coarse ring adjustment, the adjustment is made based on the carry signal FD, and when switching from the coarse ring to the fine ring adjustment, the switching is made based on the mode signal switching back to 1.

[0087] Therefore, the shift controller controls the adjustment process of the thick and thin rings by specifically adjusting and switching according to the mode signal, comparison signal, Cnt signal, and carry signal FD. When the mode signal is 0 and unstable, the Cnt signal is 0 and enters the cyclic slow adjustment. When the Cnt signal is 0 and the mode signal is 1, it enters the stable state. When the Cnt signal reaches 1, it enters the fast adjustment of the thin ring, and the shift step of the small-size PMOS switch array increases until the Cnt signal reaches 0 and enters the slow adjustment step of the thin ring; or all the switches in the small-size PMOS switch array are turned on, the Cnt signal reaches 0 and the carry signal FD is triggered, and it enters the thick ring adjustment process. During this process, the number of switches in the small-size PMOS switch array is set to be half open, and corresponding fast and slow adjustments are made. In the digital LDO, this shift controller is used to adjust the state of the PMOS switch array according to the output signal of the comparator. The shift operation is synchronized with the clock signal, and the entire circuit operates according to the clock cycle. Ensure the sequentiality and timeliness of the voltage adjustment action.

[0088] For the specific step process, please refer to Figure 2 , such as Figure 2 shown. The specific voltage stabilization process is as follows: Initially in the stable state of the thin ring, when a small change occurs in the output voltage VOUT due to load changes, if VFB < VREF at this time, Comp_out outputs '0'. At this time, both the counter and the sequence detector output '0', and it enters the slow adjustment mode of the thin ring. The Comp_out signal controls the shift control logic to shift the output of Ctrl_F by one '0', that is, turn on a small-size PMOS. If VOUT is still less than VREF, this process is repeated in the next clock cycle; after executing multiple times, if the number of consecutive '0's counted by the counter exceeds the set value (8), then Cnt = '1', and it enters the fast adjustment mode of the thin ring. The shift step of Ctrl_F increases (increases to 4), and continues to adjust until the output signal of the comparator flips, Cnt becomes '0' again, and the step size also becomes the minimum step size, and continues to adjust until the sequence detector detects the sequence of 101010, indicating that it has entered the stable state of the thin ring, and the Mode signal is set to '1', and the adjustment ends.

[0089] When the fine loop adjustment range cannot meet the requirements and has not returned to the fine loop stable state, all M PMOS_S in the small-size array of PMOS switches are adjusted and turned on to trigger the FD carry signal, and the coarse loop is switched to according to the shift control logic, and the fine loop control signal is set to turn on half of the PMOS_S; the subsequent adjustment process is exactly the same as the fine loop, except that the output signal becomes Ctrl_C. After several cycles, when the sequence detector detects the 101010 sequence, it means that the coarse loop has reached a stable state, Mode = '1', and the shift control logic is switched back to the fine loop, that is, the Ctrl_F signal is output, and the fine loop enters a stable state here after adjustment, thereby reducing the output voltage ripple.

[0090] During the whole process of regulation, when the output voltage VOUT drops rapidly and greatly, it means that the LDO needs to provide a large current. Therefore, the asynchronous control loop outputs the asynchronous control signal As_ctrl to control the coarse-loop shift logic, directly opening the coarse-loop PMOS by half to quickly provide current to prevent a large undershoot voltage.

[0091] It should be specifically explained that the asynchronous control loop sets a judgment threshold value based on the real-time value of the output voltage VOUT monitored in real time. For example, when the output voltage VOUT drops by more than a specific percentage or absolute value (such as 5% or 0.1V) within a set short time, such as a few microseconds to a few milliseconds, the asynchronous control loop is triggered to output a control signal for adjusting the PMOS array to an appropriate state to quickly compensate for the voltage drop, thereby ensuring power supply stability.

[0092] During the full-process adjustment of the coarse and fine loops by the shift controller, the adjustment of the PMOS switch array and the asynchronous control loop is carried out independently and will not affect each other. The adjustment of the PMOS switch array by the shift controller is based on clock control, while the asynchronous control loop is independent of the above clock control process and is used to cope with sudden large current demands or rapid voltage drops. The asynchronous control loop monitors the output voltage in real time and quickly sends a short pulse control signal when the voltage drops to the preset threshold, directly controlling a part of the large-size PMOS array to provide the necessary current support. This process has an extremely short response time, usually less than one clock cycle, so it does not interfere with the regular adjustment activities of the fine and coarse loops controlled by the clock. Therefore, the asynchronous control loop can quickly respond and adjust the PMOS array to adapt to the sharp change in voltage, but its independent control mechanism ensures that it will not affect the stable adjustment process of the fine and coarse loops, and ensures that the system can smoothly return to the normal adjustment mode after emergency intervention. This seamless switching ensures the stable operation of the system under different requirements and maintains performance even in the face of extreme voltage changes.

[0093] Although the present invention has been disclosed as above in the form of a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art may make possible changes and modifications to the technical solution of the present invention by using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention shall fall within the protection scope of the technical solution of the present invention.

Claims

1. A low ripple fast response digital LDO circuit, characterized in that: include: Clock control comparator, partial stability detection circuit, shift control switch circuit and asynchronous control loop; The clock-controlled comparator is used to monitor the deviation between the feedback voltage VFB and the reference voltage VREF in real time and output a comparison signal; The partial stability detection circuit includes a counter and a sequence detector, both of which are digitally designed; wherein the counter sends a Cnt signal based on the continuity of the comparison signal to detect the continuity of the output signal; and the sequence detector sends a mode signal based on the output mode of the output signal to evaluate whether the output signal reaches a preset target stable state. The shift control circuit dynamically controls and adjusts the PMOS switch array according to the Cnt signal and the mode signal provided by the partial stability detection circuit and the internal carry signal FD to achieve voltage regulation. When the shift control circuit detects the carry signal FD, it switches from fine loop regulation to coarse loop regulation to speed up the regulation speed. The input end of the clock control comparator is respectively connected to the feedback voltage VFB and the reference voltage VREF, and the output end is respectively connected to the shift control circuit and the counter and the sequence detector in the partial stability monitoring circuit, so as to output the comparison signal; the shift control circuit is connected to the partial stability monitoring circuit and the clock control comparator, and judges whether the voltage state is stable according to the output mode signal and the Cnt signal, and when the voltage state does not reach the stable state, the small-size array of PMOS switches is fine-loop regulated, and when the small-size array of PMOS switches is regulated and does not reach the stable state, the carry signal FD is triggered, and the output voltage is coarse-loop regulated in combination with the large-size array of PMOS switches to quickly respond to the change of the feedback voltage VFB, and switches to fine-loop regulation according to the mode signal to reach the stable state; The input end of the asynchronous control loop is connected to the output voltage VOUT, and the output end of the asynchronous control loop is connected to the shift controller. When the output voltage variation reaches a preset value, a large undershoot is detected, and the asynchronous control signal AS_ctrl is output. The asynchronous control signal AS_ctrl directly sets the coarse-ring PMOS large-size array to half of the maximum adjustment range. The asynchronous control signal has no effect on the current state of the shift controller and is used to quickly provide a large current.

2. The fast response digital LDO circuit according to claim 1, characterized in that: The negative input terminal of the clock-controlled comparator is connected to the reference voltage VREF, and the positive input terminal is connected to the feedback voltage VFB; the output terminal is based on a comparison signal of the reference voltage VREF and the feedback voltage VFB, and the comparison signal is signal 0 or signal 1, and the signal 0 means that the feedback voltage VFB is less than the reference voltage VREF, otherwise the signal 1 is output; wherein the feedback voltage VFB is the voltage obtained by the voltage regulator connected from the output voltage VOUT to the ground.

3. The fast response digital LDO circuit according to claim 2, characterized in that: The counter in the partial stability detection circuit receives the comparison signal of the clock control comparator and monitors the consistency of the comparison signal in two consecutive clock cycles; When the comparison signal is inconsistent in the two consecutive clock cycles, the count value of the counter is reset to 0; when the comparison signal is continuously consistent, the counter increases its count value; The corresponding Cnt signal is output based on whether the count value exceeds a preset threshold, and the shift control circuit is quickly adjusted or slowly adjusted according to the Cnt signal.

4. The fast response digital LDO circuit according to claim 2, characterized in that: The sequence detector in the partial stability detection circuit is used to analyze the comparison signal of the clock control comparator, determine whether the set sequence state is met according to the output sequence of the comparison signal, and output the corresponding mode signal to analyze the stability state of the circuit.

5. The fast response digital LDO circuit according to claim 2, characterized in that: The shift control circuit includes the shift controller, the small-size array of PMOS switches and the large-size array of PMOS switches; the input end of the shift controller is respectively connected to the counter, the sequence detector and the clock control comparator, for obtaining the current comparison signal, the Cnt signal and the mode signal; the output end of the shift controller is connected to the PMOS switch array, wherein the coarse-loop adjustment control in the shift controller is connected to the large-size array of PMOS switches, and the fine-loop adjustment control is connected to the small-size array of PMOS switches; and when the small-size array of PMOS switches is adjusted, the carry signal FD is triggered, the coarse-loop adjustment control is entered to perform the coarse-loop adjustment until the mode signal enters the stable state, and the fine-loop adjustment control is switched back to perform the fine-loop adjustment.

6. The fast response digital LDO circuit according to claim 3, characterized in that: The fine loop adjustment control comprises a fine loop slow adjustment unit and a fine loop fast adjustment unit, and when the carry signal FD is not triggered or the coarse loop adjustment is switched to the fine loop adjustment, the fast adjustment and the slow adjustment are performed according to the Cnt signal; wherein, When the Cnt signal does not reach the preset threshold, the slow adjustment is performed, and the adjustment step of the PMOS switch small-size array is reset to a minimum step of 1 according to the comparison signal; When the Cnt signal reaches the preset threshold, the rapid adjustment is performed, and the adjustment step length of the PMOS switch small-size array is set to a fixed step length according to the comparison signal, and the fixed step length is a natural number greater than 1.

7. The fast response digital LDO circuit according to claim 3, characterized in that: The coarse loop adjustment control comprises a coarse loop slow adjustment unit and a coarse loop fast adjustment unit. When the carry signal FD is triggered, the fast adjustment and the slow adjustment are performed according to the Cnt signal; wherein, When the Cnt signal does not reach the preset threshold, the slow adjustment is performed, the adjustment step of the large-size array of PMOS switches is reset to a minimum step of 1 according to the comparison signal, and the step of the small-size array of PMOS switches is set to half of the total step; When the Cnt signal reaches the preset threshold, the rapid adjustment is performed, and the adjustment step of the large-size array of PMOS switches is set to a fixed step according to the comparison signal, and the fixed step is a natural number greater than 1; and the step of the small-size array of PMOS switches is set to half of the total step.

8. The fast response digital LDO circuit according to claim 1, characterized in that: It also includes two groups of feedforward auxiliary PMOS, which use corresponding small or large-sized feedforward auxiliary PMOS according to the fine loop adjustment unit or the coarse loop adjustment unit in the shift control circuit to prevent the oscillation mode from being too high to be detected by the sequence detector.

9. The fast response digital LDO circuit according to claim 1, characterized in that: A load capacitor and a load resistor are also included to smooth the output voltage VOUT and reduce high-frequency noise.

10. A low ripple fast response digital LDO circuit control method, characterized in that: The method is controlled by using any one of the fast response digital LDO circuits as claimed in claims 1 to 9, and comprises: Step S1: obtaining a comparison signal of a clock-controlled comparator comparing a feedback voltage VFB and a reference voltage VREF, wherein the feedback voltage VFB is obtained by dividing the output voltage VOUT; a counter and a sequence detector in a partial stability detection circuit obtain corresponding Cnt signals and mode signals according to the comparison signal; Step S2: determining whether the mode signal output by the sequence detection is 1; Step S3: When the mode signal is 1, the circuit is in a stable state; when the mode signal is 0, the shift control circuit performs fine loop regulation, determines the regulation speed and logic according to the Cnt signal and the comparison signal, and suppresses steady-state oscillation through a small-sized feedforward auxiliary PMOS; wherein, When the Cnt signal is 0, the value of the counter does not reach the preset threshold value and performs slow adjustment, resetting the adjustment step of the PMOS switch small-size array to the minimum step of 1; until the mode signal is 1 and reaches a stable state or the Cnt signal is 1 and enters the fast adjustment of the fine loop adjustment; When the Cnt signal is 1, the value of the counter reaches the preset threshold value for rapid adjustment, and the adjustment step of the PMOS switch small-size array is set to a fixed step, the fixed step is a natural number greater than 1, and the step is the number of switches; until the Cnt signal is 0 and enters the slow adjustment of the fine loop adjustment or the switches in the PMOS switch small-size array are all in the open state, the carry signal FD is triggered; Step S3: the shift control circuit switches from the fine loop regulation to the coarse loop regulation according to the detected carry signal FD; determines the regulation speed and the logic according to the Cnt signal and the comparison signal, and suppresses steady-state oscillation through a large-size feedforward auxiliary PMOS; wherein, When the Cnt signal is 0, the value of the counter does not reach the preset threshold value, and the slow adjustment is performed, and the adjustment step of the large-size array of PMOS switches is reset to the minimum step of 1; and the number of switches in the small-size array of PMOS switches is set to half of the total number; until the Cnt signal is 1 and enters the fast adjustment of the coarse loop adjustment or reaches the mode signal of 1 to return to the fine loop adjustment, and reaches the stable state; When the Cnt signal is 1, the value of the counter reaches the preset threshold value to perform the fast adjustment, set the adjustment step of the PMOS switch small-size array to a fixed step, the fixed step is the natural number greater than 1, and set the number of switches in the PMOS switch small-size array to half of the total number; adjust to the slow adjustment of the coarse loop adjustment, until the mode signal is 1 and returns to the fine loop adjustment to reach the stable state; Step S4: During the adjustment process, the asynchronous control loop outputs the asynchronous control signal AS_ctrl according to the detected output voltage VOUT drop reaching a preset value, and directly sets the large-size array of PMOS switches to open half without affecting the state of the shift controller.

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