Binary translation method and device, electronic equipment and readable storage medium

Abstract

The embodiment of the invention provides a binary translation method and device, electronic equipment and a readable storage medium, and the method comprises the steps: in a binary translation process, recognizing whether a current instruction is a target calling instruction; the target calling instruction is used for calling a target function, and the target function is used for obtaining an instruction pointer; if the current instruction is identified as a target calling instruction, performing optimization translation on the target calling instruction; the optimization translation is used for translating the target calling instruction into an immediate operand loading instruction, and the immediate operand loading instruction is used for loading an address of a next instruction of the current instruction to a specified register as an immediate operand. According to the method and the device, redundant instructions generated by semantic translation can be reduced, and the segmentation times of TB can be reduced, so that the translation efficiency of a dynamic translator and the operation efficiency of a translated program are improved.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a binary translation method, device, electronic device and readable storage medium. Background Art

[0002] Binary translation refers to the use of binary translation technology to run an application of a certain ISA (Instruction Set Architecture) (such as an x86 application) on another ISA (such as LoongArch) through binary translation to achieve cross-architecture and cross-instruction set program compatibility.

[0003] The instruction pointer (Instruction Pointer), also known as the program counter (Program Counter, PC for short), is a special register that stores the address of the next instruction to be executed in the executing program. In most computer architectures, the instruction pointer is a key register that helps control the flow of the program and guides the processor to execute the correct sequence of instructions.

[0004] In the x86 instruction set architecture, a function call instruction is required to obtain an instruction pointer. However, binary translation of a large number of function call instructions used to obtain instruction pointers will generate a large number of redundant instructions, which will affect the translation efficiency and the running efficiency of the translated program. Summary of the invention

[0005] In view of the above problems, an embodiment of the present invention is proposed to provide a binary translation method that overcomes the above problems or at least partially solves the above problems, which can reduce redundant instructions generated by semantic translation and reduce the number of TB segmentation times, thereby improving the translation efficiency of the dynamic translator and improving the running efficiency of the translated program.

[0006] Correspondingly, the embodiment of the present invention also provides a binary translation device, an electronic device, and a computer program product to ensure the implementation and application of the above method.

[0007] In a first aspect, an embodiment of the present invention discloses a binary translation method, the method comprising:

[0008] In the binary translation process, identifying whether the current instruction is a target call instruction; the target call instruction is used to call a target function, and the target function is used to obtain an instruction pointer;

[0009] If the current instruction is identified as a target call instruction, the target call instruction is optimized and translated; the optimized translation is used to translate the target call instruction into an immediate load instruction, and the immediate load instruction is used to load the address of the next instruction of the current instruction as an immediate value into a specified register.

[0010] In a second aspect, an embodiment of the present invention discloses a binary translation device, the device comprising:

[0011] An instruction recognition module is used to identify whether the current instruction is a target call instruction during the binary translation process; the target call instruction is used to call a target function, and the target function is used to obtain an instruction pointer;

[0012] An optimization translation module is used to optimize the translation of the target call instruction if the current instruction is identified as a target call instruction; the optimization translation is used to translate the target call instruction into an immediate value load instruction, and the immediate value load instruction is used to load the address of the next instruction of the current instruction as an immediate value into a specified register.

[0013] In the third aspect, an embodiment of the present invention discloses an electronic device, comprising: a processor, a memory, a communication interface and a communication bus, wherein the processor, the memory and the communication interface communicate with each other through the communication bus; the memory is used to store at least one executable instruction, and the executable instruction enables the processor to execute the steps of the binary translation method as described in any of the above.

[0014] In a fourth aspect, an embodiment of the present invention discloses a readable storage medium, on which a program or instruction is stored, and when the program or instruction is executed by a processor, the binary translation method as described in any of the above can be implemented.

[0015] In a fifth aspect, an embodiment of the present invention discloses a computer program product, including a computer program, which, when executed by a processor, performs the steps of any of the aforementioned binary translation methods.

[0016] The embodiments of the present invention include the following advantages:

[0017] In the binary translation process, the embodiment of the present invention identifies whether the current instruction is a target call instruction, and the target call instruction is used to call the target function of the instruction pointer. In the case of identifying the target call instruction, the target call instruction is optimized and translated directly into an immediate load instruction for loading the address of the next instruction (i.e., the instruction pointer), rather than translating the target call instruction step by step based on semantics. The traditional method of step-by-step translation based on semantics requires that each instruction contained in this target call instruction and the target function called by this target call instruction be translated separately, which not only generates redundant instructions, but also increases the number of TB segmentations due to the need for the function call instruction to end as the TB, thereby affecting the translation efficiency and the operating efficiency of the translated program. Through the optimized translation of the embodiment of the present invention, it is only necessary to directly translate this target call instruction into an immediate load instruction to achieve the effect of obtaining the instruction pointer, which can not only reduce the redundant instructions generated by the semantic translation, but also reduce the number of TB segmentations due to the need for the immediate load instruction to end as the TB, thereby improving the translation efficiency and the operating efficiency of the translated program. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 It is a schematic diagram of a binary translation architecture of the present invention;

[0019] Figure 2 is a flowchart of a binary translation method embodiment of the present invention;

[0020] Figure 3 is a structural block diagram of an embodiment of a binary translation device of the present invention;

[0021] Figure 4 It is a schematic diagram of the structure of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0022] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0023] The terms "first", "second", etc. in the specification and claims of the present invention are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable when appropriate, so that the embodiments of the present invention can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first", "second", etc. are generally of one type, and the number of objects is not limited. For example, the first object can be one or more. In addition, the term "and / or" in the specification and claims is used to describe the association relationship of associated objects, indicating that three relationships can exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. In the embodiments of the present invention, the term "multiple" refers to two or more, and other quantifiers are similar.

[0024] Binary translation technology can solve the problem of binary-level applications running across instruction set architectures. Specifically, binary translation technology can convert instruction sequences in one instruction set architecture into instruction sequences in another instruction set architecture.

[0025] Cross-architecture binary translation will bring about a large performance loss and lead to low efficiency, which is largely caused by the differences in instructions between different architectures. Through some translation optimization technologies, such as delayed generation of flag information and elimination of redundant instructions, the generation of redundant instructions can be reduced as much as possible, and the efficiency of the translated binary program can be improved.

[0026] Reference Figure 1 , shows a schematic diagram of a binary translation architecture, which includes a disassembler, an optimizer, a translator, and an assembler. First, the source program is input into the disassembler for disassembly and cutting into basic blocks, and the information of each instruction in each basic block is obtained; the optimizer analyzes the information obtained after disassembly, finds out the possible instruction sequences to be optimized, and marks them; the translator translates each instruction according to the information obtained after disassembly, and performs some optimizations during the translation process with the assistance of the marking information provided by the optimizer; finally, the optimized and translated instructions are sent to the assembler for assembly.

[0027] Wherein, the source program refers to the program to be binary translated, and the source program can be any type of application program. The source platform refers to the machine platform that can run the source program, also known as the client. The processor of the source platform can be a processor based on the first instruction set architecture. The first instruction set architecture can be, for example, an x86 instruction set architecture, or an arm instruction set architecture (such as arm64), etc. The source program is a program developed based on the first instruction set architecture, so the source program can run normally on the source platform. The target platform is a machine platform to which the source program is desired to be transplanted. In some embodiments, the target platform can also be referred to as a host machine. The processor of the target platform can be a processor based on a second instruction set architecture. The second instruction set architecture is a different instruction set architecture from the first instruction set architecture. For example, the first instruction set architecture is an x86 instruction set architecture, and the second instruction set architecture is an arm instruction set architecture. For another example, the first instruction set architecture is an arm instruction set architecture, and the second instruction set architecture is an x86 instruction set architecture. For another example, the first instruction set architecture is an x86 instruction set architecture, and the second instruction set architecture is LoongArch (dragon architecture). The embodiment of the present invention does not limit the instruction set architecture of the source platform and the target platform.

[0028] Binary translation includes static binary translation and dynamic binary translation. Static binary translation is to translate binary program A (source program) on the source platform before it is executed, so as to translate binary program A into binary program B (target program) on the target platform. Dynamic binary translation is to translate the executed code fragments when the binary program is running. The binary translation method of the embodiment of the present invention can be applied to the scenario of dynamic binary translation. Specifically, the binary translation method of the present invention can be used to translate and execute the source program of the source platform on the target platform. Translation execution refers to translating the instructions in the source program (such as instructions of the x86 instruction set architecture) into instructions of the target platform (such as instructions of the LoongArch instruction set architecture), and executing the instructions of the target platform.

[0029] The instruction pointer is a special register that stores the address of the next instruction to be executed in the program being executed. Every time the processor executes an instruction, the instruction pointer is updated to the address of the next instruction to be executed in the next clock cycle. This process is repeated continuously, allowing the processor to execute instructions in the order of the program, thereby realizing the operation of the program.

[0030] There is no dedicated instruction for obtaining the instruction pointer in the x86 instruction set architecture. However, some scenarios require the use of the instruction pointer to complete certain operations, such as generating position-independent references to global variables through the instruction pointer. In this scenario, the instruction pointer can be obtained by calling a specific function in the x86 instruction set architecture. For example, if the specific function is func1, when a position-independent reference is required for a global variable, a function call instruction is required to call the specific function. The function call instruction refers to the call instruction, and the function call instruction is "call func1".

[0031] In a specific implementation, a specific function used to obtain an instruction pointer in the x86 instruction set architecture usually contains more than one instruction to implement the operation of obtaining an instruction pointer. Therefore, in the binary translation scenario, the semantic-based translation of the function call instruction requires the translation of the call instruction, and each instruction in func1 is translated one by one. That is, a function call instruction "call func1" needs to be translated into multiple instructions. In addition, since a TB usually ends with a control flow change instruction (such as a jump instruction, a function call instruction, etc.). Therefore, the call instruction will be used as the end of a TB to implement the segmentation of a TB block.

[0032] It can be seen that when the source program contains a function call instruction for calling a function used to obtain the instruction pointer, if the function call instruction is translated according to the semantics of the instruction, not only will redundant instructions be generated due to semantic translation, but the number of TB segmentations will increase, thereby affecting the translation efficiency; the increase in the number of TB segmentations will generate a large number of jumps between TBs, and the jumps between TBs usually involve the overhead of context switching, thereby affecting the running efficiency of the translated program.

[0033] In a specific implementation, in a source program based on the x86 instruction set architecture, if there are a large number of position-independent references to global variables, a large number of the above-mentioned function call instructions need to be translated, which will greatly affect the translation performance and the running efficiency of the translated program.

[0034] Reference Figure 2 , shows a flowchart of a binary translation method embodiment of the present invention, the method may include the following steps:

[0035] Step 101: During the binary translation process, identifying whether the current instruction is a target call instruction; the target call instruction is used to call a target function, and the target function is used to obtain an instruction pointer;

[0036] Step 102: If the current instruction is identified as a target call instruction, the target call instruction is optimized and translated; the optimized translation is used to translate the target call instruction into an immediate load instruction, and the immediate load instruction is used to load the address of the next instruction of the current instruction as an immediate value into a specified register.

[0037] The binary translation method provided in the embodiment of the present invention can be applied to a dynamic binary translator. The embodiment of the present invention does not limit the types of the source platform and the target platform, and mainly takes the x86 platform as an example for explanation.

[0038] The dynamic binary translator includes a translation module and an execution module. The translation module is used to read the binary code of the source program and translate it into target code; the execution module is used to run these target codes to simulate the execution of the source program. Correspondingly, the running process of the source program is also divided into two parts: the translation phase and the running phase. In the translation phase, the binary code of the source program is translated, and after the translation is completed, the control is transferred to the execution module for execution, entering the execution phase. When the execution module encounters a code fragment that has not been translated, the control is returned to the translation module for further translation.

[0039] In an embodiment of the present invention, the translation module identifies whether the current instruction is a target call instruction during binary translation; the target call instruction is used to call a target function, and the target function is used to obtain an instruction pointer. The current instruction may be an instruction to be translated in the source program, or may be an instruction that has been translated but not yet executed. That is, the present invention may identify the target call instruction before translation, and then directly optimize the translation of the target call instruction; or, the target call instruction may be optimized after translation, and the original translated result may be modified to the optimized translated result.

[0040] The target function refers to a specific function for obtaining an instruction pointer. Exemplarily, the target function is a specific function defined in the x86 instruction set architecture, such as __x86.get_pc_thunk.bx. The operation performed by the specific function is to obtain the instruction pointer and write it into the ebx register.

[0041] The process of the source program obtaining the instruction pointer through the specific function can be as follows: call the specific function through a function call instruction where the instruction pointer needs to be obtained. The function call instruction refers to the call instruction, such as "call__x86.get_pc_thunk.bx". The function of the call instruction is to push the address of the next instruction of the current instruction (that is, the address of the next instruction pointed to by call) to the top of the stack, and this address is also the return address of the function call instruction. Then jump to the target address (that is, the call address of the specific function) to execute the specific function. The specific function contains two instructions. The first instruction is the mov instruction. The mov instruction is a data transfer instruction, which is used to take out the value of the current top of the stack and assign it to the ebx register (the current top of the stack value is the address of the next instruction of the call instruction). The second instruction is a ret instruction. The ret instruction is a function return instruction, which is used to return in the current function. Specifically, the ret instruction takes out the address saved in the top of the stack (that is, the address of the next instruction of the call instruction) and transfers the control to this address (that is, jumps to this address to continue execution).

[0042] Since a TB usually ends with a control flow change instruction (such as a jump instruction, a function call instruction, etc.). Therefore, the call instruction that calls the specific function will be the end of a TB, and a TB will be obtained by segmentation, which is assumed to be recorded as TB1. In the above example, the specific function __x86.get_pc_thunk.bx contains two instructions, mov and ret, which constitute a TB, such as TB2. After the ret instruction is executed, it will return to continue to execute subsequent instructions. It is assumed that the subsequent instructions constitute TB3. Therefore, when the source program obtains the instruction pointer through the function call instruction "call__x86.get_pc_thunk.bx", if the function call instruction is translated according to the semantics of the instruction, it is necessary to translate the call instruction and each instruction contained in the __x86.get_pc_thunk.bx function (the two instructions, mov and ret) one by one. This translation process not only generates redundant instructions but also increases the number of segmentations of the TB, thereby affecting the translation efficiency and the running efficiency of the translated program.

[0043] In the binary translation process, the embodiment of the present invention identifies whether the current instruction is a target call instruction; the target call instruction is a function call instruction, which is used to call a target function, and the target function is used to obtain an instruction pointer. For example, the target function is the above-mentioned specific function used to obtain an instruction pointer in the x86 instruction set architecture. When the current instruction is identified as a target call instruction, the embodiment of the present invention optimizes the translation of the target call instruction instead of adopting the traditional method of semantic-based translation, so as to reduce redundant instructions generated by semantic translation and reduce the number of TB segmentation times, thereby improving the translation efficiency and the running efficiency of the translated program.

[0044] In an optional embodiment of the present invention, the target function may be any one of a series of functions in the x86 instruction set architecture for obtaining an instruction pointer, wherein the series of functions are used to obtain an instruction pointer and write it into different designated registers.

[0045] In the x86 instruction set architecture, the instruction pointer refers to the instruction pointer register in the CPU (Central Processing Unit), which stores the memory address of the instruction currently being executed by the CPU and is used to indicate the location of the next instruction to be executed by the CPU.

[0046] In the x86 instruction set architecture, a series of functions for obtaining an instruction pointer are defined. The series of functions includes multiple functions for obtaining an instruction pointer, and different functions are used to obtain the instruction pointer and write to different designated registers. For example, the __x86.get_pc_thunk.bx function is one of the functions in the series, which is used to obtain the instruction pointer and write to the ebx register. As another example, the __x86.get_pc_thunk.ax function is one of the functions in the series, which is used to obtain the instruction pointer and write to the eax register. The suffix of the series of functions can be used to indicate a designated register. For example, a suffix of bx indicates that the designated register is the ebx register, and a suffix of ax indicates that the designated register is the eax register.

[0047] The designated registers include but are not limited to general registers on the CPU in the x86 instruction set architecture, such as eax, ebx, ecx, edx, esi, edi, ebp, and esp.

[0048] In an optional embodiment of the present invention, the step of identifying whether the current instruction is a target call instruction may include:

[0049] If the current instruction is identified as a function call instruction, and the function called by the current instruction contains two instructions, the first instruction is a data transfer instruction, and the second instruction is a function return instruction, then the function called by the current instruction is determined to be the target function, and the current instruction is determined to be a target call instruction.

[0050] In the x86 instruction set architecture, each function used to obtain the instruction pointer contains only two instructions. The first instruction is a data transfer instruction, such as the mov instruction. Data transfer instructions are used to copy data from one location or register to another location or register. In the series of functions used to obtain the instruction pointer, the mov instruction is used to load the value pointed to by the current stack pointer register (extended stack pointer, esp) in the memory into the specified register. Among them, esp points to the top of the current stack.

[0051] The second instruction is the function return instruction, such as the ret instruction. The function return instruction is an indirect jump instruction. Since the same function may be called from multiple different locations in the source program, an indirect jump is required when the function returns to return to the location where it was called to continue execution.

[0052] The present invention can determine that the function called by the current instruction is the target function and that the current instruction is the target calling instruction when recognizing that the current instruction is a function calling instruction and the function called by the current instruction contains and only contains one data transfer instruction and one function return instruction.

[0053] In the binary translation process of the present invention, if the current instruction is identified as a target call instruction, the target call instruction is optimized and translated; the optimized translation is used to translate the target call instruction into an immediate load instruction, and the immediate load instruction is used to load the address of the next instruction of the current instruction (i.e., the obtained instruction pointer) into a specified register, so that the position-independent code can obtain the instruction pointer from the specified register.

[0054] It can be understood that the acquisition of the instruction pointer referred to in this article refers to acquiring the value of the instruction pointer (program counter), that is, the address of the next instruction of the current instruction.

[0055] Further, when translating to the target call instruction, the designated register can be determined by parsing the target call instruction. For example, the current instruction is a target call instruction, specifically "call__x86.get_pc_thunk.bx". By parsing the suffix of the target function called by the target call instruction, it can be determined that the target call instruction is used to write the acquired instruction pointer into the ebx register. Therefore, in the case where the target platform also has an ebx register, the designated register is determined to be the ebx register; in the case where the target platform does not have an ebx register, the designated register is determined to be the register used to simulate the ebx register in the target platform. For another example, the current instruction is a target call instruction, specifically "call__x86.get_pc_thunk.ax". By parsing the suffix of the target function called by the target call instruction, it can be determined that the target call instruction is used to write the acquired instruction pointer into the eax register. Therefore, in the case where the target platform also has an eax register, the designated register is determined to be the eax register; in the case where the target platform does not have an eax register, the designated register is determined to be the register used to simulate the eax register in the target platform.

[0056] Usually, an immediate value refers to a fixed constant or a given value. In an embodiment of the present invention, the immediate value is the address of the next instruction of the current instruction.

[0057] The present invention does not limit the specific form of the immediate value load instruction, which can be determined according to the instruction set architecture of the target platform. In one example, the immediate value load instruction is an LDR instruction, which uses an immediate value as an operand and loads the immediate value into a specified register. For example, an LDR instruction is as follows: LDR R0, = 0x12345678. This instruction is used to load the immediate value 0x12345678 into the R0 register.

[0058] In an optional embodiment of the present invention, the optimizing translation of the target call instruction may include:

[0059] Step S11, determining the designated register by parsing the target call instruction;

[0060] Step S12: determining the address of the next instruction of the current instruction based on the address of the target call instruction and the length of the target call instruction;

[0061] Step S13: taking the address of the next instruction of the current instruction as an immediate value, and translating the target call instruction into an immediate value load instruction for loading the immediate value into the designated register.

[0062] When translating to the current instruction, if the current instruction is identified as a target call instruction, the address of the target call instruction (such as addr1) and the length of the target call instruction (len1) can be obtained. The address of the target call instruction refers to the address of the call instruction in the memory, such as the address of the instruction "call__x86.get_pc_thunk.bx" in the memory. The length of the target call instruction refers to the length of the instruction "call__x86.get_pc_thunk.bx".

[0063] Based on the call address of the target call instruction and the instruction length of the target call instruction, the address of the next instruction of the current instruction (such as addr2) can be determined. Specifically, addr2=addr1+len1. Therefore, it can be determined that the immediate value is addr2. Exemplarily, the target call instruction is optimized and translated into the following immediate value load instruction: LDRebx,=addr2.

[0064] Through the optimized translation of the embodiment of the present invention, the effect of obtaining the instruction pointer can be achieved by directly translating the target call instruction into an immediate load instruction, which can reduce the redundant instructions generated by semantic translation. In addition, since the immediate load instruction is not a control flow change instruction, it does not need to be the end of the TB. The current instruction can form a TB with the subsequent instruction, and the TB segmentation is not required here, which can reduce the number of TB segmentations, thereby reducing the jumps between TBs and the overhead of context switching, thereby improving the translation efficiency of the dynamic translator and improving the running efficiency of the translated program.

[0065] In an optional embodiment of the present invention, before optimizing and translating the target call instruction, the method may further include:

[0066] Step S21, querying whether the entry address of the target function called by the target call instruction already exists in the preset hash table;

[0067] Step S22: If the entry address of the target function already exists in the preset hash table, the target call instruction is optimized and translated.

[0068] The entry address of the target function refers to the address of the first instruction (such as the mov instruction) in the target function. The embodiment of the present invention can pre-establish a preset hash table for storing the entry address of the target function called by the target call instruction.

[0069] When the current instruction is identified as a target call instruction, the preset hash table is queried to see whether the entry address of the target function (such as __x86.get_pc_thunk.bx) called by the target call instruction already exists. If the entry address of the target function already exists in the preset hash table, the target call instruction is optimized and translated directly into an immediate load instruction.

[0070] A hash table is an efficient data structure that can be used to quickly find, insert, and delete data. A hash table can map data to an index position in the table through a hash function, so that on average, the search, insertion, and deletion operations on the hash table can be completed in a very short time without affecting the translation efficiency.

[0071] When the current instruction is identified as a function call instruction, it is necessary to identify whether the function called by the function call instruction contains and only contains one data transfer instruction (mov instruction) and one function return instruction (ret instruction) to identify whether the current instruction is a target call instruction. In order to reduce the time spent on each identification of whether the current instruction is a target call instruction, the embodiment of the present invention can use a preset hash table to quickly identify whether the current instruction is a target call instruction.

[0072] Further, the identifying whether the current instruction is a target call instruction may include: if the current instruction is identified as a function call instruction, querying whether there is an entry address of the function called by the current instruction in a preset hash table, and if so, determining that the current instruction is a target call instruction.

[0073] In a specific implementation, if the current instruction is identified as a function call instruction, the preset hash table can be queried first. If the entry address of the function called by the current instruction exists in the preset hash table, it means that the current instruction is a target call instruction, and there is no need to identify whether the function called by the current instruction contains mov instructions and ret instructions, which can improve the recognition speed. If the entry address of the function called by the current instruction does not exist in the preset hash table, it is further identified whether the function called by the current instruction contains mov instructions and ret instructions. If the current instruction is not identified as a target call instruction, it is translated in the conventional way.

[0074] Therefore, when the source program contains a large number of position-independent references to global variables, only the first target call instruction needs to be translated normally. For the subsequent use of the same target call instruction, the target call instruction can be quickly identified by querying the preset hash table, and then optimized translation can be performed, which can greatly improve the translation performance and the running efficiency of the translated program.

[0075] In an optional embodiment of the present invention, the method may further include:

[0076] Step S23: If the entry address of the target function does not exist in the preset hash table, the target call instruction is conventionally translated, and the entry address of the target function is inserted into the preset hash table; the conventional translation includes translating the target call instruction and each instruction contained in the target function one by one.

[0077] The preset hash table can be established at the beginning of the translation, and the preset hash table is initially set to be empty. When a target call instruction is translated for the first time, if the entry address of the target function called by the target call instruction does not exist in the preset hash table, the target call instruction is translated normally; but it is recognized that the current instruction is a target call instruction, so the entry address of the target function called by the target call instruction is inserted into the preset hash table. In this way, when the target call instruction is translated again next time, it is found that the entry address of the target function called by the target call instruction already exists in the preset hash table, then the target call function can be directly optimized and translated without identifying the instructions in the called function.

[0078] Exemplarily, the preset hash table is empty initially. When the target call instruction is translated for the first time as "call__x86.get_pc_thunk.bx", the target function called by the target call instruction is __x86.get_pc_thunk.bx, and it is assumed that the entry address for calling the target function __x86.get_pc_thunk.bx is recorded as addr1. If the entry address does not exist in the preset hash table, the target call instruction "call__x86.get_pc_thunk.bx" is translated normally, and it is recognized that the __x86.get_pc_thunk.bx function contains mov instructions and ret instructions, then addr1 is inserted into the preset hash table. Continue to perform binary translation. When the current instruction translated is the target call instruction "call__x86.get_pc_thunk.bx", the preset hash table is queried and the entry address addr1 of the target function "__x86.get_pc_thunk.bx" is already present. Then the target call instruction "call__x86.get_pc_thunk.bx" is optimized and translated. Continue to perform binary translation. Assuming that the current instruction translated is the target call instruction "call__x86.get_pc_thunk.ax", the target function called by the target call instruction is __x86.get_pc_thunk.ax. Assuming that the entry address of calling the target function __x86.get_pc_thunk.ax is recorded as addr2. If the entry address does not exist in the preset hash table, the target call instruction "call__x86.get_pc_thunk.ax" is translated normally, and the __x86.get_pc_thunk.ax function is recognized to contain mov instructions and ret instructions, so addr2 is inserted into the preset hash table. Continue to perform binary translation. When the current instruction translated is the target call instruction "call__x86.get_pc_thunk.ax", the preset hash table is queried to find that the entry address addr2 of the target function "__x86.get_pc_thunk.ax" is already called, so the target call instruction "call__x86.get_pc_thunk.ax" is optimized. Continue to perform binary translation.

[0079] In an example, the following code is a code snippet extracted from an i386 architecture executable program after disassembly:

[0080]

[0081]

[0082] The above code snippet is binary translated. When the current instruction at the address 0x8049918 is translated, the current instruction is a "call 8049945<__x86.get_pc_thunk.ax>" instruction. It is recognized that the current instruction is a function call instruction. At this time, the preset hash table is empty, and the target call instruction is translated normally. Specifically, the call instruction and the mov instruction and ret instruction in the __x86.get_pc_thunk.ax function are translated one by one. During the translation process, it is recognized that the function call instruction is a target call instruction. The entry address of the target call instruction to call the target function is 8049945, and the entry address 0x8049945 is inserted into the preset hash table.

[0083] After the call instruction calls the __x86.get_pc_thunk.ax function, the address of the next instruction of the call instruction (that is, the value of the instruction pointer) will be loaded into the eax register.

[0084] Continue to perform binary translation. When the current instruction at address 0x804c354 is translated, the current instruction is also a "call 8049945<__x86.get_pc_thunk.ax>" instruction. It is recognized that the current instruction is a function call instruction, and the entry address 8049945 of the called function is found to exist in the preset hash table. Then the target call instruction "call8049945<__x86.get_pc_thunk.ax>" is directly optimized and translated. Specifically, the suffix of the target function __x86.get_pc_thunk.ax is parsed as ax, and the designated register is determined to be the eax register. Based on the address of the target call instruction "call 8049945<__x86.get_pc_thunk.ax>" (i.e., 804c354) and the length of the target call instruction, the immediate value 804c359 can be calculated, and the target call instruction is translated into an immediate value load instruction, such as LDReax,=804c359. Binary translation is continued until the translation is completed.

[0085] According to the above example code, in one embodiment, a binary translator translates X86 code into host code running on a host processor, and is configured to: establish a preset hash table for storing the address of an X86 instruction pointer acquisition function; for a function call instruction in a client code, query whether the address of the calling function is in the preset hash table; for a function call instruction whose address is in the preset hash table (for example, call 8049945<__x86.get_pc_thunk.ax> at 804c354), during the binary translation process, translate the function call instruction into an immediate value load instruction that loads the return address of the calling function as an immediate value into a specified register; and for other function call instructions, semantically identify whether the calling function is an X86 instruction pointer acquisition function, and insert the identified address of the X86 instruction pointer acquisition function into the hash table (for example, call 8049945<__x86.get_pc_thunk.ax> at 0x8049918). In a further alternative embodiment, call8049945 <__x86.get_pc_thunk.ax> at 804c354 may be replaced by an immediate load instruction or regarded as replaced by an immediate load instruction in binary translation. Thus, the immediate load instruction is not used as the end of the basic block, but is divided into a basic module with the next instruction.

[0086] In summary, in the binary translation process, the embodiment of the present invention identifies whether the current instruction is a target call instruction, and the target call instruction is used to call the target function of the instruction pointer. In the case of identifying the target call instruction, the target call instruction is optimized and translated directly into an immediate load instruction for loading the address of the next instruction (i.e., the instruction pointer), rather than translating the target call instruction step by step based on semantics. The traditional method of step-by-step translation based on semantics requires that each instruction contained in this target call instruction and the target function called by this target call instruction be translated separately, which not only generates redundant instructions, but also increases the number of TB segmentations due to the need for the function call instruction to end as TB, thereby affecting the translation efficiency and the running efficiency of the translated program. Through the optimized translation of the embodiment of the present invention, it is only necessary to directly translate this target call instruction into an immediate load instruction to achieve the effect of obtaining the instruction pointer, which can not only reduce the redundant instructions generated by the semantic translation, but also reduce the number of TB segmentations due to the need for the immediate load instruction to end as TB, thereby improving the translation efficiency and the running efficiency of the translated program.

[0087] It should be noted that, for the sake of simplicity, the method embodiments are described as a series of action combinations, but those skilled in the art should be aware that the embodiments of the present invention are not limited by the order of the actions described, because according to the embodiments of the present invention, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions involved are not necessarily required by the embodiments of the present invention.

[0088] Reference Figure 3 , shows a structural block diagram of a binary translation device embodiment of the present invention, the device may include:

[0089] The instruction recognition module 201 is used to identify whether the current instruction is a target call instruction during the binary translation process; the target call instruction is used to call a target function, and the target function is used to obtain an instruction pointer;

[0090] The optimization translation module 202 is used to optimize the translation of the target call instruction if the current instruction is identified as a target call instruction; the optimization translation is used to translate the target call instruction into an immediate value load instruction, and the immediate value load instruction is used to load the address of the next instruction of the current instruction as an immediate value into a specified register.

[0091] Optionally, the device further comprises:

[0092] The address query module is used to query whether the entry address of the target function called by the target call instruction already exists in the preset hash table before optimizing and translating the target call instruction; if the entry address of the target function already exists in the preset hash table, the target call instruction is optimized and translated.

[0093] Optionally, the device further comprises:

[0094] A conventional translation module is used to perform conventional translation on the target call instruction and insert the entry address of the target function into the preset hash table if the entry address of the target function does not exist in the preset hash table; the conventional translation includes translating the target call instruction and each instruction contained in the target function one by one.

[0095] Optionally, the instruction recognition module is specifically used to:

[0096] If the current instruction is identified as a function call instruction, and the function called by the current instruction contains two instructions, the first instruction is a data transfer instruction, and the second instruction is a function return instruction, then the function called by the current instruction is determined to be the target function, and the current instruction is determined to be a target call instruction.

[0097] Optionally, the optimized translation module includes:

[0098] A register determination submodule, used to determine the designated register by parsing the target call instruction;

[0099] An address determination submodule, used to determine the address of the next instruction of the current instruction based on the address of the target call instruction and the length of the target call instruction;

[0100] The optimization translation submodule is used to use the address of the next instruction of the current instruction as an immediate value, and translate the target call instruction into an immediate value loading instruction for loading the immediate value into the designated register.

[0101] Optionally, the target function is any one of a series of functions in the x86 instruction set architecture for obtaining an instruction pointer, and the series of functions are used to obtain an instruction pointer and write it into different designated registers.

[0102] The binary translation device of the present invention can apply a dynamic translator. During the binary translation process of the dynamic translator, it is identified whether the current instruction is a target call instruction, and the target call instruction is used to call the target function that obtains the instruction pointer. When the target call instruction is identified, the target call instruction is optimized and translated directly into an immediate load instruction that loads the address of the next instruction (i.e., the instruction pointer), rather than translating the target call instruction step by step based on semantics. The traditional method of step-by-step translation based on semantics requires that each instruction contained in this target call instruction and the target function called by this target call instruction be translated separately, which not only generates redundant instructions, but also increases the number of TB segmentations because the function call instruction needs to be used as the end of the TB, thereby affecting the translation efficiency and the operating efficiency of the translated program. Through the optimized translation of the embodiment of the present invention, it is only necessary to directly translate this target call instruction into an immediate load instruction to achieve the effect of obtaining the instruction pointer, which can not only reduce the redundant instructions generated by the semantic translation, but also reduce the number of TB segmentations because the immediate load instruction does not need to be used as the end of the TB, thereby improving the translation efficiency and the operating efficiency of the translated program.

[0103] As for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0104] Reference Figure 4 , is a schematic diagram of the structure of an electronic device provided by an embodiment of the present invention. Figure 4As shown, the electronic device includes: a processor, a memory, a communication interface and a communication bus, and the processor, the memory and the communication interface communicate with each other through the communication bus; the memory is used to store at least one executable instruction, and the executable instruction enables the processor to execute the steps of the binary translation method of the above-mentioned embodiment.

[0105] An embodiment of the present invention provides a non-transitory computer-readable storage medium. When instructions in the storage medium are executed by a program or a processor of a terminal, the terminal is enabled to perform the steps of the binary translation method of the aforementioned embodiment.

[0106] An embodiment of the present invention provides an electronic device, including:

[0107] Processor, which executes host code;

[0108] A memory for storing X86 code; and

[0109] The binary translator, which translates the X86 code into host code that runs on the host processor, is configured to:

[0110] Create a preset hash table to store the address of the X86 instruction pointer acquisition function;

[0111] For a function call instruction in the client code, query whether the address of the called function is in a preset hash table;

[0112] For a function call instruction whose address is located in a preset hash table, during a binary translation process, the function call instruction is translated into an immediate value load instruction for loading a return address of the called function as an immediate value into a designated register; and

[0113] For other function call instructions, semantic identification is performed to determine whether the calling function is an X86 instruction pointer acquisition function, and the address of the identified X86 instruction pointer acquisition function is inserted into the hash table.

[0114] Optionally, the binary translator performs translation according to basic blocks, and when dividing the basic blocks, does not use the function call instruction found in the preset hash table as the end of the basic block.

[0115] An embodiment of the present invention provides a binary translation program product, comprising host executable instructions, which, when executed by a host processor, causes the processor to perform the following operations:

[0116] Read X86 executable code;

[0117] Searching for a jump address of a function call instruction in an X86 executable code in a preset hash table, wherein the preset hash table is used to store an address of an X86 instruction pointer to obtain a function;

[0118] Replace the queried function call instruction with an X86 immediate value load instruction, wherein the immediate value load instruction is used to load the address of the next instruction of the function call instruction as an immediate value into a designated register;

[0119] Grouping the immediate load instruction and the next instruction into a binary translation basic block; and

[0120] Translate basic blocks.

[0121] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0122] It will be appreciated by those skilled in the art that the embodiments of the present invention may be provided as methods, devices, or computer program products. Therefore, the embodiments of the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the embodiments of the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.

[0123] The embodiments of the present invention are described with reference to the flowcharts and / or block diagrams of the methods, terminal devices (systems), and computer program products according to the embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing terminal device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0124] These computer program instructions may also be stored in a computer readable memory capable of directing a computer or other programmable data processing terminal device to operate in a predictable manner, so that the instructions stored in the computer readable memory produce a manufactured product including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0125] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal device so that a series of operating steps are executed on the computer or other programmable terminal device to produce a computer-implemented process, thereby providing instructions for executing on the computer or other programmable terminal device to implement the process. Figure 1 A process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0126] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or terminal device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or terminal device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or terminal device including the elements.

[0127] Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present invention.

Claims

1. A binary translation method, characterized in that: The method comprises: In the binary translation process, identifying whether the current instruction is a target call instruction; the target call instruction is used to call a target function, and the target function is used to obtain an instruction pointer; If the current instruction is identified as a target call instruction, the target call instruction is optimized and translated; the optimized translation is used to translate the target call instruction into an immediate load instruction, and the immediate load instruction is used to load the address of the next instruction of the current instruction as an immediate value into a specified register.

2. The method according to claim 1, characterized in that Before optimizing and translating the target call instruction, the method further includes: Querying whether the entry address of the target function called by the target call instruction already exists in the preset hash table; If the entry address of the target function already exists in the preset hash table, the target call instruction is optimized and translated.

3. The method according to claim 2, characterized in that The method further comprises: If the entry address of the target function does not exist in the preset hash table, the target call instruction is conventionally translated, and the entry address of the target function is inserted into the preset hash table; the conventional translation includes translating the target call instruction and each instruction contained in the target function one by one.

4. The method according to claim 1, characterized in that: The step of identifying whether the current instruction is a target call instruction includes: If the current instruction is identified as a function call instruction, and the function called by the current instruction contains two instructions, the first instruction is a data transfer instruction from the top of the stack to the register, and the second instruction is a function return instruction, then the function called by the current instruction is determined to be the target function, and the current instruction is determined to be a target call instruction.

5. The method according to claim 1, characterized in that The optimizing and translating the target calling instruction comprises: Determine the designated register by parsing the target call instruction; Determine the address of the next instruction of the current instruction based on the address of the target call instruction and the length of the target call instruction; The address of the next instruction of the current instruction is used as an immediate value, and the target call instruction is translated into an immediate value load instruction for loading the immediate value into the designated register.

6. The method according to any one of claims 1 to 5, characterized in that: The target function is any one of a series of functions in the x86 instruction set architecture for obtaining an instruction pointer, and the series of functions are used to obtain an instruction pointer and write it into different designated registers.

7. A binary translation device, characterized in that: The device comprises: An instruction recognition module is used to identify whether the current instruction is a target call instruction during the binary translation process; the target call instruction is used to call a target function, and the target function is used to obtain an instruction pointer; An optimization translation module is used to optimize the translation of the target call instruction if the current instruction is identified as a target call instruction; the optimization translation is used to translate the target call instruction into an immediate value load instruction, and the immediate value load instruction is used to load the address of the next instruction of the current instruction as an immediate value into a specified register.

8. An electronic device, characterized in that: include: A processor, a memory, a communication interface and a communication bus, wherein the processor, the memory and the communication interface communicate with each other via the communication bus; The memory is used to store at least one executable instruction, and the executable instruction enables the processor to execute the steps of the binary translation method according to any one of claims 1 to 6.

9. A readable storage medium, characterized in that: The readable storage medium stores a program or instruction, and when the program or instruction is executed by a processor, the steps of the binary translation method according to any one of claims 1 to 6 are implemented.

10. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the binary translation method according to any one of claims 1 to 6 are implemented.

11. An electronic device, comprising: Processor, which executes host code; Memory, storing X86 code; as well as The binary translator, which translates the X86 code into host code that runs on the host processor, is configured to: Create a preset hash table to store the address of the X86 instruction pointer acquisition function; For a function call instruction in the client code, query whether the address of the called function is in a preset hash table; For a function call instruction whose address is located in a preset hash table, during a binary translation process, the function call instruction is translated into an immediate value load instruction for loading a return address of the called function as an immediate value into a designated register; as well as For other function call instructions, semantic identification is performed to determine whether the calling function is an X86 instruction pointer acquisition function, and the address of the identified X86 instruction pointer acquisition function is inserted into the hash table.

12. The electronic device according to claim 11, wherein: The binary translator translates according to basic blocks, and when dividing the basic blocks, does not use the function call instruction found in the preset hash table as the end of the basic block.

13. A binary translation program product comprising host executable instructions which, when executed by a host processor, cause the processor to perform the following operations: Read X86 executable code; Searching for a jump address of a function call instruction in an X86 executable code in a preset hash table, wherein the preset hash table is used to store an address of an X86 instruction pointer to obtain a function; Replace the queried function call instruction with an X86 immediate value load instruction, wherein the immediate value load instruction is used to load the address of the next instruction of the function call instruction as an immediate value into a designated register; Grouping the immediate load instruction and the next instruction into a binary translation basic block; and Translate basic blocks.

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