Communication method, logic device, communication system and readable storage medium

Abstract

The invention discloses a communication method, a logic device, a communication system and a readable storage medium, the logic device of a server is located on a mainboard, the logic device is connected with a multi-channel connector on a network card connection board, and the multi-channel connector is connected with a network card connector; on the main board, a clock signal line of the processor is connected with a clock connector of the network card connecting board through the data gating device, the clock connector is connected with a clock signal interface of the network card connector, and the logic device is connected with a control port of the data gating device; the method comprises the following steps: receiving an address signal from a multi-channel connector; analyzing the address signal to obtain a data path connection relationship between the processor and the multi-channel connector; determining a gating path of the data gating device by using the data path connection relationship; and a control signal for communicating the gating path is sent to the data gating device, so that the network card plugged on the network card connecting plate meets the communication condition of clock homology. The technical effect of the invention is that the expansibility of the network card can be effectively improved.

Description

Technical Field

[0001] The present application relates to the field of telecommunication technology, and in particular to a communication method, a logic device, a communication system and a readable storage medium. Background Art

[0002] In server and network architecture, OCP network cards can be designed to support multihost functions. Multihost refers to multiple CPUs in the same server. The multihost function enables the network card to communicate and transmit data with multiple CPUs at the same time. Among them, OCP is a project aimed at promoting the standardization and openness of data center hardware. By formulating a series of open standards, it reduces the complexity and cost of data centers and improves the versatility and interoperability of equipment.

[0003] Currently, one OCP network card can connect to two processors. When the OCP network card provides network services to the processor, the clock source must be the same to achieve communication. In order to ensure the clock source, the existing network card connection topology has poor scalability, that is, it cannot support more processors.

[0004] In summary, how to effectively improve the scalability of network cards and other issues are technical problems that technical personnel in this field urgently need to solve. Summary of the invention

[0005] The purpose of this application is to provide a communication method, a logic device, a communication system and a readable storage medium to enable a network card to support multiple processors.

[0006] In order to solve the above technical problems, this application provides the following technical solutions:

[0007] A communication method is applied to a logic device of a server, wherein the logic device is located on a mainboard, the logic device is connected to a multi-channel connector on a network card connection board, and the multi-channel connector is connected to a network card connector; on the mainboard, a clock signal line of a processor is connected to a clock connector of the network card connection board through a data selector, the clock connector is connected to a clock signal interface of the network card connector, and the logic device is connected to a control port of the data selector;

[0008] Accordingly, the method comprises:

[0009] receiving an address signal from the multi-channel connector;

[0010] parsing the address signal to obtain a data path connection relationship between the processor and the multi-channel connector;

[0011] Determine the strobe path of the data strobe by using the data path connection relationship;

[0012] A control signal for connecting the strobe path is sent to the data strobe, so that the network card plugged into the network card connecting board meets the communication condition of the same clock source.

[0013] Preferably, the multi-channel connector includes a processor address signal interface, and the logic device is connected to the processor address signal interface via an interface expander;

[0014] Accordingly, receiving an address signal from the multi-channel connector includes:

[0015] The address signal is received by the interface expander.

[0016] Preferably, parsing the address signal to obtain a data path connection relationship between the processor and the multi-channel connector includes:

[0017] Parsing the address signal to obtain an address mapping value;

[0018] The address and processor mapping truth table is queried to obtain the data path connection relationship corresponding to the address mapping value.

[0019] Preferably, the clock signal line of the processor is a differential signal line, the differential signal line is connected to the input end of the data selector, and the output end of the data selector is connected to the clock signal interface of the network card connector;

[0020] Determining a strobe path of the data strobe by using the data path connection relationship includes:

[0021] According to the data path connection relationship, determining the target processor to be connected to each of the clock connectors;

[0022] The path connected to the target processor is determined as the strobe path of the corresponding data strobe.

[0023] Preferably, it also includes:

[0024] Continuously receiving address signals and monitoring the address signals in real time;

[0025] After detecting a change in the address signal, parsing the current address signal to obtain a new data path connection relationship between the processor and the multi-channel connector;

[0026] Determine a new strobe path of the data strobe by using the new data path connection relationship;

[0027] A new control signal connected to the new selection path is sent to the data selector so that the network card plugged into the network card connection board meets the communication condition of the same clock source.

[0028] Preferably, the logic device is connected to an interface expander on a network card connection board via a data transmission bus, and the interface expander is connected to a processor address signal interface of a plurality of multi-channel connectors;

[0029] On the mainboard, the clock signal line of the processor is a differential signal line, and one of the differential signal lines is respectively connected to two input ends of the data selector;

[0030] An output end of the data selector is connected to an input interface of the clock connector, the output end of the clock connector is connected to the clock signal interface of the network card connector, and the logic device is connected to control ports of several data selectors;

[0031] Accordingly, receiving an address signal from the multi-channel connector includes:

[0032] Receiving address signals from a plurality of the multi-channel connectors through the interface expander;

[0033] Accordingly, parsing the address signal to obtain a data path connection relationship between the processor and the multi-channel connector includes:

[0034] Parsing the address signal to obtain an address mapping value;

[0035] Querying a truth table of mapping addresses to processors to obtain a data path connection relationship corresponding to the address mapping value;

[0036] Accordingly, determining the strobe path of the data strobe by using the data path connection relationship includes:

[0037] According to the data path connection relationship, determining the target processor to be connected to each of the clock connectors;

[0038] Determine the path connected to the target processor as the strobe path of the corresponding data strobe;

[0039] Accordingly, sending a control signal connecting the strobe path to the data strobe includes:

[0040] Determining a gating value connecting the gating path from a truth table corresponding to the data gating device;

[0041] A control signal carrying the strobe value is sent to the data strobe.

[0042] A logic device, the logic device is located on a mainboard, the logic device is connected to a multi-channel connector on a network card connection board, and the multi-channel connector is connected to a network card connector; on the mainboard, a clock signal line of a processor is connected to a clock connector of the network card connection board through a data selector, the clock connector is connected to a clock signal interface of the network card connector, and the logic device is connected to a control port of the data selector;

[0043] Accordingly, the logic device includes:

[0044] An address signal receiving module, used for receiving an address signal from the multi-channel connector;

[0045] An address parsing module, used for parsing the address signal to obtain a data path connection relationship between the processor and the multi-channel connector;

[0046] A path determination module, used for determining a strobe path of the data strobe by using the data path connection relationship;

[0047] The gating control module is used to send a control signal to the data gating device to connect the gating path, so that the network card plugged into the network card connecting board meets the communication condition of the same clock source.

[0048] A communication system, comprising:

[0049] Mainboard and network card connection board;

[0050] On the mainboard, the logic device is connected to the multi-channel connector on the network card connection board, and the multi-channel connector is connected to the network card connector; on the mainboard, the clock signal line of the processor is connected to the clock connector of the network card connection board through a data selector, and the clock connector is connected to the clock signal interface of the network card connector, and the logic device is connected to the control port of the data selector;

[0051] The processor on the mainboard is plugged into the multi-channel connector on the network card connection board via a high-speed transmission bus;

[0052] The network card connecting plate is used for plugging in the network card.

[0053] Preferably, it includes:

[0054] The processor on the mainboard is plugged into the interface expander of the network card connection board through a high-speed transmission bus. The multi-channel connector on the network card connection board includes a processor address signal interface, and the processor address signal interface is plugged into the interface expander.

[0055] A readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the above communication method are implemented.

[0056] A computer program product comprises a computer program / instruction, which implements the steps of the above communication method when executed by a processor.

[0057] The logic device of the server applies the method provided in the embodiment of the present application, the logic device is located on the mainboard, the logic device is connected to the multi-channel connector on the network card connection board, and the multi-channel connector is connected to the network card connector; on the mainboard, the clock signal line of the processor is connected to the clock connector of the network card connection board through the data selector, the clock connector is connected to the clock signal interface of the network card connector, and the logic device is connected to the control port of the data selector; accordingly, the method includes: receiving an address signal from the multi-channel connector; parsing the address signal to obtain a data path connection relationship between the processor and the multi-channel connector; using the data path connection relationship to determine a selection path of the data selector; sending a control signal to the data selector to connect the selection path, so that the network card plugged into the network card connection board meets the communication conditions of the same clock source.

[0058] In the present application, the logic device is located on the mainboard, and the logic device is connected to the multi-channel connector on the network card connection. The logic device can receive the address signal from the multi-channel connector and parse it, so as to clarify the data path connection relationship between the processor on the mainboard and the multi-channel connector on the network card connector. In order to achieve clock homology, the logic device also needs to control the clock signal of the corresponding processor to be input to the clock signal interface on the network card connector. Specifically, the data path connection relationship can be used to determine the gating path of the data selector. Then, a control signal connecting the gating path is sent to the data selector. In response to the control signal, the data selector selects the corresponding gating path, so that the clock signal on the processor is input to the network card on the network card connection board, thereby satisfying the communication conditions of clock homology.

[0059] Technical effect: Combined with the data selector, N-choose-1 can be achieved, so the number of processors connected to the network card can be expanded instead of being limited to 2 processors, which can effectively improve the scalability of the network card.

[0060] Correspondingly, the embodiments of the present application also provide a logic device, a communication system, a readable storage medium and a computer program product corresponding to the above-mentioned communication method, which have the above-mentioned technical effects and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0061] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the related technologies, the drawings required for use in the embodiments or the related technical descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0062] Figure 1 This is a flow chart of an implementation of a communication method in an embodiment of the present application;

[0063] Figure 2 This is a schematic diagram of the structure of a communication system in an embodiment of the present application;

[0064] FIG3 is a schematic diagram of an expander pin in an embodiment of the present application;

[0065] FIG4 is a schematic diagram of a data strobe pin in an embodiment of the present application;

[0066] Figure 5 A topology diagram of an OCP network card;

[0067] Figure 6 The topology diagram of an OCP network card in an embodiment of the present application is shown in FIG.

[0068] FIG. 7 is a schematic diagram of the structure of a logic device in an embodiment of the present application. DETAILED DESCRIPTION

[0069] In order to enable those skilled in the art to better understand the present application, the present application is further described in detail below in conjunction with the accompanying drawings and specific implementation methods. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without making creative work are within the scope of protection of the present application.

[0070] To facilitate understanding of the technical solutions in this application, the relevant terms involved in this specification are collectively explained below.

[0071] OCP network card: a server network card that complies with the Open Compute Project interface specification.

[0072] CPLD: Complex Programmable Logic Device (hereinafter referred to as logic device).

[0073] PCIe: Peripheral Component Interconnect Express, a high-speed, serial, full-duplex, computer expansion bus standard.

[0074] MCIO connector: A multi-channel input / output connector (referred to as a multi-channel connector in this article) that can combine multiple physical channels into an interface for high-speed data streams, and is often used to transmit PCIe signals.

[0075] CPU: Central Processing Unit (referred to as processor in this article).

[0076] CLK BUFFER: CLK BUFFER can expand one CLK (CLOCK) signal of the CPU into multiple CLK signals. This article only describes the one connected to the OCP network card, and there is no limitation on other channels.

[0077] I2C: Inter-Integrated Circuit, a widely used serial communication protocol, mainly used to connect low-speed peripheral devices to master devices such as microprocessors and microcontrollers, and communicate through two wires (SDA, data line; SCL, clock line).

[0078] PCA9555: is a commonly used I / O expansion chip produced by NXP Semiconductors, that is, a specific interface expander.

[0079] MC14052B: A 4-channel analog multiplexer (MUX) chip that can filter one of four paired input signals as an output signal, i.e., a specific data selector.

[0080] Please refer to Figure 1 , Figure 1 This is a flow chart of a communication method in an embodiment of the present application, which is applied to the logic of the server, such as Figure 2 As shown, the logic device 101 is located on the mainboard 100, the logic device is connected to the multi-channel connector 201 on the network card connection board 200, and the multi-channel connector is connected to the network card connector 204; on the mainboard, the clock signal line of the processor 103 is connected to the clock connector 202 of the network card connection board through the data selector 104, the clock connector is connected to the clock signal interface 203 of the network card connector, and the logic device is connected to the control port of the data selector;

[0081] Accordingly, the communication method includes:

[0082] S101. Receive an address signal from a multi-channel connector.

[0083] The processor can be plugged into a multi-channel connector on the network card connection board through a high-speed transmission bus (such as a PCIe bus) to transmit data to and from the network card.

[0084] The multi-channel connector can send an address signal to the logic device through a channel connected to the logic device. The address signal corresponds to which processor is connected to each multi-channel connector. In practical applications, there can be multiple multi-channel connectors on the network card connection board, there can also be multiple processors, and the processor can have multiple multi-channel connectors. The multi-channel connector of the processor can be connected to the multi-channel connector on the network card connection board.

[0085] In a specific implementation of the present application, the multi-channel connector includes a processor address signal interface, and the logic device is connected to the processor address signal interface through an interface expander;

[0086] Accordingly, receiving an address signal from the multi-channel connector includes:

[0087] The address signal is received through the interface expander.

[0088] The multi-channel connector may be specifically an MCIO connector. MCIO connector: a multi-channel input / output connector that can combine multiple physical channels into an interface for a high-speed data stream, and can be used to transmit PCIe signals.

[0089] The MCIO connector is provided with a processor address signal interface, which can output a CPU address (CPU ADDR) signal (address signal). The address signal is used to indicate which CPU the high-speed PCIe signal comes from.

[0090] In order to collect address signals, in this embodiment, the address interfaces of the multi-channel connector are all connected to the interface expander, and the interface expander is connected to the logic on the mainboard. The interface expander can be a PCA9555 chip. That is, the address signals from multiple multi-channel connectors can be received through the PCA9555 chip.

[0091] S102, parsing the address signal to obtain a data path connection relationship between the processor and the multi-channel connector.

[0092] By parsing the address signal, it is possible to obtain which channel connector on the processor and the network card connector has established data connection.

[0093] It should be noted that if the processor wants to achieve network communication based on the network card, the clock source between the processor and the network card needs to be the same. Specifically, when the data line of processor 1 is connected to the network card, the clock line of processor 1 also needs to be connected to the network card.

[0094] In order to make the network card have strong scalability, the network card connector can have multiple multi-channel connectors, and the motherboard can also have multiple processors. If the processor wants to communicate based on the network card, it is necessary to connect its multi-channel connector with the multi-channel connector on the network card connector to achieve data connection. There are multiple processors on the motherboard, and the network card connector also has a multi-channel connector. In order to achieve clock homology, it is necessary to access the clock signal line of the corresponding processor at the corresponding clock signal interface. Therefore, in this embodiment, it is necessary to clarify which processor each multi-channel connector is connected to based on the address signal. This connection relationship is referred to as the data path connection relationship in this article.

[0095] For example, if there are processors 0, 1, 2, and 3 on the motherboard, there are multi-channel connectors 0, 1, 2, and 3 on the network card connector. On multi-channel connector 0, the multi-channel connector of any of the four processors may be plugged. Therefore, based on the address signal analysis, it can be clearly determined which processor is connected to each of the four multi-channel connectors. Of course, in actual applications, a processor may be connected to one or more multi-channel connectors; multi-channel connectors may also be idle and unconnected.

[0096] In a specific implementation of the present application, parsing the address signal to obtain the data path connection relationship between the processor and the multi-channel connector includes:

[0097] Parse the address signal and obtain the address mapping value;

[0098] Query the address and processor mapping truth table to obtain the data path connection relationship corresponding to the address mapping value.

[0099] For ease of description, the above steps are combined for explanation below.

[0100] Please refer to Figure 3, the mapping truth table between address and processor is shown in Table 1 below:

[0101] Table 1 is the mapping truth table between address and processor

[0102]

[0103] That is, by combining the truth table, the connection relationship between the processor and the multi-channel connector can be clearly understood.

[0104] S103, using the data path connection relationship, determine the selection path of the data selector.

[0105] After the data path connection relationship is determined, it is necessary to ensure that the data path connection relationship of the processor corresponds to the clock path connection relationship one by one. Therefore, the gating path of the data gator can be determined directly based on the data path connection relationship.

[0106] For example, the processor 1 and the multi-channel connector 1 have a data path connection, and the multi-channel connector 1 and the clock signal interface 1 have a corresponding relationship, so it is necessary to adjust the data selector so that the clock signal of the processor 1 is input to the clock signal interface 1.

[0107] In a specific implementation of the present application, the clock signal line of the processor is a differential signal line, the differential signal line is connected to the input end of the data selector, and the output end of the data selector is connected to the clock signal interface of the network card connector;

[0108] Using the data path connection relationship, determine the strobe path of the data strobe, including:

[0109] According to the data path connection relationship, determine the target processor to which each clock connector is to be connected;

[0110] The path connected to the target processor is determined as the strobe path of the corresponding data strobe.

[0111] For ease of description, the above steps are combined for explanation below.

[0112] That is to say, the data path connection relationship needs to correspond to the clock path connection relationship one by one. Therefore, based on the data path connection relationship, the gating path of the data selector can be determined. That is, it is determined which processor the data selector needs to be connected to. In this embodiment, the path connecting the target processor is determined as the gating path of the corresponding data selector. The path connected by the data selector is the clock path. The clock path and data path of a processor need to be strictly matched, otherwise the clock homology cannot be achieved.

[0113] S104, sending a control signal for connecting the strobe path to the data strobe, so that the network card plugged into the network card connecting board meets the communication condition of the same clock source.

[0114] In order to connect the corresponding clock signal path, in this embodiment, a control signal for connecting the strobe path may be sent to the corresponding data strobe.

[0115] In this way, based on the corresponding control signal, the data selector can make the network card plugged into the network card connecting board meet the communication condition of the same clock source.

[0116] The logic device of the server applies the method provided in the embodiment of the present application, the logic device is located on the mainboard, the logic device is connected to the multi-channel connector on the network card connection board, and the multi-channel connector is connected to the network card connector; on the mainboard, the clock signal line of the processor is connected to the clock connector of the network card connection board through the data selector, the clock connector is connected to the clock signal interface of the network card connector, and the logic device is connected to the control port of the data selector; accordingly, the method includes: receiving an address signal from the multi-channel connector; parsing the address signal to obtain a data path connection relationship between the processor and the multi-channel connector; using the data path connection relationship to determine a selection path of the data selector; sending a control signal to the data selector to connect the selection path, so that the network card plugged into the network card connection board meets the communication conditions of the same clock source.

[0117] In the present application, the logic device is located on the mainboard, and the logic device is connected to the multi-channel connector on the network card connection. The logic device can receive the address signal from the multi-channel connector and parse it, so as to clarify the data path connection relationship between the processor on the mainboard and the multi-channel connector on the network card connector. In order to achieve clock homology, the logic device also needs to control the clock signal of the corresponding processor to be input to the clock signal interface on the network card connector. Specifically, the data path connection relationship can be used to determine the gating path of the data selector. Then, a control signal connecting the gating path is sent to the data selector. In response to the control signal, the data selector selects the corresponding gating path, so that the clock signal on the processor is input to the network card on the network card connection board, thereby satisfying the communication conditions of clock homology.

[0118] Technical effect: Combined with the data selector, N-choose-1 can be achieved, so the number of processors connected to the network card can be expanded instead of being limited to 2 processors, which can effectively improve the scalability of the network card.

[0119] It should be noted that, based on the above embodiments, the embodiments of the present application also provide corresponding improved solutions. In the preferred / improved embodiments, the same steps or corresponding steps as those in the above embodiments can be referenced to each other, and the corresponding beneficial effects can also be referenced to each other, which will not be described one by one in the preferred / improved embodiments of this article.

[0120] In a specific implementation of the present application, it also includes:

[0121] Continuously receive address signals and monitor the address signals in real time;

[0122] After detecting that the address signal changes, the current address signal is parsed to obtain a new data path connection relationship between the processor and the multi-channel connector;

[0123] Determine a new strobe path of the data strobe by using the new data path connection relationship;

[0124] A new control signal connecting a new selection path is sent to the data selector so that the network card plugged into the network card connection board meets the communication condition of the same clock source.

[0125] For ease of description, the above steps are combined for explanation below.

[0126] That is to say, after completing the control of clock homology, in order to avoid manually plugging and unplugging the connection line during use, which will destroy the communication conditions of clock homology, it is necessary to continue to receive the address signal. Once the address signal is found to have changed, it is necessary to re-sort and determine the strobe path of the data selector and perform signal control, so that the newly plugged and unplugged processor and network card can still maintain the clock homology to ensure communication reliability.

[0127] Of course, in actual applications, the service objects of the network card can also be expanded. For example, in the initial state, only one processor uses the network card. As time goes by, a new processor is added and the corresponding interface is plugged in (that is, the multi-channel connector for transmitting data signals of the new processor is connected to the multi-channel connector on the network card connector board, and the clock signal of the new processor is connected to the data selector through the CLK BUFFER (clock buffer)). At this time, the following steps can be performed:

[0128] receiving an address signal from a multi-channel connector;

[0129] Parsing the address signal to obtain the data path connection relationship between the processor and the multi-channel connector;

[0130] Determine a newly added strobe path of the data strobe by using the data path connection relationship;

[0131] A control signal is sent to the data selector to connect to the newly added selection path so that the network card newly plugged into the network card connection board meets the communication condition of the same clock source.

[0132] In this way, by controlling the data selector, one more clock signal is connected to the network card connector. In addition, the connected processor can be continuously switched according to demand, so that multiple processors can share network card resources.

[0133] In a specific implementation of the present application, the logic device is connected to an interface expander on a network card connection board via a data transmission bus, and the interface expander is connected to a processor address signal interface of a plurality of multi-channel connectors;

[0134] On the motherboard, the processor's clock signal line is a differential signal line, and one differential signal line is connected to the two input terminals of the data selector respectively;

[0135] An output end of a data selector is connected to an input interface of a clock connector, an output end of the clock connector is connected to a clock signal interface of a network card connector, and a logic device is connected to control ports of several data selectors;

[0136] Accordingly, receiving an address signal from the multi-channel connector includes:

[0137] receiving address signals from a plurality of multi-channel connectors via an interface expander;

[0138] Accordingly, the address signal is parsed to obtain the data path connection relationship between the processor and the multi-channel connector, including:

[0139] Parse the address signal and obtain the address mapping value;

[0140] Query the address and processor mapping truth table to obtain the data path connection relationship corresponding to the address mapping value;

[0141] Accordingly, the data path connection relationship is used to determine the strobe path of the data strobe, including:

[0142] According to the data path connection relationship, determine the target processor to which each clock connector is to be connected;

[0143] Determine the path connected to the target processor as the strobe path of the corresponding data strobe;

[0144] Accordingly, a control signal for connecting the strobe path is sent to the data strobe, including:

[0145] Determine the strobe value of the connected strobe path from the truth table corresponding to the data strobe;

[0146] A control signal carrying a strobe value is sent to the data strobe.

[0147] For ease of explanation, the above steps are described in detail below in combination with specific scenarios and relevant technical solutions as examples.

[0148] Please refer to Figure 5, which corresponds to a solution topology that supports multihost OCP network cards. The high-speed signal PCIe of the OCP network card has a total of 16 lanes (channels). The front x8 lane of the PCIe signal comes from CPU0, and the clock signal CLK signal also comes from CPU0. The rear x8 lane of the PCIe signal is connected to the MCIO connector. The MCIO connector can be connected to two MCIOs from CPU0 or CPU1 respectively. If connected to CPU1, the multihost function can be realized, that is, one OCP network card is connected to two CPUs at the same time. The CPLD (logic control chip) controls whether to open the CLK BUFFER connected to CPU1 through the CPU source signal on the MCIO connector (the signal will show different characteristics when connected to the MCIO of CPU0 or the MCIO of CPU1). If connected to CPU1, the CLK BUFFER connected to CPU1 is opened, so that the PCIe signal of the x8 lane after the OCP network card is consistent with the clock signal source. If connected to CPU0, the CLK BUFFER connected to CPU1 is closed, so that the PCIe signal of the x8 lane after the OCP network card is consistent with the clock signal source. At the same time, the MCIO of the x8 lane behind the OCP network card can also be disconnected from other MCIOs, and the OCP network card only uses the x8 bandwidth.

[0149] visible, Figure 5 The solution shown is not very extensible and the application scenario is relatively simple. In this technical solution, the source of the front x8 lane of the PCIe of the OCP network card is fixed, and there are only two options for the source of the rear x8 lane of the PCIe. If the OCP network card supports more CPUs (such as 4 CPUs), the design of the PCIe high-speed signal source may be more complicated and not fixed, and this technical solution will no longer be applicable.

[0150] In this application, when the OCP network card supports multihost (one OCP network card is connected to multiple CPUs), the high-speed signal (PCIe signal) and clock signal (CLK signal) connected to the OCP network card come from the same CPU, so that the PCIe signal and the CLK signal have the same source.

[0151] For details, please refer to Figure 6 In the case where the OCP network card supports multihost (multiple CPUs as hosts) and the number of CPUs is large (such as 4 CPUs, processor 0 to processor 3 in the figure), the OCP network card connector is placed on a separate OCP network card connection board instead of on the mainboard.

[0152] The OCP network card connector is located on the OCP network card connection board and is used to connect the OCP network card. At the same time, the OCP network card connection board is connected to the motherboard to transmit clock signals (CLK signals), high-speed PCIe signals, and I2C signals that communicate with the motherboard CPLD (logic).

[0153] The OCP network card connection board is connected to the MCIO connector on the mainboard to transmit PCIe signals through the four MCIO connectors on the OCP network card connection board. The PCIe signal bandwidth corresponding to each MCIO connector on the OCP network card connection board is x4. Each CPU has N (N≥2) MCIO connectors that can be used to connect to the MCIO on the OCP network card connection board to provide PCIe high-speed signals (this connection relationship is not drawn in the figure). The MCIO signal on the OCP network card connection board can establish communication with the corresponding CPU by connecting the MCIO connectors belonging to different CPUs.

[0154] The MCIO connector on the corresponding motherboard is provided with a CPU address (CPU ADDR) signal, which is used to characterize which CPU the high-speed PCIe signal comes from, as shown in Figure 3, and the corresponding relationship truth table between the CPU ADDR signal and the CPU. When the OCP network card connection board is connected to the motherboard MCIO connector, the information can be transmitted to the onboard PCA9555 chip on the OCP network card connection board. How the CPU ADDR signal of each MCIO is configured on the PCA9555 is shown in Figure 3 and Table 1. The PCA9555 chip is transmitted to the motherboard CPLD through I2C communication. The CPLD can obtain the CPU information currently connected to the OCP network card by parsing the CPU ADDDR information on the corresponding port of PCA9555. As an IO expansion chip, PCA9555 has 16 IO pins. Each MCIO CPU ADDRpin has three, which are connected to the corresponding pins in Figure 3, such as MCIO's CPU ADDR0, CPU ADDR1, and CPU ADDR2 is connected to P0, P1, and P2 pins of PCA9555. The truth table in Table 1 gives the relationship between the actual levels of these three pins and the source of the CPU. Therefore, after CPLD obtains the level information of the corresponding pin of PCA9555 through I2C signal, it can determine which CPU the MCIO comes from.

[0155] There are 4 clock CLK interfaces (clock signal interfaces) on the OCP network card connector. CLK1-CLK4 correspond to 4 PCIe interfaces in sequence, that is, CLK1 corresponds to PCIe lane <3:0>, CLK2 corresponds to PCIe lane <7:4>, CLK3 corresponds to PCIelane <11:8>, and CLK4 corresponds to PCIe lane <15:12>, in order to achieve clock homology, the PCIe source of MCIO needs to be consistent with its corresponding CLK source. The implementation method is that each of the four CLK interfaces on the OCP network card connector corresponds to a MUX chip (MC14051B). The MUX chip can select one of the four CLK differential signals (from four CPUs) as output. How the MUX chip (MC14051B) selects the input is determined by the CPLD. After the CPLD analyzes which CPU the upstream of one of the PCIe interfaces of the corresponding OCP network card connector comes from, it controls the corresponding CLK interface corresponding to the MUX to select the CLK signal output by the same CPU as the clock signal to achieve clock homology. Taking the MCIO1 of the OCP network card connector as an example, if MCIO1 is connected to the MCIO of CPU0, the CPLD controls the CLK signal output by the CPU0 connected to MUX0 as the output signal to the CLK1 of the OCP network card connector to make their clocks homology. The control pin control transmission relationship of the MUX chip (MC14051B) is shown in Figure 4 and the truth table is shown in Table 2:

[0156] Table 2 is the truth table of the control transmission relationship of the data strobe

[0157]

[0158] CPLD controls the level of C, A, B pins of MUX chip through output selection signal to select the input signal source corresponding to the output signal. If CPLD controls C, B, A pins to be low level (0, 0, 0), the input sources of output X and Y are X0 and Y0, and the CPLD control logic is shown in Table 2.

[0159] That is to say, the embodiment of the present application provides a clock homology system solution for OCP network cards supporting multihost function, which can realize the multihost function of OCP network cards supporting multiple CPUs. Figure 5 The scheme shown is more adaptable and has the following beneficial effects:

[0160] (1) Enhanced parallel processing capability: OCP network cards support multihost functions, and multiple CPUs can process network data in parallel, significantly improving the speed and efficiency of data processing. This parallel processing capability enables data centers or high-performance computing environments to better cope with large-scale, highly complex data processing tasks.

[0161] (2) Load balancing: OCP network cards that support multihost can automatically or manually distribute network loads to different CPUs to achieve load balancing, avoid overloading a single CPU, and improve the stability and performance of the overall system.

[0162] Corresponding to the above method embodiment, the embodiment of the present application further provides a logic device, and the logic device described below and the communication method described above can be referenced to each other.

[0163] The logic device is located on the mainboard, the logic device is connected to the multi-channel connector on the network card connection board, and the multi-channel connector is connected to the network card connector; on the mainboard, the clock signal line of the processor is connected to the clock connector of the network card connection board through the data selector, the clock connector is connected to the clock signal interface of the network card connector, and the logic device is connected to the control port of the data selector;

[0164] Correspondingly, as shown in FIG7 , the connector includes the following modules:

[0165] An address signal receiving module 1001, used for receiving an address signal from a multi-channel connector;

[0166] An address parsing module 1002 is used to parse the address signal and obtain the data path connection relationship between the processor and the multi-channel connector;

[0167] A path determination module 1003 is used to determine a strobe path of a data strobe by using a data path connection relationship;

[0168] The strobe control module 1004 is used to send a control signal to the data strobe to connect the strobe path so that the network card plugged into the network card connecting board meets the communication condition of the same clock source.

[0169] The logic of the server is located on the mainboard, the logic is connected to the multi-channel connector on the network card connection board, and the multi-channel connector is connected to the network card connector; on the mainboard, the clock signal line of the processor is connected to the clock connector of the network card connection board through the data selector, the clock connector is connected to the clock signal interface of the network card connector, and the logic is connected to the control port of the data selector; accordingly, the method includes: receiving an address signal from the multi-channel connector; parsing the address signal to obtain a data path connection relationship between the processor and the multi-channel connector; using the data path connection relationship, determining a gating path of the data selector; sending a control signal to the data selector to connect the gating path, so that the network card plugged into the network card connection board meets the communication conditions of clock homology.

[0170] In the present application, the logic device is located on the mainboard, and the logic device is connected to the multi-channel connector on the network card connection. The logic device can receive the address signal from the multi-channel connector and parse it, so as to clarify the data path connection relationship between the processor on the mainboard and the multi-channel connector on the network card connector. In order to achieve clock homology, the logic device also needs to control the clock signal of the corresponding processor to be input to the clock signal interface on the network card connector. Specifically, the data path connection relationship can be used to determine the gating path of the data selector. Then, a control signal connecting the gating path is sent to the data selector. In response to the control signal, the data selector selects the corresponding gating path, so that the clock signal on the processor is input to the network card on the network card connection board, thereby satisfying the communication conditions of clock homology.

[0171] Technical effect: Combined with the data selector, N-choose-1 can be achieved, so the number of processors connected to the network card can be expanded instead of being limited to 2 processors, which can effectively improve the scalability of the network card.

[0172] In a specific implementation of the present application, the multi-channel connector includes a processor address signal interface, and the logic device is connected to the processor address signal interface through an interface expander;

[0173] Correspondingly, the address signal receiving module is specifically used to receive the address signal through the interface expander.

[0174] In a specific implementation of the present application, the address resolution module is specifically used to resolve the address signal to obtain the address mapping value;

[0175] Query the address and processor mapping truth table to obtain the data path connection relationship corresponding to the address mapping value.

[0176] In a specific implementation of the present application, the clock signal line of the processor is a differential signal line, the differential signal line is connected to the input end of the data selector, and the output end of the data selector is connected to the clock signal interface of the network card connector;

[0177] A path determination module, specifically used to determine the target processor to be connected to each clock connector according to the data path connection relationship;

[0178] The path connected to the target processor is determined as the strobe path of the corresponding data strobe.

[0179] In a specific implementation of the present application, the adaptive adjustment module is used to continuously receive the address signal and monitor the address signal in real time;

[0180] After detecting that the address signal changes, the current address signal is parsed to obtain a new data path connection relationship between the processor and the multi-channel connector;

[0181] Determine a new strobe path of the data strobe by using the new data path connection relationship;

[0182] A new control signal connecting a new selection path is sent to the data selector so that the network card plugged into the network card connection board meets the communication condition of the same clock source.

[0183] In a specific implementation of the present application, the logic device is connected to an interface expander on a network card connection board via a data transmission bus, and the interface expander is connected to a processor address signal interface of a plurality of multi-channel connectors;

[0184] On the motherboard, the processor's clock signal line is a differential signal line, and one differential signal line is connected to the two input terminals of the data selector respectively;

[0185] An output end of a data selector is connected to an input interface of a clock connector, an output end of the clock connector is connected to a clock signal interface of a network card connector, and a logic device is connected to control ports of several data selectors;

[0186] Correspondingly, the address signal receiving module is specifically used to receive address signals from multiple multi-channel connectors through the interface expander;

[0187] Correspondingly, the address resolution module is specifically used to resolve the address signal to obtain the address mapping value;

[0188] Query the address and processor mapping truth table to obtain the data path connection relationship corresponding to the address mapping value;

[0189] Correspondingly, the path determination module is specifically used to determine the target processor to be connected to each clock connector according to the data path connection relationship;

[0190] Determine the path connected to the target processor as the strobe path of the corresponding data strobe;

[0191] Correspondingly, the strobe control module is specifically used to determine the strobe value of the connected strobe path from the truth table corresponding to the data strobe;

[0192] A control signal carrying a strobe value is sent to the data strobe.

[0193] Corresponding to the above method embodiment, the embodiment of the present application also provides a communication system. The communication system described below and the communication method and logic described above can refer to each other.

[0194] like Figure 2 As shown, the communication system comprises:

[0195] Mainboard and network card connection board;

[0196] On the mainboard, the logic device is connected to the multi-channel connector on the network card connection board, and the multi-channel connector is connected to the network card connector; on the mainboard, the clock signal line of the processor is connected to the clock connector of the network card connection board through a data selector, and the clock connector is connected to the clock signal interface of the network card connector, and the logic device is connected to the control port of the data selector;

[0197] The processor on the mainboard is plugged into the multi-channel connector on the network card connection board via a high-speed transmission bus;

[0198] The network card connecting plate is used for plugging in the network card.

[0199] like Figure 6 , preferably, comprising:

[0200] The processor on the mainboard is plugged into the interface expander of the network card connection board through a high-speed transmission bus. The multi-channel connector on the network card connection board includes a processor address signal interface, which is plugged into the interface expander.

[0201] That is, the communication system is essentially a clock homology management system solution that supports multihost OCP network cards. When the OCP network card supports multihost (one OCP network card is connected to multiple CPUs), the high-speed signal (PCIe signal) and clock signal (CLK signal) connected to the OCP network card come from the same CPU, thus achieving the same source of PCIe signal and CLK signal.

[0202] Corresponding to the above method embodiment, the embodiment of the present application further provides a readable storage medium. The readable storage medium described below and the communication method described above can refer to each other.

[0203] A readable storage medium stores a computer program, which implements the steps of the communication method of the above method embodiment when the computer program is executed by a processor.

[0204] The readable storage medium may specifically be a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, or other readable storage medium that can store program codes.

[0205] Corresponding to the above method embodiment, the embodiment of the present application further provides a computer program product. The computer program product described below and the communication method described above can refer to each other.

[0206] A computer program product includes a computer program / instruction. When the computer program / instruction is executed by a processor, the steps of the above communication method are implemented.

[0207] In this specification, each embodiment is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the logic device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part.

[0208] Those skilled in the art may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented with electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in terms of function in the above description. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art may use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0209] The steps of the method or algorithm described in conjunction with the embodiments disclosed herein may be implemented directly using hardware, a software module executed by a processor, or a combination of the two. The software module may be placed in a random access memory (RAM), a memory, a read-only memory (ROM), an electrically programmable ROM, an electrically erasable programmable ROM, a register, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.

[0210] Finally, it should be noted that, in this article, relationships such as first and second, etc. are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms include, include or any other variations are intended to cover non-exclusive inclusion, so that a process, method, article or device that includes a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device.

[0211] Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method and core idea of ​​the present application. At the same time, for those skilled in the art, according to the idea of ​​the present application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A communication method, characterized in that: A logic device applied to a server, the logic device is located on a mainboard, the logic device is connected to a multi-channel connector on a network card connection board, and the multi-channel connector is connected to a network card connector; on the mainboard, a clock signal line of a processor is connected to a clock connector of the network card connection board through a data selector, the clock connector is connected to a clock signal interface of the network card connector, and the logic device is connected to a control port of the data selector; Accordingly, the method comprises: receiving an address signal from the multi-channel connector; parsing the address signal to obtain a data path connection relationship between the processor and the multi-channel connector; Determine the strobe path of the data strobe by using the data path connection relationship; A control signal for connecting the strobe path is sent to the data strobe, so that the network card plugged into the network card connecting board meets the communication condition of the same clock source.

2. The method according to claim 1, characterized in that The multi-channel connector includes a processor address signal interface, and the logic device is connected to the processor address signal interface through an interface expander; Accordingly, receiving an address signal from the multi-channel connector includes: The address signal is received by the interface expander.

3. The method according to claim 2, characterized in that Parsing the address signal to obtain a data path connection relationship between the processor and the multi-channel connector includes: Parsing the address signal to obtain an address mapping value; The address and processor mapping truth table is queried to obtain the data path connection relationship corresponding to the address mapping value.

4. The method according to claim 1, characterized in that: The clock signal line of the processor is a differential signal line, the differential signal line is connected to the input end of the data selector, and the output end of the data selector is connected to the clock signal interface of the network card connector; Determining a strobe path of the data strobe by using the data path connection relationship includes: According to the data path connection relationship, determining the target processor to be connected to each of the clock connectors; The path connected to the target processor is determined as the strobe path of the corresponding data strobe.

5. The method according to claim 1, characterized in that Also includes: Continuously receiving address signals and monitoring the address signals in real time; After detecting a change in the address signal, parsing the current address signal to obtain a new data path connection relationship between the processor and the multi-channel connector; Determine a new strobe path of the data strobe by using the new data path connection relationship; A new control signal connected to the new selection path is sent to the data selector so that the network card plugged into the network card connection board meets the communication condition of the same clock source.

6. The method according to any one of claims 1 to 5, characterized in that: The logic device is connected to the interface expander on the network card connection board through a data transmission bus, and the interface expander is connected to the processor address signal interface of a plurality of multi-channel connectors; On the mainboard, the clock signal line of the processor is a differential signal line, and one of the differential signal lines is respectively connected to two input ends of the data selector; An output end of the data selector is connected to an input interface of the clock connector, the output end of the clock connector is connected to the clock signal interface of the network card connector, and the logic device is connected to control ports of several data selectors; Accordingly, receiving an address signal from the multi-channel connector includes: Receiving address signals from a plurality of the multi-channel connectors through the interface expander; Accordingly, parsing the address signal to obtain a data path connection relationship between the processor and the multi-channel connector includes: Parsing the address signal to obtain an address mapping value; Querying a truth table of mapping addresses to processors to obtain a data path connection relationship corresponding to the address mapping value; Accordingly, determining the strobe path of the data strobe by using the data path connection relationship includes: According to the data path connection relationship, determining the target processor to be connected to each of the clock connectors; Determine the path connected to the target processor as the strobe path of the corresponding data strobe; Accordingly, sending a control signal connecting the strobe path to the data strobe includes: Determining a gating value connecting the gating path from a truth table corresponding to the data gating device; A control signal carrying the strobe value is sent to the data strobe.

7. A logic device, characterized in that: The logic device is located on the mainboard, the logic device is connected to the multi-channel connector on the network card connection board, and the multi-channel connector is connected to the network card connector; on the mainboard, the clock signal line of the processor is connected to the clock connector of the network card connection board through a data selector, the clock connector is connected to the clock signal interface of the network card connector, and the logic device is connected to the control port of the data selector; Accordingly, the logic device includes: An address signal receiving module, used for receiving an address signal from the multi-channel connector; An address parsing module, used for parsing the address signal to obtain a data path connection relationship between the processor and the multi-channel connector; A path determination module, used for determining a strobe path of the data strobe by using the data path connection relationship; The gating control module is used to send a control signal to the data gating device to connect the gating path, so that the network card plugged into the network card connecting board meets the communication condition of the same clock source.

8. A communication system, characterized in that: include: Mainboard and network card connection board; On the mainboard, the logic device is connected to a multi-channel connector on a network card connection board, and the multi-channel connector is connected to a network card connector; On the mainboard, the clock signal line of the processor is connected to the clock connector of the network card connection board through a data selector, the clock connector is connected to the clock signal interface of the network card connector, and the logic device is connected to the control port of the data selector; The processor on the mainboard is plugged into the multi-channel connector on the network card connection board via a high-speed transmission bus; The network card connecting plate is used for plugging in the network card.

9. The communication system according to claim 8, characterized in that: include: The processor on the mainboard is plugged into the interface expander of the network card connection board through a high-speed transmission bus. The multi-channel connector on the network card connection board includes a processor address signal interface, and the processor address signal interface is plugged into the interface expander.

10. A readable storage medium, characterized in that: The readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the communication method according to any one of claims 1 to 6 are implemented.

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