Data writing method, related memory controller and data storage device

Abstract

The invention relates to a data writing method for a flash memory, a related memory controller and a data storage device. The method comprises the following steps of: writing write data into a page buffer of the flash memory; encoding the write-in data to generate first check data corresponding to the write-in data, and writing the first check data into the page buffer; when the first verification data is generated, performing error detection according to the write-in data and the first verification data to generate an error detection result; and when the error detection result indicates that the first verification data has no error, sending a write command to the flash memory so as to write the write data in the page buffer and the first verification data into a flash memory element of the flash memory.

Description

Technical Field

[0001] The present invention relates to a flash memory, and more particularly to a data writing method, a related memory controller and a data storage device capable of improving data integrity and reliability of a data storage device. Background Art

[0002] In extreme environments, alpha particles may have adverse effects on data storage devices, for example, causing data loss or errors. Alpha particles are positively charged particles that are usually produced during radioactive decay and have high energy and penetration. When data storage devices are exposed to an environment containing a large number of alpha particles, these high-energy particles may impact sensitive components of the device, such as semiconductor storage media and controllers. When alpha particles interact with electrons inside the device, they may cause local charge imbalances, which may induce transient current and voltage fluctuations. These transient phenomena may negatively affect the reliability and integrity of data storage devices, causing data loss, corruption, or errors. For example, in flash memory, when an alpha particle penetrates a flash memory cell, it may change the charge state stored therein, causing a bit flipping, which may cause data corruption or errors. In extreme cases, the high-energy impact of alpha particles may even cause permanent damage to the flash memory cell, resulting in data loss. Since alpha particles are very harmful to data storage devices, it is necessary to propose an architecture that can ensure high reliability and stability of data storage devices in extreme environments such as high radiation environments, so as to further reduce the potential risks to data storage devices caused by radiation sources such as alpha particles. Summary of the invention

[0003] In view of the above, the object of the present invention is to provide a data writing mechanism that can improve the data integrity and reliability of data storage devices. In an embodiment of the present invention, an error check is performed on the encoded data generated by the flash memory controller to determine whether the data writing needs to be repeated. Among them, the embodiment of the present invention relies on a read-back check to verify whether the data written to the flash memory has errors, or performs on-the-fly verification while encoding, so as to ensure that: no errors are caused by the influence of alpha particles during the encoding process, or no transmission errors occur during the data being transmitted to the flash memory.

[0004] An embodiment of the present invention provides a data writing method for a flash memory. The method comprises: writing a write data into a page buffer of the flash memory; encoding the write data to generate a first verification data corresponding to the write data, and writing the first verification data into the page buffer; while generating the first verification data, performing an error detection according to the write data and the first verification data to generate an error detection result; and when the error detection result indicates that there is no error in the first verification data, issuing a write command to the flash memory to write the write data and the first verification data in the page buffer into a flash memory element of the flash memory.

[0005] An embodiment of the present invention provides a data writing method for a flash memory. The method includes: encoding a write data to generate the write data and a corresponding first verification data, and writing the write data and the first verification data to a page buffer of the flash memory. Sending a write command to write the write data and the first verification data in the page buffer to a flash memory element of the flash memory; reading the write data and the first verification data from the page buffer, and decoding them to generate an error detection result; and when the error detection result indicates that the first verification data has an error, encoding the write data again to generate a second verification data corresponding to the write data, and writing the write data and the second verification data to the flash memory.

[0006] An embodiment of the present invention provides a memory controller for a flash memory. The memory controller includes: a storage unit, a processing unit, an encoder and a check circuit. The storage unit is used to store a program code. The processing unit is used to execute the program code to perform an operation of writing a write data into the flash memory. The encoder is used to encode the write data to generate a first check data corresponding to the write data. The check circuit is used to perform an error detection based on the write data and the first check data while the encoder generates the first check data to generate an error detection result. Among them, the processing unit is also used to write the write data and the first check data to the page buffer to a page buffer of the flash memory, and when the error detection result indicates that there is no error in the first check data, a write command is issued to the flash memory to write the write data and the first check data in the page buffer to a flash memory element of the flash memory.

[0007] An embodiment of the present invention provides a memory controller for a flash memory. The memory controller includes: a storage unit, a processing unit, an encoder and a decoder. The storage unit is used to store a program code. The processing unit is used to execute the program code to perform an operation of writing a write data into the flash memory. The encoder is used to encode the write data to generate a first verification data corresponding to the write data, wherein the processing unit is used to write the write data and the first verification data into a flash memory element in the flash memory, and after the writing is completed, the write data and the first verification data are read back from a page buffer in the flash memory. The decoder is used to decode the read-back write data and the first verification data to generate an error detection result. Wherein, the encoder is also used to encode the write data again when the error detection result indicates that the first verification data has an error, so as to generate a second verification data corresponding to the write data, and the processing unit writes the write data and the second verification data into the flash memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 A structural diagram of a data storage device according to an embodiment of the present invention is shown.

[0009] Figure 2 A flow chart of a data writing mechanism according to a first embodiment of the present invention is shown.

[0010] Figure 3 A partial structural diagram of a memory controller and an NV memory according to a first embodiment of the present invention is shown.

[0011] Figure 4 A flowchart of data writing according to the second embodiment of the present invention is shown.

[0012] Figure 5 A partial structural diagram of a memory controller and an NV memory according to a second embodiment of the present invention is shown.

[0013] Figure 6 FIG. 4 is a timing diagram illustrating data writing, encoding and error detection according to a second embodiment of the present invention.

[0014]

Explanation of symbols

[0015] 10 Electronic devices

[0016] 50 Host device

[0017] 52 Processors

[0018] 54RAM

[0019] 100 Data storage devices

[0020] 110 Memory Controller

[0021] 112 Processing Units

[0022] 112C Program code

[0023] 112M ROM

[0024] 113 Internal Memory

[0025] 114 Control Logic Circuit

[0026] 118 Transmission interface circuit

[0027] 121 Page Cache

[0028] 122_1~122_N NV memory element

[0029] 123 Control Circuit

[0030] 130 Encoder

[0031] 140 Decoder

[0032] 150 Test circuit

[0033] 160 AES operation circuit

[0034] Steps 210-260, 310-360 DETAILED DESCRIPTION

[0035] In the following text, many specific details are described to provide readers with a thorough understanding of the embodiments of the present invention. However, those skilled in the art will understand how to implement the present invention without one or more specific details, or using other methods, components, materials, etc. In other cases, well-known structures, materials, or operations will not be shown or described in detail to avoid obscuring the core concepts of the present invention.

[0036] The reference to "an embodiment" in the specification means that the specific features, structures or characteristics described in the embodiment may be included in at least one embodiment of the present invention. Therefore, the "in an embodiment" that appears in various places in this specification does not necessarily mean the same embodiment. In addition, the aforementioned specific features, structures or characteristics may be combined in one or more embodiments in any suitable form.

[0037] Figure 11 is a schematic diagram of an electronic device 10 according to an embodiment of the present invention, wherein the electronic device 10 includes a host device 50 and a data storage device 100. The host device 50 may include: at least one processor 52 for controlling the host device 50, and a random access memory (Random Access Memory) 54 for storing data and information required by the processor 52. Examples of the host device 50 include but are not limited to: a smart phone, a tablet computer, a wearable device, a personal computer (e.g., a desktop computer and a notebook computer), an imaging device (e.g., a digital camera or a video camera), a game console, a car navigation system, a printer, a scanner, or a server system. Examples of the data storage device 100 include but are not limited to: a portable storage device (e.g., a memory card that complies with SD / MMC, CF, MS, XD, or UFS specifications), a solid state drive (SSD), and various embedded storage devices (e.g., an embedded storage device that complies with UFS or EMMC specifications).

[0038] According to various embodiments of the present invention, the data storage device 100 may include a controller (e.g., a memory controller 110), and may also include a non-volatile (NV) memory 120. The NV memory 120 is configured to store information. The NV memory 120 may include one or more NV memory elements, for example, a plurality of NV memory elements 122_1 to 122_N. The NV memory 120 may be a flash memory, and the NV memory elements 122_1 to 122_N may be a plurality of flash memory chips or a plurality of flash memory dies, respectively, but the present invention is not limited thereto. In addition, the NV memory 120 may include memory cells having a two-dimensional structure, and may also include memory cells having a three-dimensional structure.

[0039] like Figure 1As shown, the memory controller 110 may include a processing unit 112, a read-only memory (ROM) 112M, an internal memory 113, a control logic circuit 114, and a transmission interface circuit 118, a buffer 125, an encoder 130, a decoder 140, a verification circuit 150, and an Advanced Encryption Standard (AES) operation circuit 160. At least some of these components may be coupled to each other via a bus. The internal memory 113 may be implemented by one or more memory devices. For example, the internal memory 113 may be a static RAM (SRAM) and / or a dynamic RAM (DRAM). The internal memory 113 may be used to provide internal storage space for the memory controller 110, for example, to temporarily store information such as variables / parameters, data, commands, addresses, and / or address mapping tables. In some embodiments, the memory controller 110 also relies on a host memory buffer (HMB) technology. By using the HMB technology, the memory controller 110 can utilize the RAM 54 (e.g., DRAM) of the host device 50 as a part or extension of the internal memory 113, thereby improving the read and write performance of the data storage device 100. In addition, the ROM 112M in this embodiment is configured to store the program code 112C, and the microprocessor 112 is configured to execute the program code 112C, thereby controlling the access to the NV memory 120. In addition, the program code 112C can also be stored in the NV memory 120.

[0040] The memory controller 110 controls the reading, writing and erasing of the NV memory 120 through the control logic circuit 114. In addition, the memory controller 110 can simultaneously perform: the writing of user data based on the host command of the host device 50, and the writing of valid data read from the NV memory 120 based on the garbage collection operation and / or the wear-leveling operation. The control logic circuit 114 can be further configured to control the NV memory 120 and include an error correction code (ECC) circuit (not shown) to perform data protection and / or error correction, but the present invention is not limited thereto. The transmission interface circuit 118 may comply with a specific communication specification (e.g., a Serial Advanced Technology Attachment (SATA) specification, a Universal Serial Bus (USB) specification, a Peripheral Component Interconnect Express (PCIE) specification, an embedded Multi Media Card (eMMC) specification, or a Universal Flash Storage (UFS) specification), and may communicate with the host device 50 according to the specific communication specification.

[0041] Generally speaking, the host device 50 may indirectly access the NV memory 120 by transmitting a host command and a corresponding logical address to the memory controller 110. The memory controller 110 receives the host command and the logical address, and translates the logical address into a physical address, and translates the host command into a memory operation command (Memory Operation Command), and further controls the NV memory 120 through the memory operation command to perform a read, write or erase operation on a memory cell or data page (Page) with a physical address. Among them, the NV memory 120 includes one or more page buffers 121 (which can be implemented by SRAM), and one or more control circuits 123. What the memory controller 110 wants to write to the NV memory 120 will be written to the page buffer 121, and one or more control circuits 123 read, write or erase data according to the memory operation command sent by the memory controller 110. Address. When the memory controller 110 performs an erase operation on any one of the NV memory elements 122_1 to 122_N, at least one block in the NV memory element 122_k may be erased. In addition, each block of the NV memory element 122_k may include multiple pages, and access operations (e.g., read or write) may be performed on one or more pages.

[0042] In one embodiment, each of the NV memory elements 122_1 to 122_N may be an NV memory die or chip. Each NV memory die 122_1 to 122_N has a control circuit for executing a memory operation command issued by the memory controller 110. In addition, each NV memory die 122_1 to 122_N may include multiple planes. Each plane may have multiple blocks composed of memory cells, and related column and row control circuits. The memory cells in each plane may be arranged in a 2D or 3D memory structure. In addition, various processing operations can be performed on different planes at the same time through multi-plane operation commands. For example, multiple operations can be performed in parallel (simultaneously) on memory blocks in different planes to perform multi-plane (e.g., read, write, erase) operations.

[0043] In one embodiment, the memory controller 110 may be used to combine memory blocks in the NV memory 120 into multiple super blocks. In one embodiment, the composition of the super block may span across the NV memory chips 122_1-122_N. In addition, the super block may be used as one or more storage blocks in each of the NV memory chips 122_1-122_N.

[0044] In one embodiment of the present invention, a L2P address mapping table consisting of a plurality of logical-to-physical (L2P) address mapping entries can be divided into a plurality of mapping groups, each mapping group including a portion of mapping entries of the L2P address mapping table to perform logical to physical address conversion. These mapping groups are permanently stored in blocks of the NV memory 120 and loaded into the internal memory 113 when needed. Similarly, a P2L address mapping table consisting of a plurality of physical-to-logical (P2L) address mapping entries can be divided into a plurality of mapping groups, each mapping group including a portion of mapping entries of the P2L address mapping table to perform physical to logical address conversion. These mapping groups are permanently stored in blocks of the NV memory 120 and loaded into the internal memory 113 when needed.

[0045] Generally speaking, the memory controller 110 will write, read or erase according to the host command of the host device 50. In a typical writing process, the host write command sent by the host device 50 will include a write address (i.e., a logical address) and the data to be written. The data to be written may be processed by the AES operation circuit 160 for AES decryption operation (if the host device 50 has performed AES encryption on the data), and the processed data (hereinafter referred to as write data DAT) will be temporarily stored in a buffer area of ​​the internal memory 113 (hereinafter referred to as buffer 113, which may be DRAM or SRAM). In this process, the write data DAT may also be protected by a specific error correction mechanism. Before the write data DAT is written to the NV memory 120, it will be read from the buffer 113 to the encoder 130 for encoding, thereby generating check data (i.e., parity data (parity data or parity bits)) PTY. The check data PTY will be attached to the end of the write data DAT and regarded as an encoded data (i.e., systematic encoding), and the two will be written into the NV memory 120 together. In addition, when writing, the encoded data will be written into the page buffer 121 first, and when the memory controller 110 sends a write command to the control circuit 123 in the NV memory 120, the encoded data will be written into one or more pages (or super pages) on a certain NV memory element 122_k in the NV memory 120. On the other hand, when reading, the encoded data (write data DAT and corresponding check data PTY) will be read out from the NV memory 120, and the decoder 140 will decode according to the read encoded data, thereby performing error detection and correction according to its encoding and decoding architecture. In one embodiment, the encoder 130 and the decoder 140 can be a low-density parity-check code (LDPC code) encoder and decoder.

[0046] In the process of writing data to the NV memory 120, the encoder 130 may be attacked by alpha particles, so that it generates error-containing check data PTY, or bit errors are caused by high-speed transmission during the process of writing the check data PTY to the page buffer 121. In order to verify the data integrity, the present invention determines whether there is an error in the encoded data written into the NV memory 120.

[0047] In one embodiment, the present invention performs a read back check to determine whether there is an error in the encoded data. Figure 2 The flowchart shown is similar to Figure 3 1 is a partial structural diagram of the memory controller 110 and the NV memory 120 shown in FIG. First, in step 210, the write data DAT to be written by the host device 50 is read from the buffer 113, and the write data DAT is encoded by the encoder 130 to generate encoded data consisting of the write data DAT and the check data PTY. Then, in step 220, the encoded data is written to the page buffer 121 of the NV memory 120. In step 230, the memory controller 110 sends a write command to the control circuit 123 in the NV memory 120, and the control circuit 123 writes the encoded data from the page buffer 121 to the NV memory element 122_k. In step 240, the memory controller 110 reads back the encoded data just written from the page buffer 121, and decodes the read encoded data through the decoder 140 to determine whether an error occurs (e.g., performing LDPC decoding to perform error detection). If so, the process enters step 260, re-encodes the write data DAT, generates the check data PTY' again, and finally writes the two to another physical address of the NV memory element 122_k (or selects another NV memory element in the NV memory 120), and performs a read-back check again (that is, repeats steps 210 to 240) until no error is found, and the write operation of the write data DAT is considered to be completed. If no error is found in step 240, the process ends and the writing is completed (step 250). On the other hand, in step 260, in addition to re-encoding the write data DAT and writing the encoded data to the NV memory 120, the memory controller 110 also marks the physical address where the data DAT and the check data PTY are written in step 230 as invalid in the address mapping table. It can be seen that in the above embodiment, the encoded data that has been written is read back from the page buffer 121 of the NV memory 120 to determine whether an error has occurred.

[0048] However, in another embodiment of the present invention, the encoded data is only written to the page buffer first, and the data is not written to the NV memory element 122_k until it passes the verification. Figure 4 The flowchart shown is similar to Figure 51 is a partial schematic diagram of the memory controller 110 and the NV memory 120. First, in step 310, the write data DAT to be written by the host device 50 is read from the buffer 113 and written to the page buffer 121 of the NV memory 120. In step 320, the write data DAT is encoded to generate the check data PTY corresponding to the write data DAT, and the generated check data PTY is written to the page buffer 121. In step 330, while the check data PTY is generated (on-the-fly), the write data DAT and the check data PTY are verified by the check circuit 150 to generate an error detection result. In one embodiment, the check circuit 150 may include another encoder similar to the encoder 130. This encoder will encode the write data DAT again and generate another check data. The check data generated by the check circuit 150 will be compared with the check data PTY generated by the encoder 130. If the two are consistent, it means that no error has occurred (e.g., there is no error in the check data PTY). Otherwise, it indicates that an error has occurred. In another embodiment, the check circuit 150 may include a check equation verification circuit, which obtains multiple check equations based on a check matrix used to generate the check data PTY. And the write data DAT and the check data PTY are input into multiple check equations for verification. If multiple check equations are not satisfied at the same time, it is determined that an error has occurred. In one embodiment, the check equation can be a parity check matrix in LDPC coding, and the check equation is generated by each row of the parity check matrix. In step 340, it is determined whether the error detection result indicates that an error has occurred; if so, the process enters step 360, and the write data DAT is written from the buffer 113 to the page buffer 121 again, and the encoder 130 is used to encode the write data DAT again to generate new check data PTY', and it is verified through the check circuit 150 until no error is found (that is, steps 310 to 340 are repeated) to complete the writing of the write data DAT. If the judgment result of step 340 is no, the process enters step 350, the memory controller 110 will issue a write command to the control circuit 123 of the NV memory 120, and the control circuit 123 will write the write data DAT and the verification data PTY in the page buffer 121 to one or more pages of the NV memory element 122_k, and end the process.In this embodiment, before the encoded data passes verification, it is only written to the page buffer 121 and not written to the NV memory element 122_k, so the cost caused by the encoding error is relatively small (it will not cause invalid data on the NV memory 120 and saves time writing to the flash memory element in the NV memory 120).

[0049] Figure 6 Draw Figure 4 and Figure 5 The timing diagram of data writing and data encoding in the embodiment shown in the figure. In this embodiment, the write data DAT is first written into the page buffer 121. After the operation of writing the write data DAT into the page buffer 121 is completed, the encoder 130 will start to encode the write data DAT and generate the verification data PTY. After the encoder 130 starts to output the verification data PTY in sequence, the verification circuit 150 will perform error checking on the write data DAT and the verification data PTY that has been generated in real time (on-the-fly). If an error is detected, it will be Figure 6 In the operation sequence shown, the write data DAT is first written into the page buffer 121 (covering the previous write), the write data DAT is encoded again, and the generated check data PTY is verified again. As can be seen from the figure, the encoder 130 outputs the check data PTY and the check circuit 150 performs error checking almost at the same time, so the delay caused by the error checking can be shortened, so that the write operation of the write data DAT does not take a long time due to the error checking.

[0050] In summary, the write mechanism provided by the present invention can be used to eliminate two causes of errors. First, the encoder is attacked by alpha particles and generates error-containing check data. Second, during the process of transferring the check data to the flash memory, bit errors are caused by high-speed transmission. Through the write mechanism provided by the present invention, the reliability of the data storage device can be improved, thereby ensuring data integrity.

[0051] The embodiments of the present invention may be specifically implemented as an apparatus, method or computer program product. Accordingly, the embodiments of the present invention may take the form of an entity implemented entirely by hardware, an entity implemented entirely by software (including firmware, resident software, microcode, etc.), or an entity combining software and hardware aspects, which may be generally referred to as a "module" or "system". In addition, the embodiments of the present invention may take the form of a computer program product embodied in any tangible expression medium, and the medium has a computer-usable program code embodied in the medium. In terms of hardware, the present invention may be implemented by applying any of the following technologies or related combinations: separate operating logic of a logic gate capable of executing a logic function according to a data signal, and an application specific integrated circuit (ASIC), a programmable gate array (PGA) or a field programmable gate array (FPGA) with appropriate combinational logic.

[0052] The flow chart and block diagram illustrate the architecture, function and operation of the system, method and computer program product of different possible implementation methods of the embodiment of the present invention. In this regard, each block in the flow chart or block diagram may represent a module, section or a portion of the program code, including one or more executable instructions to implement a specific logic function. It should also be noted that each block in the block diagram and / or flow chart, and the block combination in the block diagram and / or flow chart can be implemented by a special-purpose hardware base system, or a combination of special hardware and computer program instructions. These computer program instructions can be stored in a readable computer medium to command a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the readable computer medium generate functions / operations specified in the blocks or block combinations that include implementing the flow chart and / or block diagram.

[0053] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made according to the scope of the patent application of the present invention should fall within the scope of the present invention.

Claims

1. A method for writing data into a flash memory, comprising: Writing a write data into a page buffer of the flash memory; Encoding the write data to generate first verification data corresponding to the write data, and writing the first verification data into the page buffer; While generating the first verification data, performing an error detection according to the write data and the first verification data to generate an error detection result; as well as When the error detection result indicates that the first verification data has no error, a write command is issued to the flash memory to write the write data and the first verification data in the page buffer into a flash memory element of the flash memory.

2. The data writing method according to claim 1, characterized in that: The step of performing the error detection according to the write data and the first verification data comprises: Encoding the written data again to generate a second verification data; comparing the second verification data with the first verification data; and When the second verification data is consistent with the first verification data, an error detection result indicating that there is no error in the first verification data is generated.

3. The data writing method according to claim 1, characterized in that: The step of verifying according to the written data and the verification data comprises: Obtaining a plurality of verification formulas according to a verification matrix used to generate the first verification data; Inputting the write data and the first verification data into the plurality of verification programs; as well as When the plurality of verification procedures are all satisfied, an error detection result indicating that the first verification data does not have an error is generated.

4. The data writing method according to claim 1, characterized in that: Also includes: When the error detection result indicates that the first verification data has an error, writing the write data into the page buffer again; Encoding the write data again to generate a third verification data corresponding to the write data, and writing the third verification data into the page buffer; as well as When the third verification data is generated, an error detection is performed according to the write data and the third verification data to generate an error detection result.

5. A method for writing data into a flash memory, comprising: Encoding a write data to generate the write data and a corresponding first verification data, and writing the write data and the first verification data into a page buffer of the flash memory; Sending a write command to write the write data and the first verification data in the page buffer into a flash memory element of the flash memory; Reading the write data and the first verification data from the page buffer and decoding them to generate an error detection result; as well as When the error detection result indicates that the first verification data has an error, the write data is encoded again to generate a second verification data corresponding to the write data, and the write data and the second verification data are written into the flash memory.

6. The method as claimed in claim 5, characterized in that when the error detection result indicates that the first verification data has an error, a physical address of the flash memory element of the flash memory into which the write data and the first verification data are written is marked as invalid.

7. A memory controller for a flash memory, comprising: a storage unit for storing a program code; a processing unit, configured to execute the program code to perform an operation of writing write data into the flash memory; An encoder, used for encoding the write data to generate a first verification data corresponding to the write data; a check circuit for performing an error check according to the write data and the first check data to generate an error detection result when the encoder generates the first check data; The processing unit is also used for: Writing the write data and the first verification data into the page buffer to a page buffer of the flash memory; as well as When the error detection result indicates that the first verification data has no error, a write command is issued to the flash memory to write the write data and the first verification data in the page buffer into a flash memory element of the flash memory.

8. A memory controller as described in claim 7, wherein the verification circuit is used to encode the write data to generate a second verification data, the verification circuit is used to compare the second verification data with the first verification data, and when the second verification data is consistent with the first verification data, the verification circuit is used to generate an error detection result indicating that there is no error in the first verification data.

9. A memory controller as described in claim 7, wherein the verification circuit obtains multiple verification programs based on a verification matrix used to generate the first verification data, and the verification circuit inputs the write data and the first verification data into the multiple verification programs; and when the multiple verification programs are all satisfied, the verification circuit is used to generate an error detection result indicating that there is no error in the first verification data.

10. The memory controller according to claim 7, wherein: When the error detection result indicates that the first verification data has an error, the processing unit writes the write data into the page buffer again; The encoder encodes the write data again to generate a third verification data corresponding to the write data, and the processing unit writes the third verification data into the page buffer; And the checking circuit performs an error detection according to the written data and the third checking data to generate an error detection result while the encoder generates the third checking data.

11. A data storage device comprising the memory controller as claimed in claim 7 and a flash memory.

12. A memory controller for a flash memory, comprising: a storage unit for storing a program code; a processing unit, configured to execute the program code to perform an operation of writing write data into the flash memory; an encoder for encoding the write data to generate a first verification data corresponding to the write data, wherein the processing unit is used to write the write data and the first verification data into a flash memory element in the flash memory, and after writing is completed, read the write data and the first verification data back from a page buffer in the flash memory; a decoder for decoding the read-back write data and the first verification data to generate an error detection result; When the error detection result indicates that the first verification data has an error, the encoder encodes the write data again to generate a second verification data corresponding to the write data, and the processing unit is used to write the write data and the second verification data into the flash memory.

13. The memory controller according to claim 12, wherein: When the error detection result indicates that the first verification data has an error, the processing unit marks a physical address of the flash memory element of the flash memory into which the write data and the first verification data are written as invalid.

14. A data storage device comprising the memory controller as claimed in claim 12 and a flash memory.

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