Array substrate, preparation method thereof and display panel

Abstract

The invention provides a preparation method of an array substrate and a display panel. The preparation method comprises the following steps: forming an active layer on a substrate layer; forming a gate insulating layer covering the active layer on the substrate layer; forming a first metal layer on the gate insulating layer; forming a capacitor dielectric module on the gate insulating layer; hydrogenating the active layer through a high-temperature activation process; and forming an interlayer dielectric module on the capacitor dielectric module. According to the invention, the step of high-temperature annealing after opening the holes in the interlayer dielectric film layer is canceled, so that the problem of poor content uniformity of hydrogen ions in the active layer caused by overflow of the hydrogen ions through the via holes is solved.

Description

Technical Field

[0001] The present invention relates to the field of display devices, and in particular to an array substrate and a preparation method thereof, and a display panel. Background Art

[0002] AMOLED (Active-Matrix Organic Light-Emitting Diode) display technology is regarded as the next generation of display technology, with the characteristics of fast response speed, high contrast, wide viewing angle, and low energy consumption. With the rapid development of science and technology, people have higher and higher requirements for the display quality of AMOLED displays, and the requirements for the uniformity of low grayscale images are also getting higher and higher. At present, when AMOLED displays low grayscale, a straight-line defect (Mura) will appear at the edge of the screen, which is mainly manifested as uneven brightness display. Summary of the invention

[0003] The object of the present invention is to provide an array substrate and a method for preparing the same, and a display panel, so as to solve the problem that a penetrating linear defect appears at the edge of the screen when the existing display panel displays low grayscale.

[0004] To achieve the above-mentioned purpose, the present invention provides a method for preparing an array substrate, which includes the following steps: forming an active layer on a substrate layer; forming a gate insulating layer covering the active layer on the substrate layer; forming a first metal layer on the gate insulating layer; forming a capacitor dielectric module on the gate insulating layer; hydrogenating the active layer through a high-temperature activation process; forming an interlayer dielectric module on the capacitor dielectric module; forming a via hole on a side of the active layer away from the substrate layer, and filling the via hole with a third metal layer.

[0005] Furthermore, the step of forming a capacitor dielectric module on the gate insulating layer includes: forming a first dielectric layer covering the first metal layer on a surface of the gate insulating layer away from the active layer; and forming a second dielectric layer on a surface of the first dielectric layer away from the first metal layer.

[0006] Furthermore, the thickness of the first dielectric layer is less than or equal to 500 angstroms; and the thickness of the capacitor dielectric module is 1000-1400 angstroms.

[0007] Furthermore, the material of the first dielectric layer includes silicon nitride; and the material of the second dielectric layer includes silicon oxide.

[0008] Furthermore, the step of forming an interlayer dielectric module on the capacitor dielectric module includes: forming a third dielectric layer on a surface of the capacitor dielectric module away from the first metal layer; and forming a fourth dielectric layer on a surface of the third dielectric layer away from the capacitor dielectric module.

[0009] Furthermore, the material of the third dielectric layer includes silicon oxide; the material of the fourth dielectric layer includes silicon nitride; preferably, the thickness of the interlayer dielectric module is greater than the thickness of the capacitor dielectric module.

[0010] Furthermore, before the step of forming an interlayer dielectric module on the capacitor dielectric module, the step includes: forming a second metal layer on a surface of the capacitor dielectric module away from the first metal layer.

[0011] Furthermore, the step of forming a via hole on the side of the active layer away from the substrate layer and filling the via hole with a third metal layer includes the following steps: opening the via hole in the interlayer dielectric module, the capacitor dielectric module and the gate insulating layer; forming the third metal layer on a surface of the interlayer dielectric module away from the capacitor dielectric module, and filling the via hole with the third metal layer.

[0012] The present invention further provides an array substrate, which is prepared by the array substrate preparation method as described above.

[0013] The present invention further provides a display panel, which includes the array substrate as described above.

[0014] The advantages of the present invention are as follows: in an array substrate and a preparation method thereof, and a display panel of the present invention, the step of high-temperature annealing after opening a hole in the interlayer dielectric film layer in the related process technology is eliminated, and no high-temperature operation is required after the hole is opened, thereby solving the problem of poor uniformity of hydrogen ion content in the active layer caused by hydrogen ions overflowing through the vias, thereby improving the picture uniformity of the display panel when displaying low-gray pictures. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0016] Figure 1 is a schematic diagram of a layered structure of an array substrate in an embodiment of the present invention;

[0017] Figure 2 is a schematic flow chart of a method for preparing an array substrate in an embodiment of the present invention;

[0018] Figure 3 Schematic diagram of the layered structure of the array substrate after step S10 in an embodiment of the present invention;

[0019] Figure 4 Schematic diagram of the layered structure of the array substrate after step S20 in an embodiment of the present invention;

[0020] Figure 5 Schematic diagram of the layered structure of the array substrate after step S30 in an embodiment of the present invention;

[0021] Figure 6 Schematic diagram of the layered structure of the array substrate after step S40 in an embodiment of the present invention;

[0022] Figure 7 Schematic diagram of the layered structure of the array substrate after step S50 in an embodiment of the present invention;

[0023] Figure 8 Schematic diagram of the layered structure of the array substrate after step S60 in an embodiment of the present invention;

[0024] Fig. 9 Schematic diagram of the layered structure of the array substrate after step S70 in an embodiment of the present invention;

[0025] Fig.10 Schematic diagram of the layered structure of the array substrate after step S80 in an embodiment of the present invention.

[0026] The components in the figure are shown as follows:

[0027] Array substrate 1; Substrate layer 10;

[0028] Active layer 20; First doping part 21;

[0029] A second doped portion 22; A channel portion 23;

[0030] Gate insulating layer 30; First metal layer 40;

[0031] Gate 41; First wiring 42;

[0032] Capacitor dielectric module 50; First dielectric layer 51;

[0033] A second dielectric layer 52; A second metal layer 60;

[0034] Second wiring 61; Interlayer dielectric module 70;

[0035] A third dielectric layer 71; A fourth dielectric layer 72;

[0036] A third metal layer 80; A source electrode 81;

[0037] Drain 82; Third wiring 83;

[0038] A first via hole 91; A second via hole 92;

[0039] The third via hole 93 . DETAILED DESCRIPTION

[0040] The preferred embodiments of the present invention are described below with reference to the drawings in the specification to prove that the present invention can be implemented. The embodiments of the invention can fully introduce the present invention to those skilled in the art, making its technical content clearer and easier to understand. The present invention can be embodied through many different forms of embodiments of the invention, and the protection scope of the present invention is not limited to the embodiments mentioned in the text.

[0041] In the drawings, components with the same structure are indicated by the same numerical reference numerals, and components with similar structures or functions are indicated by similar numerical reference numerals. The size and thickness of each component shown in the drawings are arbitrarily shown, and the present invention does not limit the size and thickness of each component. In order to make the illustration clearer, the thickness of the components is appropriately exaggerated in some places in the drawings.

[0042] In addition, the following descriptions of the various embodiments of the invention are made with reference to the attached diagrams to illustrate specific embodiments of the invention that the present invention can be implemented with. The directional terms mentioned in the present invention, such as "upper", "lower", "front", "back", "left", "right", "inner", "outer", "side", etc., are only with reference to the directions of the attached drawings. Therefore, the directional terms used are for better and clearer description and understanding of the present invention, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first", "second", "third", etc. are used for descriptive purposes only and cannot be understood as indicating or implying relative importance.

[0043] When some components are described as being "on" another component, the component may be directly placed on the other component; there may also be an intermediate component on which the component is placed, and the intermediate component is placed on the other component. When a component is described as being "mounted on" or "connected to" another component, the two may be understood to be directly "mounted on" or "connected", or one component may be indirectly "mounted on" or "connected to" another component via an intermediate component.

[0044] In the relevant process technology of the array substrate, it is usually hydrogenated through a high-temperature annealing process after the interlayer dielectric film layer is opened. However, since the active layer will be exposed in the opening after the interlayer dielectric module is opened, hydrogen ions will escape from the exposed surface of the active layer, resulting in a deterioration in the uniformity of the hydrogen ion content in the active layer, thereby affecting the electrical performance of related circuit devices in the array substrate, and further causing a straight-line display defect (Mura) running through the edge of the screen when the display panel displays a low grayscale screen, seriously affecting the uniformity of the displayed screen.

[0045] In an embodiment of the present invention, a display panel is provided, which can be applied to smart terminals such as mobile phones, computers, and tablet computers, and is used to display images. The display panel includes a stacked array substrate 1 and a light-emitting layer. The light-emitting layer is provided with a plurality of light-emitting devices, which are connected to the array substrate 1. The array substrate 1 controls the brightness of each light-emitting device according to a display signal, thereby lighting up the display panel and realizing image display.

[0046] like Figure 1 As shown, the array substrate 1 includes a substrate layer 10 , an active layer 20 , a gate insulating layer 30 , a first metal layer 40 , a capacitor dielectric module 50 , a second metal layer 60 , an interlayer dielectric module 70 and a third metal layer 80 .

[0047] The substrate layer 10 is a flexible substrate layer 10, which is used to protect the overall structure of the array substrate 1. The substrate layer 10 can be a single-layer flexible material film layer, or can be formed by stacking multiple film layers of different materials, such as a buffer layer of inorganic material and a barrier layer of inorganic material stacked on a flexible PI (polyimide) film layer. In another embodiment of the present invention, the substrate layer 10 can also be a hard substrate, such as a glass plate, a quartz plate, etc.

[0048] The active layer 20 is disposed on a surface of the substrate layer 10, and includes a first doping portion 21, a second doping portion 22 and a channel portion 23. The first doping portion 21 and the second doping portion 22 are respectively disposed at both ends of the channel portion 23. The active layer 20 is made of polycrystalline silicon (Polycrystalline Silicon, P-Si). In another embodiment of the present invention, the active layer 20 can also be made of other semiconductor materials such as amorphous silicon (a-Si), single crystal silicon or metal oxide. Among them, the metal oxide can be one of semiconductor oxides such as indium gallium zinc oxide (IGZO), indium zinc tritium oxide (IZTO), indium gallium zinc tritium oxide (IGZTO) and the like.

[0049] The gate insulating layer 30 is disposed on a surface of the substrate layer 10 and covers the active layer 20. The gate insulating layer 30 can be made of inorganic materials such as silicon oxide (SiOx), silicon nitride (SiNx) or silicon oxynitride (SiOxNy), and is used to insulate the gate 41 from the active layer 20.

[0050] The first metal layer 40 is disposed on a surface of the gate insulating layer 30 away from the active layer 20, and the first metal layer 40 includes a gate 41 and a first wiring 42. The orthographic projection of the gate 41 on the substrate layer 10 is located within the orthographic projection range of the active layer 20 on the substrate layer 10, and the width of the gate 41 is smaller than the width of the active layer 20. Optionally, the central axis of the gate 41 coincides with the central axis of the active layer 20. The first wiring 42 can be one of the signal wirings such as a scan signal line and a reset signal line.

[0051] The capacitor dielectric module 50 is arranged on the gate insulating layer 30 and covers the first metal layer 40. The capacitor dielectric module 50 includes a first dielectric layer 51 and a second dielectric layer 52 which are stacked. Specifically, the first dielectric layer 51 is located on the side of the capacitor dielectric module 50 close to the active layer 20, that is, the first dielectric layer 51 is arranged on a surface of the gate insulating layer 30 away from the active layer 20, and covers the exposed surface of the first metal layer 40; the second dielectric layer 52 is located on the side of the capacitor dielectric module 50 away from the active layer 20, that is, the second dielectric layer 52 is arranged on a surface of the first dielectric layer 51 away from the first metal layer 40. The preparation materials of the first dielectric layer 51 and the second dielectric layer 52 are both insulating inorganic materials. Optionally, the material of the first dielectric layer 51 includes silicon nitride (SiNx), and the material of the second dielectric layer 52 includes silicon oxide (SiOx). The thickness of the first dielectric layer 51 is less than or equal to 500 angstroms, the thickness of the second dielectric layer 52 is greater than or equal to 500 angstroms, and the thickness of the capacitor dielectric module 50 is 1000-1400 angstroms; optionally, the thickness of the second dielectric layer 52 is greater than 500 angstroms, and the thickness of the capacitor dielectric module 50 is 1200 angstroms. In the capacitor dielectric module 50, the first dielectric layer containing silicon nitride (SiNx) is used to provide hydrogen ions when hydrogenating the active layer, and the second dielectric layer 52 containing silicon oxide (SiOx) is used to prevent the hydrogen ions diffused from the first dielectric layer 51 from diffusing to the outside of the array substrate 1.

[0052] The second metal layer 60 is disposed on a surface of the capacitor dielectric module 50 away from the first metal layer 40, that is, on a surface of the second dielectric layer 52 away from the first dielectric layer 51. The second metal layer 60 includes a plurality of second wirings 61, which can be at least one of initial signal lines, power signal lines, storage capacitor wirings, and the like.

[0053] The interlayer dielectric module 70 is arranged on the capacitor dielectric module 50 and covers the second metal layer 60. The interlayer dielectric module 70 includes a third dielectric layer 71 and a fourth dielectric layer 72 which are stacked. Specifically, the third dielectric layer 71 is located on a side of the interlayer dielectric module 70 close to the capacitor dielectric module 50, that is, the third dielectric layer 71 is arranged on a surface of the second dielectric layer 52 away from the first dielectric layer 51, and covers the exposed surface of the second metal layer 60; the fourth dielectric layer 72 is located on a side of the interlayer dielectric module 70 away from the capacitor dielectric module 50, that is, the fourth dielectric layer 72 is arranged on a surface of the third dielectric layer 71 away from the second metal layer 60. The preparation materials of the third dielectric layer 71 and the fourth dielectric layer 72 are both insulating inorganic materials. Optionally, the material of the third dielectric layer 71 includes silicon nitride (SiOx), and the material of the fourth dielectric layer 72 includes silicon nitride (SiNx). In the interlayer dielectric module 70, the third dielectric layer 71 containing silicon nitride (SiOx) is used to insulate and protect the second metal layer 60, and the fourth dielectric layer 72 containing silicon nitride (SiNx) is used to improve the stress resistance of the interlayer dielectric module 70 and prevent the interlayer dielectric module 70 from cracking.

[0054] The array substrate 1 is provided with a first via hole 91 and a second via hole 92, which penetrate the interlayer dielectric module 70, the capacitor dielectric module 50 and the gate insulating layer 30 in sequence, and the orthographic projections of the first via hole 91 and the second via hole 92 on the active layer 20 are respectively located on the first doped portion 21 and the second doped portion 22 of the active layer 20, so that part of the upper surface of the first doped portion 21 and the second doped portion 22 of the active layer 20 (i.e., a surface of the active layer 20 away from the substrate layer 10) is respectively exposed in the first via hole 91 and the second via hole 92. Optionally, the penetration direction of the first via hole 91 and the second via hole 92 is parallel to the stacking direction of the array substrate 1.

[0055] The third metal layer 80 is disposed on a surface of the interlayer dielectric module 70 away from the second metal layer 60, that is, disposed on a surface of the fourth dielectric layer 72 away from the second metal layer 60, and the third metal layer 80 includes a source electrode 81 and a drain electrode 82. Specifically, the source electrode 81 is located at an end of the first via hole 91 away from the active layer 20, fills the first via hole 91, and contacts the exposed surface of the first doped portion 21 of the active layer 20 in the first via hole 91, thereby realizing electrical connection between the source electrode 81 and the active layer 20; the drain electrode 82 is disposed at an end of the second via hole 92 away from the active layer 20, fills the second via hole 92, and contacts the exposed surface of the second doped portion 22 of the active layer 20 in the second via hole 92, thereby realizing electrical connection between the drain electrode 82 and the active layer 20.

[0056] The active layer 20, the gate 41, the source 81 and the drain 82 in the array substrate 1 form the main conductive structure in the thin film transistor (TFT). When the gate 41 is supplied with current and voltage, it will generate an electric field, which will cause the surface of the active layer 20 to generate induced charges, change the width of the conductive channel in the active layer 20, and cause the two doped parts of the active layer 20 to be turned on, thereby achieving the purpose of controlling the current and voltage of the source 81 and the drain 82. The light-emitting device in the display device is electrically connected to the source 81 or the drain 82 in the array substrate 1, and the array substrate 1 further controls the brightness of the light-emitting device by controlling the condition of the thin film transistor.

[0057] Furthermore, the array substrate 1 is provided with a third via hole 93, which penetrates the interlayer dielectric module 70, and its orthographic projection on the second metal layer 60 is located on the second wiring 61, so that part of the upper surface of the second wiring 61 (i.e., a surface of the second metal layer 60 away from the capacitor dielectric module 50) is exposed in the third via hole 93. The third metal layer 80 also includes a third wiring 83, which is located at one end of the third via hole 93 away from the second wiring 61, fills the third via hole 93, and contacts the exposed surface of the second wiring 61, thereby being electrically connected to the second wiring 61.

[0058] The present invention also provides a method for preparing an array substrate 1, which is used to prepare the array substrate 1 as described above. The preparation process of the array substrate 1 is as follows: Figure 2 As shown, it includes steps S10 to S90.

[0059] Step S10) forming an active layer 20 on the substrate layer 10:

[0060] A substrate layer 10 is prepared, and a semiconductor material is deposited on a surface of the substrate layer 10 to form a semiconductor layer; wherein the semiconductor material is polycrystalline silicon; the semiconductor layer is patterned by a photolithography process, and excess semiconductor material is removed to form a semiconductor layer as shown in FIG. Figure 3 The active layer 20 shown in FIG.

[0061] Step S20) forming a gate insulating layer 30 covering the active layer 20 on the substrate layer 10:

[0062] A layer of inorganic material covering the active layer 20 is deposited on one surface of the substrate layer 10 to form a Figure 4 The gate insulating layer 30 is shown in FIG.

[0063] Step S30) forming a first metal layer 40 on the gate insulating layer 30:

[0064] A layer of metal material is deposited on a surface of the gate insulating layer 30 away from the active layer 20 to form a first metal layer 40; the first metal layer 40 is patterned by a photolithography process to form a Figure 5The gate 41 and the first wiring 42 shown in FIG. 4 are shown in FIG. 4 ; wherein the metal material selected for the first metal layer 40 is molybdenum (Mo); in another embodiment of the present invention, the metal material may also be a stacked combination of one or more metal materials with high conductivity such as titanium (Ti), aluminum (Al), copper (Cu), and silver (Ag);

[0065] Furthermore, after forming the gate 41, the active layer 20 is plasma treated, so that a first doped portion 21 and a second doped portion 22 with lower resistance are formed in the active layer 20 without adding a mask, and the active layer 20 located directly below the gate 41 is blocked by the gate 41 and is not doped, thereby maintaining semiconductor characteristics and forming a channel portion 23.

[0066] Step S40) forming a capacitor dielectric module 50 on the gate insulating layer 30:

[0067] A layer of inorganic material covering the first metal layer 40 is deposited on a surface of the gate insulating layer 30 away from the active layer 20 to form a first dielectric layer 51; another layer of inorganic material is deposited on a surface of the first dielectric layer 51 away from the first metal layer 40 to form a second dielectric layer 52; Figure 6 As shown, the first dielectric layer 51 and the second dielectric layer 52 are combined to form a capacitor dielectric module 50; wherein the inorganic material used in the first dielectric layer 51 is silicon nitride (SiNx), and the inorganic material used in the second dielectric layer 52 is silicon oxide (SiOx).

[0068] Step S50) hydrogenating the active layer 20 through a high temperature activation process:

[0069] like Figure 7 As shown, the active layer 20 is hydrogenated in a high temperature environment of 350°C-700°C; specifically, the first dielectric layer 51 of the capacitor dielectric module 50 contains hydrogen ions. When the first dielectric layer 51 is activated at high temperature, it serves as a source of hydrogen ions. The hydrogen ions formed after the Si-H bonds are broken diffuse at high temperature and repair into the dangling bonds in the active layer 20, thereby replenishing hydrogen ions in the active layer 20, reducing the internal defects and surface defects of the active layer 20, and thus improving the performance of the active layer 20;

[0070] In the embodiment of the present invention, the active layer 20 is hydrogenated by a high-temperature activation process after the capacitor dielectric module 50 is prepared. Compared with the operation of hydrogenation after the interlayer dielectric layer structure is prepared in the related art, the hydrogenation path (i.e., the distance between the silicon nitride film layer and the active layer 20) in this embodiment is shorter, the required hydrogenation time is shorter, and the high-temperature time is also shorter, which can greatly improve the production efficiency and reduce the production cost;

[0071] During high-temperature activation, the hydrogen ions in the first dielectric layer 51 will not only diffuse downward (i.e., diffuse toward the active layer 20), but also diffuse upward (i.e., overflow the capacitor dielectric module 50). The lower amount of hydrogen ions diffusing downward will also lead to poor uniformity of the hydrogen ion content in the active layer 20. Therefore, stacking a second dielectric layer 52 containing silicon oxide (SiOx) on the first dielectric layer 51 can effectively prevent the hydrogen ions from diffusing upward, prompting the hydrogen ions in the first dielectric layer 51 to diffuse downward, thereby increasing the concentration of hydrogen ions diffusing downward, and further improving the uniformity of the hydrogen ion content in the active layer 20.

[0072] Step S60) forming a second metal layer 60 on a surface of the capacitor dielectric module 50 away from the first metal layer 40:

[0073] A layer of metal material is deposited on a surface of the second dielectric layer 52 away from the first dielectric layer 51 to form a second metal layer 60; the second metal layer 60 is patterned by a photolithography process to form a Figure 8 The second trace 61 is shown in the figure; wherein the metal material selected for the second metal layer 60 is molybdenum (Mo); in another embodiment of the present invention, the metal material can also be a stacked combination of one or more highly conductive metal materials such as titanium (Ti), aluminum (Al), copper (Cu), and silver (Ag).

[0074] Step S70) forming an interlayer dielectric module 70 on the capacitor dielectric module 50:

[0075] On a surface of the capacitor dielectric module 50 away from the first metal layer 40, that is, on a surface of the second dielectric layer 52 away from the first dielectric layer 51, a layer of inorganic material covering the second metal layer 60 is deposited to form a third dielectric layer 71; on a surface of the third dielectric layer 71 away from the second metal layer 60, another layer of inorganic material is deposited to form a fourth dielectric layer 72; Fig. 9 As shown, the third dielectric layer 71 and the fourth dielectric layer 72 are stacked to form an interlayer dielectric module 70; wherein the inorganic material used in the third dielectric layer 71 is silicon oxide (SiOx), and the inorganic material used in the fourth dielectric layer 72 is silicon nitride (SiNx);

[0076] Furthermore, the thickness of the third dielectric layer 71 and the fourth dielectric layer 72 are both greater than the thickness of the first dielectric layer 51 , so the total thickness of the interlayer dielectric module 70 is greater than the total thickness of the capacitor dielectric module 50 .

[0077] Step S80) forming a via hole on the side of the active layer 20 facing away from the substrate layer 10:

[0078] like Fig.10As shown, through the photolithography process, a plurality of vias are opened in the interlayer dielectric module 70, the capacitor dielectric module 50 and the gate insulating layer 30, and the plurality of vias include a first via 91, a second via 92 and a third via 93; specifically, the first via 91 sequentially penetrates the interlayer dielectric module 70, the capacitor dielectric module 50 and the gate insulating layer 30 to the upper surface of the active layer 20, and corresponds to the first doped portion 21 of the active layer 20; the second via 92 sequentially penetrates the interlayer dielectric module 70, the capacitor dielectric module 50 and the gate insulating layer 30 to the upper surface of the active layer 20, and corresponds to the first doped portion 21 of the active layer 20; The dielectric module 50 and the gate insulating layer 30 extend to the upper surface of the active layer 20, and correspond to the second doped portion 22 of the active layer 20; the third via 93 passes through the interlayer dielectric module 70, and corresponds to the second routing 61 of the second metal layer 60; further, the orthographic projections of the first via 91 and the second via 92 on the active layer 20 are located on both sides of the orthographic projection of the gate 41 on the active layer 20, and the orthographic projections of the first via 91 and the second via 92 do not overlap with the orthographic projection of the gate 41.

[0079] Step S90) Filling the via hole with the third metal layer 80:

[0080] A layer of metal material is deposited on a surface of the fourth dielectric layer 72 away from the third dielectric layer 71, and the layer of metal material fills the first via hole 91, the second via hole 92 and the third via hole 93, and covers the exposed surface of the active layer 20 or the second metal layer 60 in the via hole to form a third metal layer 80; the third metal layer 80 is patterned by a photolithography process to form a Figure 1 The source 81, drain 82 and third wiring 83 shown in the figure; specifically, the source 81 extends from a surface of the fourth dielectric layer 72 away from the active layer 20 to the first via 91, the drain 82 extends from a surface of the fourth dielectric layer 72 away from the active layer 20 to the second via 92, and the third wiring 83 extends from a surface of the fourth dielectric layer 72 away from the second metal layer 60 to the third via 93; wherein the metal material selected for the third metal layer 80 can be a stacked combination of one or more highly conductive metal materials such as molybdenum (Mo), titanium (Ti), aluminum (Al), copper (Cu), and silver (Ag).

[0081] Furthermore, in step S40, the thickness of the first dielectric layer 51 is less than or equal to 500 angstroms, the thickness of the second dielectric layer 52 is greater than or equal to 500 angstroms, and the thickness of the capacitor dielectric module 50 is 1000-1400 angstroms. By reducing the thickness of the first dielectric layer 51, the hydrogen ion content in the capacitor dielectric module 50 is reduced, thereby reducing the hydrogen ion content diffused into the active layer 20 during high-temperature activation in step S50.

[0082] In the array substrate and the preparation method thereof provided in the embodiments of the present invention, the step of performing high-temperature annealing after opening the interlayer dielectric film layer in the related process technology is eliminated. No high-temperature operation is required after the opening, and hydrogen ions will not overflow through the via holes, thereby solving the problem of poor uniformity of hydrogen ion content in the active layer caused by hydrogen ion overflow, improving the stability of circuit devices in the array substrate, and further eliminating linear display defects (Mura) in the display panel, thereby improving the picture uniformity of the display panel when displaying low-gray pictures.

[0083] At the same time, in the embodiment of the present invention, in order to meet the electrical requirements of the array substrate, the step of high temperature hydrogenation (i.e., high temperature activation) is also advanced from after the preparation of the interlayer dielectric module to after the preparation of the capacitor dielectric module. Since the interlayer dielectric module also contains a silicon nitride film layer, advancing the step of high temperature hydrogenation to after the preparation of the capacitor dielectric module can reduce a layer of silicon nitride film layer that is treated at high temperature, thereby reducing the hydrogen ion content that is thermally diffused into the active layer, and preventing the active layer from being electrically unstable due to excessive hydrogen ion content after the high temperature annealing process is cancelled.

[0084] Although the present invention is described herein with reference to specific embodiments, it should be understood that these embodiments are merely examples of the principles and applications of the present invention. It should therefore be understood that many modifications may be made to the exemplary embodiments and that other arrangements may be devised without departing from the spirit and scope of the present invention as defined by the appended claims. It should be understood that the various dependent claims and features described herein may be combined in a manner different from that described in the original claims. It should also be understood that features described in conjunction with individual embodiments may be used in other described embodiments.

Claims

1. A method for preparing an array substrate, characterized in that: include: forming an active layer on the substrate layer; forming a gate insulating layer covering the active layer on the substrate layer; forming a first metal layer on the gate insulating layer; forming a capacitor dielectric module on the gate insulating layer; hydrogenating the active layer through a high temperature activation process; forming an interlayer dielectric module on the capacitor dielectric module; A via hole is formed on a side of the active layer facing away from the substrate layer, and a third metal layer is filled in the via hole.

2. The method for preparing an array substrate according to claim 1, wherein: The step of forming a capacitor dielectric module on the gate insulating layer includes: forming a first dielectric layer covering the first metal layer on a surface of the gate insulating layer away from the active layer; A second dielectric layer is formed on a surface of the first dielectric layer away from the first metal layer.

3. The method for preparing an array substrate according to claim 2, wherein: The thickness of the first dielectric layer is less than or equal to 500 angstroms; The thickness of the capacitor dielectric module is 1000-1400 angstroms.

4. The method for preparing an array substrate according to claim 2, wherein: include: The material of the first dielectric layer includes silicon nitride; The material of the second dielectric layer includes silicon oxide.

5. The method for preparing an array substrate according to claim 1, wherein: The step of forming an interlayer dielectric module on the capacitor dielectric module includes: forming a third dielectric layer on a surface of the capacitor dielectric module away from the first metal layer; A fourth dielectric layer is formed on a surface of the third dielectric layer away from the capacitor dielectric module.

6. The method for preparing an array substrate according to claim 5, wherein: The material of the third dielectric layer includes silicon oxide; The material of the fourth dielectric layer includes silicon nitride; Preferably, the thickness of the interlayer dielectric module is greater than the thickness of the capacitor dielectric module.

7. The method for preparing an array substrate according to claim 1, wherein: Before the step of forming an interlayer dielectric module on the capacitor dielectric module, the step includes: A second metal layer is formed on a surface of the capacitor dielectric module away from the first metal layer.

8. The method for preparing an array substrate according to claim 1, wherein: The steps of forming a via hole on a side of the active layer away from the substrate layer and filling the via hole with a third metal layer include: Opening the via hole in the interlayer dielectric module, the capacitor dielectric module and the gate insulating layer; The third metal layer is formed on a surface of the interlayer dielectric module away from the capacitor dielectric module, and the third metal layer fills the via hole.

9. An array substrate, characterized in that: The array substrate is prepared by the method for preparing the array substrate as described in any one of claims 1 to 8.

10. A display panel, characterized in that: Comprising the array substrate as claimed in claim 9.

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