Semiconductor package and method of identifying plurality of integrated circuit substrates in stacked structure

Abstract

The invention discloses a semiconductor package and a method for identifying a plurality of integrated circuit substrates in a stacked structure. The semiconductor package includes a plurality of integrated circuit substrates and a conductive structure. The plurality of integrated circuit substrates are stacked on top of each other. The conductive structure passes through the plurality of integrated circuit substrates. Each integrated circuit substrate includes an identification circuit coupled to the conductive structure. Each identification circuit is configured to identify a corresponding integrated circuit substrate by receiving an input signal from the conductive structure and thereby generating an identifier of the corresponding integrated circuit substrate. The stacked layers of the semiconductor package can be individually identified according to identifiers, ensuring that system functions can be correctly performed, and achieving accurate testing and failure analysis.

Description

Technical Field

[0001] The present application relates to a semiconductor package, and more particularly to a semiconductor package and a method for identifying a plurality of integrated circuit substrates in a stacked structure. Background Art

[0002] In order to further improve system performance, integration density, signal transmission speed and data processing capacity, more and more electronic products are using three-dimensional semiconductor packaging (3D semiconductor packaging) technology. Three-dimensional semiconductor packaging technology includes chip-on-chip stacking, chip-on-wafer (CoW) stacking, and wafer-on-wafer (WoW) stacking. For example, wafer-to-wafer stacking can achieve vertical integration of multiple chips by vertically connecting multiple wafers. In high-performance computing applications, wafer-to-wafer stacking can increase computing speed and data throughput by vertically integrating multiple processor chips and memory chips. In addition, wafer-to-wafer stacking can be applied to memory devices to increase storage density and read and write speeds. Summary of the invention

[0003] Embodiments of the present application disclose a semiconductor package and a method for identifying a plurality of integrated circuit substrates in a stacked structure.

[0004] Certain embodiments of the present application include a semiconductor package. The semiconductor package includes a plurality of integrated circuit substrates and a conductive structure. The plurality of integrated circuit substrates are stacked one above the other. The conductive structure passes through the plurality of integrated circuit substrates. Each integrated circuit substrate includes an identification circuit coupled to the conductive structure. Each identification circuit is used to identify the corresponding integrated circuit substrate by receiving an input signal from the conductive structure and generating an identifier of the corresponding integrated circuit substrate accordingly.

[0005] Certain embodiments of the present application include a method for identifying a plurality of integrated circuit substrates in a stacked structure. The method includes: when each integrated circuit substrate is in an unselectable state, by assigning a first identifier to a first integrated circuit substrate among the plurality of integrated circuit substrates, converting the first integrated circuit substrate from an unselectable state to an selectable state; applying an input signal to a conductive structure, the conductive structure passing through the plurality of integrated circuit substrates in the stack; and identifying a second integrated circuit substrate among the plurality of integrated circuit substrates by referring to the input signal and generating a second identifier, wherein the second integrated circuit substrate is adjacent to the first integrated circuit substrate.

[0006] Through the identification scheme disclosed in the present application, each layer in the chip / wafer stack can be assigned a corresponding unique identifier based on the physical spatial relationship between the stacked layers. The identification scheme disclosed in the present application can individually identify the stacked layers based on the corresponding identifiers, thereby ensuring that the system functions can be executed correctly and achieving accurate testing and failure analysis. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The various aspects of the present application can be clearly understood by reading the following embodiments in conjunction with the accompanying drawings. It should be noted that, according to standard practice in the art, the various features in the drawings are not necessarily drawn to scale. In fact, in order to be able to describe clearly, the size of certain features can be arbitrarily enlarged or reduced.

[0008] Figure 1 is a schematic diagram of an exemplary semiconductor package according to some embodiments of the present application.

[0009] Figure 2A According to some embodiments of the present application Figure 1 A schematic diagram of an embodiment of an integrated circuit substrate is shown.

[0010] Figure 2B According to some embodiments of the present application Figure 1 FIG. 1 is a schematic diagram of another embodiment of an integrated circuit substrate.

[0011] FIG. 3A to FIG. 3C According to some embodiments of the present application, Figure 1 A schematic diagram showing the location of the controller for the identification circuit is shown.

[0012] Figure 4 According to some embodiments of the present application Figure 1 A schematic diagram of an embodiment of a semiconductor package is shown.

[0013] Figure 5 According to some embodiments of the present application Figure 4A schematic diagram of an embodiment of an identification circuit is shown.

[0014] Figure 6 According to some embodiments of the present application Figure 1 A schematic diagram of another embodiment of a semiconductor package is shown.

[0015] Figure 7 According to some embodiments of the present application Figure 1 A schematic diagram of another embodiment of a semiconductor package is shown.

[0016] Figure 8 According to some embodiments of the present application Figure 7 A schematic diagram of an embodiment of an identification circuit is shown.

[0017] Fig. 9 According to some embodiments of the present application Figure 1 A schematic diagram of another embodiment of a semiconductor package is shown.

[0018] Fig.10 According to some embodiments of the present application Figure 1 A schematic diagram of another embodiment of a semiconductor package is shown.

[0019] Fig.11 is a flow chart of an exemplary method for identifying a plurality of integrated circuit substrates in a stacked structure according to some embodiments of the present application. DETAILED DESCRIPTION

[0020] The following disclosure discloses a variety of implementations or illustrations that can be used to implement different features of the present application. The specific examples of components and arrangements described below are used to simplify the present application. As can be imagined, these descriptions are only examples and are not intended to limit the present application. For example, the present application may reuse component symbols and / or labels in the embodiments. This repetition is based on the purpose of simplicity and clarity, and does not itself represent the relationship between the different embodiments and / or configurations discussed.

[0021] In addition, if one component is described as being “connected to” or “coupled to” another component, the two components may be directly connected or coupled, or other intervening components may be present between the two components.

[0022] Furthermore, for ease of description, spatially relative terms such as "below," "above," "left," "right," and the like may be used herein to describe the relationship of one component or member to another component or members as shown in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. Moreover, the device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein shall be interpreted accordingly.

[0023] In a semiconductor structure using three-dimensional packaging, multiple chips / wafers stacked on each other may correspond to the same function. Because it may be difficult to distinguish these chips / wafers based on electrical characteristics and operations, when you want to access a chip, you may accidentally access another chip with the same function. For example, when you want to address the memory circuit of a chip, you may mistakenly address the memory circuit of another chip; for another example, when you want to perform failure analysis (FA) on the circuit of a chip, you may accidentally perform failure analysis on the circuit of another chip.

[0024] The present application discloses a scheme capable of identifying each wafer / chip in a wafer / chip stack. For example, the identification scheme disclosed in the present application can use the identification circuit built into each wafer / chip to assign a unique identifier (or exclusive identifier) ​​to the wafer / chip. For example, the identification circuit can send a signal between adjacent wafers / chips to generate a unique identifier for the corresponding wafer / chip; for another example, the identification circuit can refer to the signal transmitted through the conductive structure (which passes through the wafers / chips stacked on each other and is shared by these wafers / chips) to generate a unique identifier for the corresponding wafer / chip.

[0025] In certain embodiments, the identification scheme disclosed in the present application can utilize the physical spatial relationship between wafers / chips stacked on each other to provide a unique identifier for each stacked layer. Please note that the identification scheme disclosed in the present application can be applied not only to chips / wafers with the same function and stacked on each other, but also to chips / wafers with different functions and stacked on each other. Through the identification scheme disclosed in the present application, multi-layer chips / wafers stacked together can be individually / separately identified to ensure that system functions can be performed correctly and to achieve accurate testing and failure analysis. Further explanation is as follows.

[0026] Figure 11 is a schematic diagram of an exemplary semiconductor package according to certain embodiments of the present application. The semiconductor package 100 includes (but is not limited to) a plurality of integrated circuit (IC) substrates 110[0]-110[P] (P is greater than 1) and a conductive structure 120. The IC substrates 110[0]-110[P] are stacked one above the other and may be (P+1) wafers, dies or chips stacked one above the other. The conductive structure 120 penetrates through the IC substrates 110[0]-110[P] to electrically connect the IC substrates 110[0]-110[P] to each other. The conductive structure 120 may include a plurality of through-substrate vias (TSVs) or through-silicon vias (TSVs).

[0027] Each IC substrate may include an identification circuit (i.e., one of the identification circuits 112[0]-112[P]) for identifying the corresponding IC substrate. In this embodiment, the identification circuit 112[i] (i=0, 1, ..., P) may generate an identifier ID[i] corresponding to the IC substrate 110[i]. The identifier ID[i] may provide information to identify or label the IC substrate 110[i]. For example (but the present application is not limited thereto), the identifier ID[i] may be a multi-bit signal or data corresponding to an IC substrate address pointing to the IC substrate 110[i]; for another example, the identifier ID[i] may be a multi-bit signal or data used to uniquely identify the IC substrate 110[i]. The contents of the identifiers corresponding to different IC substrates are different from each other, that is, the identification circuit 112[i] may generate an identifier that is exclusive to the IC substrate 110[i].

[0028] In addition, the order of the identifiers ID[0]-ID[P] may match the spatial arrangement order of the IC substrates 110[0]-110[P]. For example (but the present application is not limited thereto), the values / patterns indicated by the identifiers ID[0]-ID[P] may be in an increasing or decreasing relationship to indicate the spatial arrangement of the IC substrates 110[0]-110[P] stacked in sequence.

[0029] In some embodiments, some or all of the IC substrates 110[0]-110[P] may be identical to each other. For example, the identical IC substrates may have the same core structure / function; for another example, the identical IC substrates may be memory IC substrates, such as dynamic random-access memory (DRAM) having the same capacity or density. These identical IC substrates may be accessed through a shared conductive structure 120. In a case where it is difficult to electrically distinguish an IC substrate of interest in a stack of IC substrates based on the structure / function of the IC substrate, the IC substrate of interest may be correctly identified and accessed through an identifier obtained by an identification circuit built into each IC substrate.

[0030] Figure 2A According to some embodiments of the present application Figure 1 Schematic diagram of an embodiment of IC substrates 110[0]-110[P] is shown. In this embodiment, IC substrates 110[1]-110[P] are identical to each other, while IC substrate 110[0] is non-identical to IC substrates 110[1]-110[P]. For example, IC substrates 110[1]-110[P] may have the same structure / function, while IC substrate 110[0] may have a structure / function that is different from the structure / function of IC substrates 110[1]-110[P]. Each of the IC substrates 110[1]-110[P] may be referred to as an identical layer (i.e., the same wafer / die / chip), and the IC substrates 110[1]-110[P] may be considered as an IC structure 102A having multiple identical layers; the IC substrate 110[0] may be referred to as a non-identical layer (i.e., a different wafer / die / chip), and the IC substrate 110[0] may be considered as at least a portion of the IC structure 102B having at least one non-identical layer. In some embodiments, multiple IC substrates in the IC substrates 110[0]-110[P] may be different from other IC substrates.

[0031] For example (but the present application is not limited thereto), the IC substrates 110[1]-110[P] can be implemented as a memory IC substrate, which includes at least one memory (such as a dynamic random access memory); the IC substrate 110[0] can be implemented as a logic IC substrate, which includes one or more processors (such as a central processing unit (CPU) and / or a graphics processing unit (GPU)). In some embodiments, the identifiers of non-same layers (i.e., the identifier ID[0] of the IC substrate 110[0]) can be determined first; the identifiers of the same layer can be generated based on the identifiers of the non-same layers and the spatial arrangement of the same layer. Please note that this is not intended to limit the scope of the present application.

[0032] Figure 2B According to some embodiments of the present application Figure 1 Schematic diagram of another embodiment of IC substrates 110[0]-110[P] shown. In this embodiment, IC substrates 110[0]-110[P] are identical to each other, or have the same structure / function. IC substrates 110[0]-110[P] can be considered as multiple identical layers (i.e., identical wafers / bare die / chips). For example (but the present application is not limited to this), IC substrates 110[0]-110[P] can be implemented as memory IC substrates including memory (such as dynamic random access memory). In some embodiments, an identifier of one identical layer among multiple identical layers can be determined first (for example, identifier ID[0] / ID[P] of IC substrates 110[0] / 110[P] located at the outermost side in the stacking structure); identifiers of other identical layers can be generated based on the determined identifiers and the spatial arrangement of the identical layers. Please note that this is not intended to limit the scope of the present application.

[0033] Please refer again Figure 1 Each identification circuit can be coupled to the conductive structure 120. Each identification circuit is used to receive an input signal S from the conductive structure 120. IN , and accordingly determine the identifier of the corresponding IC substrate, thereby identifying the IC substrate.

[0034] For example (but the present application is not limited thereto), the input signal S IN It may be an address input for selecting an IC substrate, wherein the selected IC substrate is assigned an input signal S IN The unique identifier corresponding to the indicated address; for example, the input signal S IN It may be a voltage signal that is applied to each IC substrate to determine the next IC substrate to be identified.

[0035] In this embodiment, the input signal S IN The identification circuits 112[0]-112[P] may have different signal values / patterns corresponding to the contents of the identifiers ID[0]-ID[P], respectively. In some embodiments, the identification circuits 112[0]-112[P] may sequentially generate the respective identifiers ID[0]-ID[P]. For example, the identification circuit 112[0] may generate the respective identifiers ID[0]-ID[P] according to the input signal S having the first signal value. IN The identification circuit 112[0] may generate an identifier ID[0] according to the input signal S having the second signal value. IN The identifier ID[1] is generated, and so on. That is, the identification circuits 112[0]-112[P] can determine the respective identifiers ID[0]-ID[P] in sequence based on the spatial arrangement order of the IC substrates 110[0]-110[P].

[0036] Additionally or alternatively, the input signal S IN In some embodiments, the address corresponding to the identifier of the IC substrate can be indicated, and the identification circuit located on the IC substrate can send a stimulus signal to another identification circuit located on another IC substrate, so that the other identification circuit can be enabled according to the input signal S IN For example, the identification circuit 112[0] may send an excitation signal to the adjacent identification circuit 112[1], so that the identification circuit 112[1] generates a corresponding identifier according to the input signal S IN Generate the corresponding identifier ID[1].

[0037] The identification circuits 112[0]-112[P] may be controlled by a control circuit, which may be located externally or internally to the IC substrates 110[0]-110[P]. FIG. 3A to FIG. 3C According to some embodiments of the present application, Figure 1 The schematic diagram of the setting position of the controller of the identification circuit 112[0]-112[P] is shown. Figure 3A The identification circuits 112[0]-112[P] may be controlled by a control circuit 330 located outside the IC substrate 110[0]-110[P]. The control circuit 330 is coupled to the conductive structure 120 to generate signals related to the operation of the identification circuits 112[0]-112[P], such as the input signal S IN .exist Figure 3A In the illustrated embodiment, the control circuit 330 may be included in the semiconductor package 100 .

[0038] See also Figure 3BThe identification circuits 112[0]-112[P] may be controlled by a control circuit 330 located in the IC substrate 110[0]. The control circuit 330 is coupled to the conductive structure 120 to generate signals related to the operation of the identification circuits 112[0]-112[P], such as an input signal S IN The IC substrate 110 [ 0 ] can be a non-same layer or a same layer, that is, the control circuit 330 can be built in a non-same layer or a same layer.

[0039] See also Figure 3C The identification circuits 112[0]-112[P] may be controlled by a control circuit 330 located in a tester 302. The tester 302 may be an integrated circuit tester or a semiconductor tester located outside the semiconductor package 100. The control circuit 330 is coupled to the conductive structure 120 to generate signals related to the operation of the identification circuits 112[0]-112[P], such as an input signal S IN . FIG. 3A to FIG. 3C The control circuit 330 shown can be implemented as a logic controller, a logic circuit, an application-specific integrated circuit (ASIC), or other types of control circuits.

[0040] To facilitate understanding of the content of this application, some embodiments are given below to illustrate the wafer / chip identification solution disclosed in this application. However, this is for illustrative purposes and is not intended to limit the scope of this application. Those skilled in the art should understand that other embodiments may be used. Figure 1 Implementations of using the architecture shown to identify each wafer / die / chip in a stack of wafers / die / chips are within the scope of the present application.

[0041] Figure 4 According to some embodiments of the present application Figure 1 Schematic diagram of an embodiment of a semiconductor package 100 is shown. In this embodiment, the semiconductor package 400 may include IC substrates 410[0]-410[N] (N is greater than 1) stacked on top of each other and a conductive structure 420. The IC substrates 410[0]-410[N] may be stacked with Figure 1 The IC substrates 110[0]-110[P] shown are substantially the same / similar, or can be used as Figure 1 1 and 110 [0] - 110 [P] are shown. IC substrates 410 [1] - 410 [N] may be implemented as the same layer, while IC substrate 410 [0] may be implemented as a different layer. Conductive structure 420 may be implemented as Figure 1 The conductive structures 120 shown are substantially the same / similar to, or may be used as Figure 11. The IC substrates 410[0]-410[N] include identification circuits 412[0]-412[N], respectively, which can be used with Figure 1 The identification circuits 112[0]-112[P] shown are substantially the same / similar to, or can be used as Figure 1 Implementations of identification circuits 112[0]-112[P] are shown.

[0042] The identification circuits 412[0]-412[N] may identify the IC substrates 410[0]-410[N] by wireless coupling. In this embodiment, each identification circuit may include a coupling circuit (i.e., one of the coupling circuits 416[0]-416[N]) that may be used to send and receive an excitation signal. The excitation signal may be sent or received by wireless coupling (such as inductive or capacitive coupling) between coupling circuits (or between identification circuits) of adjacent IC substrates. For example, each coupling circuit may be implemented as an inductive coupling circuit (such as an inductive element or an inductive coil), the induced voltage generated by the inductive coupling circuit may be used as an excitation signal, and the coupling circuits 416[0]-416[N] may be used as an inductive coupling chain; for another example, each coupling circuit may be implemented as a capacitive coupling circuit (such as a capacitive element or a flat electrode), the induced current generated by the capacitive coupling circuit may be used as an excitation signal, and the coupling circuits 416[0]-416[N] may be used as a capacitive coupling chain.

[0043] The identification circuits 412[0]-412[N] can utilize the interaction between adjacent coupling circuits to generate identifiers ID[0]-ID[N], which can indicate the spatial arrangement relationship between the IC substrates 410[0]-410[N]. For example, the excitation signal sent by the first coupling circuit can cause the second coupling circuit adjacent to the first coupling circuit to generate an induction signal, and the identification circuit including the second coupling circuit can generate an identifier accordingly. Other coupling circuits that are not adjacent to the first coupling circuit will not (or almost will not) respond to the excitation signal sent by the first coupling circuit. Therefore, the two identification circuits that sequentially generate their respective identifiers can be located in two adjacent IC substrates respectively. In some examples where the contents of the identifiers ID[0]-ID[N] are represented in an increasing or decreasing order, two adjacent identifiers can correspond to two adjacent IC substrates.

[0044] In this embodiment, each identification circuit can be controlled by a control circuit 430 located outside the IC substrate 410[0]-410[N]; the control circuit 430 can enable the coupling circuit of the identification circuit to generate an excitation signal. The control circuit 430 can be a logic controller disposed in the semiconductor package 400, or a logic controller disposed in a test system outside the semiconductor package 400.

[0045] During operation, the control circuit 430 may first reset the IC substrates 410[1]-410[N] to a non-selectable state, and set the identifier ID[0] of the IC substrate 410[0] to data ID0, so that the IC substrate 410[0] is in a selectable state. In this embodiment, if the IC substrate is in a selectable state, it may represent that the IC substrate is selectable, or that the IC substrate has been identified; if the IC substrate is in a non-selectable state, it may represent that the IC substrate is not selectable, or that the IC substrate has not been identified. When the identifier of the IC substrate is generated, the IC substrate can be identified.

[0046] For example, the identification circuit 412[i] (i=0, 1, ..., N) may store or register status information ST[i], which may indicate whether the IC substrate 410[i] is in a selectable state, or whether the IC substrate 410[i] has been identified. The control circuit 430 may set the status information ST[1]-ST[N] to indicate that the IC substrates 410[1]-410[N] are in an unselectable state. In addition, the control circuit 430 may assign an address signal indicating data ID0 to the identification circuit 412[0] to set the identifier ID[0] to data ID0, and set the status information ST[0] to indicate that the IC substrate 410[0] is in a selectable state.

[0047] Next, the control circuit 430 may select the IC substrate 410[0] and cause the IC substrate 410[0] to send an excitation signal SS[0]. The adjacent IC substrate 410[1] may receive the excitation signal SS[0], generate an identifier ID[1] accordingly, and set the IC substrate 410[1] to a selectable state.

[0048] For example, the control circuit 430 may send an input signal S IN (which indicates the address corresponding to the identifier ID[0]) to select the IC substrate 410[0], and cause the coupling circuit 416[0] of the identification circuit 412[0] to send the excitation signal SS[0]. The adjacent identification circuit 412[1] can receive the excitation signal SS[0] and INThe identifier ID[1] is set to data ID1 (e.g., data ID0 plus a predetermined value or a predetermined address offset). Other identification circuits not adjacent to the identification circuit 412[0] will not (or almost not) respond to the stimulus signal SS[0]. In addition, the identification circuit 412[1] can set the state information ST[1] according to the stimulus signal SS[0], which can indicate that the IC substrate 410[1] is in a selectable state.

[0049] After the identifier ID[1] is generated, the control circuit 430 can select the IC substrate 410[1] and cause the identification circuit 412[1] to generate an excitation signal SS[1]. The adjacent IC substrate 410[2] can receive the excitation signal SS[1], generate the identifier ID[2] accordingly, and set the IC substrate 410[2] to a selectable state.

[0050] For example, the control circuit 430 may send an input signal S IN (which indicates the address corresponding to the identifier ID[1]) to select the IC substrate 410[1], and make the coupling circuit 416[1] of the identification circuit 412[1] send the excitation signal SS[1]. The adjacent identification circuit 412[2] can receive the excitation signal SS[1] and IN The identifier ID[2] is set to data ID2 (eg, data ID1 plus a predetermined value or a predetermined address offset). In addition, the identification circuit 412[2] can set the state information ST[2] according to the stimulation signal SS[1], which can indicate that the IC substrate 410[2] is in a selectable state.

[0051] Note that the adjacent identification circuit 412[0] (which is already in a selectable state or has been identified) does not (or hardly) respond to the excitation signal SS[1]. When the excitation signal SS[1] is sent to the IC substrate 410[0], the identifier ID[0] of the identification circuit 412[0] may remain unchanged. In other words, the identification circuit 412[0] may ignore the excitation signal SS[1] according to the state information ST[0] (which indicates that the IC substrate 410[0] has been identified); the identifier ID[0] of the IC substrate 410[0] may remain at data ID0.

[0052] Similarly, after the identifier ID[2] is generated, the control circuit 430 can select the IC substrate 410[2] and make the identification circuit 412[2] generate the excitation signal SS2. The adjacent IC substrate 410[3] can receive the excitation signal SS2, generate the identifier ID[3] accordingly, and set the IC substrate 410[3] to a selectable state.

[0053] For example, the control circuit 430 may send an input signal SIN (which indicates the address corresponding to the identifier ID[2]) to select the IC substrate 410[2], and cause the coupling circuit 416[2] of the identification circuit 412[2] to send the excitation signal SS[2]. The adjacent identification circuit 412[3] can receive the excitation signal SS[2] and IN The identifier ID[3] is set to data ID3 (e.g., data ID2 plus a predetermined value or a predetermined address offset). In addition, the identification circuit 412[3] can set the state information ST[3] according to the excitation signal SS[2], which can indicate that the IC substrate 410[3] is in a selectable state. Please note that the adjacent identification circuit 412[1] (which is already in a selectable state or has been identified) will not (or almost will not) respond to the excitation signal SS[2]. When the excitation signal SS[2] is sent to the IC substrate 410[1], the identifier ID[1] of the identification circuit 412[1] can remain unchanged. In other words, the identification circuit 412[1] can ignore the excitation signal SS[2] according to the state information ST[1] (which indicates that the IC substrate 410[1] has been identified); the identifier ID[1] of the IC substrate 410[1] can remain at data ID1.

[0054] After the identifiers ID[0]-ID[N] are stored in the IC substrates 410[0]-410[N] respectively, the control circuit 430 can select the IC substrates 410[0]-410[N] individually according to the identifiers ID[0]-ID[N].

[0055] Figure 5 According to some embodiments of the present application Figure 4 Schematic diagram of an implementation of the identification circuit 412[i] (i=0, 1, ..., N) shown. The identification circuit 412[i] may include (but is not limited to) a storage device 514, a coupling circuit 516, and a processing circuit 518. The storage device 514 is used to store Figure 4 The state information ST[i] and the identifier ID[i] of the IC substrate 410[i] are shown. The storage device 514 can be implemented by a volatile or non-volatile storage device. The coupling circuit 516 is used to receive the drive signal SD and generate the excitation signal SS[i] according to the drive signal SD. The processing circuit 518 is coupled to the storage device 514 and the coupling circuit 516 to determine the input signal S IN Whether the address corresponding to the identifier ID[i] of the IC substrate 410[i] is indicated, the drive signal SD is selectively generated. For example, when the input signal S INWhen the address corresponding to the identifier ID[i] is indicated, the processing circuit 518 can generate a driving signal SD; when the input signal S IN When there is no match with the identifier ID[i], the processing circuit 518 does not generate the driving signal SD.

[0056] In addition or alternatively, the coupling circuit 516 is used to receive the excitation signal SR and generate the sensing signal SN according to the excitation signal SR. When the state information ST[i] indicates an unselectable state, the processing circuit 518 is used to receive the sensing signal SN, refer to the input signal S IN To generate the identifier ID[i], and update the state information ST[i] to indicate that the IC substrate 410[0] is in a selectable state. Please note that when the state information ST[i] indicates that the IC substrate 410[0] is in a selectable state, the processing circuit 518 does not respond to the sensing signal SN.

[0057] Please include Figure 4 See also Figure 5 ,by Figure 4 The identification circuit 412[1] shown uses Figure 5 Taking the structure shown in FIG. 1 (ie, i=1) as an example, when the control circuit 430 is used to send the input signal S IN (which indicates the address corresponding to the identifier ID[0]) to select the IC substrate 410[0], the processing circuit 518 can determine the input signal S IN The indicated address does not match the identifier ID[1] (read from the storage device 514). Therefore, the processing circuit 518 does not generate the drive signal SD. When the IC substrate 410[0] is selected and sends the excitation signal SS[0], the coupling circuit 516 generates the sensing signal SN according to the excitation signal SR (i.e., the excitation signal SS[0] sent by the IC substrate 410[0]). The processing circuit 518 can receive the sensing signal SN and read the status information ST[1] (which indicates that the IC substrate 410[1] is in an unselectable state) from the storage device 514. The processing circuit 518 can refer to the input signal S IN An identifier ID[1] is generated, and the status information ST[1] is updated to indicate that the IC substrate 410[1] is in a selectable state.

[0058] by Figure 4 The identification circuit 412[0] shown uses Figure 5 Taking the structure shown in FIG. 1 (ie, i=0) as an example, when the control circuit 430 is used to send the input signal S IN (which indicates the address corresponding to the identifier ID[0]) to select the IC substrate 410[0], the processing circuit 518 can determine the input signal S INThe indicated address corresponds to the identifier ID[0] (read from the storage device 514), and it is determined that the state information ST[0] (read from the storage device 514) indicates that the IC substrate 410[0] is in a selectable state. Therefore, the processing circuit 518 can generate the drive signal SD. In addition, when the control circuit 430 is used to send the input signal S IN (which indicates the address corresponding to the identifier ID[1]) so that the IC substrate 410[1] generates the excitation signal SS[1], the coupling circuit 516 can generate the sensing signal SN according to the excitation signal SR (i.e., the excitation signal SS[1] sent by the IC substrate 410[1]). Since the state information ST[0] read from the storage device 514 indicates that the IC substrate 410[0] is in a selectable state, the processing circuit 518 will not respond to the sensing signal SN. In other words, the processing circuit 518 will not change / update the identifier ID[0].

[0059] Since those skilled in the art should be aware of Figure 5 The architecture shown can be applied to Figure 4 Each identification circuit is shown, therefore, similar descriptions are not repeated here.

[0060] Figure 6 According to some embodiments of the present application Figure 1 FIG. 6 is a schematic diagram of another embodiment of the semiconductor package 100 shown in FIG. 600 , except that the stacked IC substrates included in the semiconductor package 600 are all implemented as the same layer. Figure 4 The structure of the semiconductor package 400 shown in FIG. 6 is substantially the same. In this embodiment, the semiconductor package 600 includes Figure 4 IC substrates 410 [ 1 ] - 410 [N] and conductive structures 420 are shown.

[0061] During operation, the control circuit 430 may first reset the IC substrates 410[2]-410[N] to an unselectable state, and set the identifier ID[1] of the IC substrate 410[1] to data ID1, so that the IC substrate 410[1] is in a selectable state.

[0062] For example, the control circuit 430 may set the state information ST[2]-ST[N] to indicate that the IC substrates 410[2]-410[N] are in an unselectable state, and set the state information ST[1] to indicate that the IC substrate 410[1] is in an selectable state. IN Set the identifier ID[1] to data ID1. Input signal S IN It may include (but is not limited to) an address input indicating data ID1.

[0063] Next, the control circuit 430 may select the IC substrate 410[1] and cause the IC substrate 410[1] to send an excitation signal SS[1]. The adjacent IC substrate 410[2] may receive the excitation signal SS[1], generate an identifier ID[2] accordingly, and set the IC substrate 410[2] to a selectable state.

[0064] For example, the control circuit 430 may send an input signal S IN (which indicates the address corresponding to the identifier ID[1]) to select the IC substrate 410[1], and cause the coupling circuit 416[1] of the identification circuit 412[1] to send the excitation signal SS[1]. The adjacent identification circuit 412[2] can receive the excitation signal SS[1] and IN The identifier ID[2] is set to data ID2 (eg, data ID1 plus a predetermined value or a predetermined address offset). In addition, the identification circuit 412[2] can set the state information ST[2] according to the stimulation signal SS[1], which can indicate that the IC substrate 410[2] is in a selectable state.

[0065] After the identifier ID[2] is generated, the control circuit 430 can select the IC substrate 410[2] and cause the identification circuit 412[2] to generate the excitation signal SS[2]. The adjacent IC substrate 410[3] can receive the excitation signal SS[2], generate the identifier ID[3] accordingly, and set the IC substrate 410[3] to a selectable state.

[0066] For example, the control circuit 430 may send an input signal S IN (which indicates the address corresponding to the identifier ID[2]) to select the IC substrate 410[2], and cause the coupling circuit 416[2] of the identification circuit 412[2] to send the excitation signal SS[2]. The adjacent identification circuit 412[3] can receive the excitation signal SS[2] and IN The identifier ID[3] is set to data ID3 (e.g., data ID2 plus a predetermined value or a predetermined address offset). In addition, the identification circuit 412[3] can set state information ST[3] based on the stimulation signal SS[2], which can indicate that the IC substrate 410[3] is in a selectable state. The identification circuit 412[1] (which is already in a selectable state, or has been identified) will not (or almost will not) respond to the stimulation signal SS[2]. When the IC substrate 410[1] has been identified, the identifier ID[1] of the IC substrate 410[1] will not be modified by the stimulation signal SS[2].

[0067] Since the technicians in this field read Figures 1 to 5 After reading the relevant paragraphs, you should be able to understand Figure 6The operation details of the semiconductor package 600 are shown, and therefore, further description is not repeated here.

[0068] Figure 7 According to some embodiments of the present application Figure 1 FIG. 1 is a schematic diagram of another embodiment of a semiconductor package 100. In this embodiment, the semiconductor package 700 may include IC substrates 710[0]-710[N] (N is greater than 1) stacked one above the other and a conductive structure 720. The IC substrates 710[0]-710[N] may be stacked with Figure 1 The IC substrates 110[0]-110[P] shown are substantially the same / similar, or can be used as Figure 1 1 and 110 [0] - 110 [P] are shown. IC substrates 710 [1] - 710 [N] may be implemented as the same layer, while IC substrate 710 [0] may be implemented as a different layer. Conductive structure 720 may be implemented as Figure 1 The conductive structures 120 shown are substantially the same / similar to, or may be used as Figure 1 1. The IC substrates 710[0]-710[N] include identification circuits 712[0]-712[N], respectively, which can be used with Figure 1 The identification circuits 112[0]-112[P] shown are substantially the same / similar to, or can be used as Figure 1 Implementations of identification circuits 112[0]-112[P] are shown.

[0069] The identification circuits 712[0]-712[N] can use voltage division to identify the IC substrates 710[0]-710[N]. In this embodiment, the conductive structure 720 includes conductive paths 721 and 722 that pass through the IC substrates 710[1]-710[N]. Both conductive paths 721 and 722 can be substrate through-holes shared by the identification circuits 712[0]-712[N]. The reference voltage Vref applied to the conductive path 721 can be used as Figure 1 The input signal S shown IN In addition, the two ends of the conductive path 722 are connected to different potentials to form a voltage divider 724 having a plurality of nodes N[0]-N[N], and the segment between two adjacent nodes on the conductive path 722 serves as a resistive element of the voltage divider 724. Figure 7 In the illustrated embodiment, two ends of the conductive path 722 are respectively coupled to a predetermined voltage Vsrc (a source voltage applied to the IC substrate 710 [N]) and a predetermined voltage Vss (a reference voltage applied to the IC substrate 710 [0]).

[0070] The identification circuits 712[0]-712[N] are coupled to nodes N[0]-N[N], respectively. Each identification circuit is used to determine the identifier of the corresponding IC substrate by comparing the reference voltage Vref with the node voltage of the corresponding node. The node voltage is a proportionally divided voltage between a predetermined voltage Vsrc and a predetermined voltage Vss. The identification circuits 712[0]-712[N] can generate identifiers ID[0]-ID[N] by detecting the corresponding divided voltages, which can indicate the spatial arrangement relationship between the IC substrates 712[0]-712[N].

[0071] For example, each identification circuit may include a comparator (i.e., one of the comparators 716[0]-716[N]), wherein a first input terminal and a second input terminal of each comparator are respectively coupled to a corresponding node and a reference voltage Vref. By adjusting the reference voltage Vref, the voltage levels of the nodes N[0]-N[N] to which the identification circuits 712[0]-712[N] are coupled may be detected, thereby generating identifiers ID[0]-ID[N]. Since the voltage levels of the nodes N[0]-N[N] may be in an increasing relationship, the values / patterns indicated by the identifiers ID[0]-ID[N] may represent the spatial arrangement relationship between the IC substrates 712[0]-712[N].

[0072] In this embodiment, each identification circuit may be controlled by a control circuit 730 located outside the IC substrate 710[0]-710[N], and both the predetermined voltage Vsrc and the reference voltage Vref may be provided by the control circuit 730. The control circuit 730 may be a logic controller located in the semiconductor package 700, or a logic controller located in a test system outside the semiconductor package 700.

[0073] During operation, the control circuit 730 may first reset the IC substrates 710[1]-710[N] to an unselectable state, and set the identifier ID[0] of the IC substrate 710[0] to data ID0, so that the IC substrate 710[0] is in a selectable state.

[0074] For example, the identification circuit 712[i] (i=0, 1, ..., N) may store or record status information ST[i], which may indicate whether the IC substrate 710[i] is in a selectable state, or whether the IC substrate 710[i] has been identified. The control circuit 730 may set the status information ST[1]-ST[N] to indicate that the IC substrates 710[1]-710[N] are in an unselectable state. In addition, the control circuit 730 may assign an address signal indicating data ID0 to the identification circuit 712[0] to set the identifier ID[0] to data ID0, and set the status information ST[0] to indicate that the IC substrate 710[0] is in a selectable state.

[0075] Next, the control circuit 730 may apply the predetermined voltage Vsrc to the voltage divider 724. In the case where the predetermined voltage Vss is the ground voltage, the voltage level V(i) of the node N[i] in the IC substrate 710[i] (i=0, 1, ..., N) is equal to (or substantially equal to) VLsrc×(i / N), where VLsrc represents the voltage level of the predetermined voltage Vsrc.

[0076] For example, the control circuit 730 may apply a predetermined voltage Vsrc to one end of the conductive path 722 located at the substrate 710[N], while the other end of the conductive path 722 located at the substrate 710[0] is coupled to the ground voltage. The voltage level of the first input terminal (coupled to the node N[i]) of the comparator 716[i] is equal to (or substantially equal to) VLsrc×(i / N).

[0077] In addition, the control circuit 730 may set the voltage level VLref of the reference voltage Vref to be between V(1) and V(2), and apply the reference voltage Vref to the second input terminal of each comparator. The comparator 716[i] (i=0, 1, ..., N) is used to compare the voltage level V(i) with the voltage level VLref. When the comparison result of the comparator indicates that the voltage level VLref is greater than the voltage level V(1), and the IC substrate corresponding to the comparator is in an unselectable state, the control circuit 730 may set the IC substrate to a selectable state and assign data ID1 to the identifier of the IC substrate.

[0078] For example, the comparison result of the comparator 716[1] may indicate that the voltage level VLref is greater than the voltage level V(1), and the IC substrate 710[1] corresponding to the comparator 716[1] is in an unselectable state. The control circuit 730 may set the state information ST[1] to indicate that the IC substrate 710[1] is in a selectable state, and set the identifier ID[1] to data ID1 (e.g., data ID0 plus a predetermined value or a predetermined address offset).

[0079] After determining the identifier ID[1], the control circuit 730 may set the voltage level VLref of the reference voltage Vref to be between V(2) and V(3), and apply the reference voltage Vref to the second input terminal of each comparator. Similarly, the comparator 716[i] (i=0, 1, ..., N) is used to compare the voltage level V(i) with the voltage level VLref. When the comparison result of the comparator indicates that the voltage level VLref is greater than the voltage level V(2), and the IC substrate corresponding to the comparator is in an unselectable state, the control circuit 730 may set the IC substrate to a selectable state and assign data ID2 to the identifier of the IC substrate.

[0080] For example, the comparison result of the comparator 716[2] may indicate that the voltage level VLref is greater than the voltage level V(2), and the IC substrate 710[2] corresponding to the comparator 716[2] is in an unselectable state. The control circuit 730 is configured to set the state information ST[2] to a selectable state and set the identifier ID[2] to data ID2 (e.g., data ID1 plus a predetermined value or a predetermined address offset).

[0081] After the identifiers ID[0]-ID[N] are stored in the IC substrates 710[0]-710[N] respectively, the control circuit 730 can select the IC substrates 710[0]-710[N] individually according to the identifiers ID[0]-ID[N].

[0082] Figure 8 According to some embodiments of the present application Figure 7 The schematic diagram of an implementation of the identification circuit 712[i] (i=0, 1, ..., N) shown in FIG. The identification circuit 712[i] may include (but is not limited to) a storage device 814, a comparator 816, and a processing circuit 818. The storage device 814 is used to store Figure 7The state information ST[i] and identifier ID[i] of the IC substrate 710[i] shown. The storage device 814 can be implemented by a volatile or non-volatile storage device. The comparator 816 is used to compare the reference voltage Vref (having a voltage level VLref) with the node voltage VN (having a voltage level V(i)) to generate a comparison result CR. The processing circuit 818 is coupled to the storage device 814 and the comparator 816. When the comparison result CR indicates that the voltage level VLref is greater than the voltage level V(i) and the state information ST[i] indicates an unselectable state, the processing circuit 818 is used to generate the identifier ID[i] with reference to the voltage level VLref, and update the state information ST[i] to a selectable state; when the comparison result CR indicates that the voltage level VLref is less than the voltage level V(i), or indicates that the state information ST[i] represents a selectable state, the processing circuit 818 does not change the identifier ID[i] and the state information ST[i].

[0083] Please include Figure 7 See also Figure 8 , to identify the circuit 712 [1] using Figure 8 Taking the illustrated structure (i.e., i=1) as an example, when the control circuit 730 is used to set the voltage level VLref of the reference voltage Vref to be between V(1) and V(2), the comparison result CR generated by the comparator 816 indicates that the voltage level VLref is greater than the voltage level V(1). The processing circuit 818 reads the state information ST[1] from the storage device 814, which indicates a non-selectable state. The processing circuit 818 can generate an identifier ID[1] based on the voltage level VLref, and update the state information ST[1] to indicate a selectable state. Please note that when the control circuit 730 is used to set the voltage level VLref of the reference voltage Vref to be between V(2) and V(3), the comparison result CR generated by the identification circuit 712[1] indicates that the voltage level VLref is greater than the voltage level V(1). Since the state information ST[1] read from the storage device 814 indicates a selectable state, the processing circuit 818 does not change the identifier ID[1] and the state information ST[1].

[0084] Since those skilled in the art should be aware of Figure 8 The architecture shown can be applied to Figure 7 Each identification circuit is shown, therefore, similar descriptions are not repeated here.

[0085] Fig. 9 According to some embodiments of the present application Figure 1 FIG. 1 is a schematic diagram of another embodiment of a semiconductor package 100 shown in FIG. 1 . Except that the IC substrates stacked on each other in the semiconductor package 900 are implemented as the same layer, the structure of the semiconductor package 900 is similar to that of FIG. Figure 7 The structure of the semiconductor package 700 shown in FIG. 7 is substantially the same. In this embodiment, the semiconductor package 900 includes Figure 7 IC substrates 710 [ 1 ] - 710 [N] and conductive structures 720 are shown.

[0086] During operation, the control circuit 730 may first reset the IC substrates 710[2]-710[N] to an unselectable state, and set the identifier ID[1] of the IC substrate 710[1] to data ID1, so that the IC substrate 710[1] is in a selectable state.

[0087] For example, the control circuit 730 may set the state information ST[2]-ST[N] to indicate that the IC substrates 710[2]-710[N] are in an unselectable state. In addition, the control circuit 730 may assign an address signal indicating data ID1 to the identification circuit 712[1] to set the identifier ID[1] to data ID1 and set the state information ST[1] to indicate that the IC substrate 710[1] is in an selectable state.

[0088] Next, the control circuit 730 may apply the predetermined voltage Vsrc to the voltage divider 724. In the case where the predetermined voltage Vss is the ground voltage, the voltage level V(i) of the node N[i] in the IC substrate 710[i] (i=1, 2, ..., N) is equal to (or substantially equal to) VLsrc×((i-1) / (N-1)), where VLsrc represents the voltage level of the predetermined voltage Vsrc.

[0089] For example, the control circuit 730 may apply a predetermined voltage Vsrc to one end of the conductive path 722 located at the substrate 710[N], while the other end of the conductive path 722 located at the substrate 710[1] is coupled to the ground voltage. The voltage level of the first input terminal (coupled to the node N[i]) of the comparator 716[i] is equal to (or substantially equal to) VLsrc×((i-1) / (N-1)).

[0090] In addition, the control circuit 730 may set the voltage level VLref of the reference voltage Vref to be between V(2) and V(3), and apply the reference voltage Vref to the second input terminal of each comparator. The comparator 716[i] (i=1, 2, ..., N) is used to compare the voltage level V(i) with the voltage level VLref. When the comparison result of the comparator indicates that the voltage level VLref is greater than the voltage level V(2), and the IC substrate corresponding to the comparator is in an unselectable state, the control circuit 730 may set the IC substrate to a selectable state and assign data ID2 to the identifier of the IC substrate.

[0091] For example, the comparison result of the comparator 716[2] may indicate that the voltage level VLref is greater than the voltage level V(2), and the IC substrate 710[2] corresponding to the comparator 716[2] is in an unselectable state. The control circuit 730 may set the state information ST[2] to indicate that the IC substrate 710[2] is in a selectable state, and set the identifier ID[2] to data ID2 (e.g., data ID1 plus a predetermined value or a predetermined address offset).

[0092] Since the technicians in this field read Figures 1 to 8 After reading the relevant paragraphs, you should be able to understand Fig. 9 The operation details of the semiconductor package 900 are shown, and therefore, further description is not repeated here.

[0093] In some embodiments, the comparator of the first IC substrate to be assigned an identifier may be omitted. Fig.10 According to some embodiments of the present application Figure 1 FIG. 1 is a schematic diagram of another embodiment of a semiconductor package 100. In addition to the identification circuit 1012[0], the structure of the semiconductor package 1000 is similar to Figure 7 The structures of the semiconductor packages 1000 shown are substantially the same.

[0094] In this embodiment, the semiconductor package 1000 includes Figure 7 The IC substrates 710[1]-710[N] and the conductive structure 720 are shown. Except for omitting the comparator, the circuit structure of the identification circuit 1012[0] is the same as Figure 7 The identification circuit 712[0] shown is substantially the same. In operation, the control circuit 730 may first reset the IC substrates 710[1]-710[N] to an unselectable state, and set the identifier ID[0] of the IC substrate 1010[0] to data ID0, so that the IC substrate 1010[0] is in a selectable state. Next, the control circuit 730 may apply a predetermined voltage Vsrc to the voltage divider 724 to generate identifiers for other IC substrates. As those skilled in the art will appreciate in reading Figures 1 to 9 After reading the relevant paragraphs of the description, the operation details of the semiconductor package 1000 should be understood, and therefore, further description is not repeated here.

[0095] Fig.11 is a flow chart of an exemplary method for identifying multiple IC substrates in a stacked structure according to certain embodiments of the present application. Figure 4The method 1100 is illustrated with reference to the semiconductor package 400 and the control circuit 430 shown. Please note that the method 1100 can be applied to other control circuits to identify stacked IC substrates without departing from the scope of the present application. In addition, in some embodiments, the method 1100 may include other steps. In some embodiments, the steps of the method 1100 may be implemented in different orders or implementations.

[0096] Please include Figure 4 See also Fig.11 In step 1102, when each IC substrate is in an unselectable state, a first identifier is assigned to the first IC substrate, thereby converting the first IC substrate from an unselectable state to an selectable state. For example, the control circuit 430 may convert the IC substrate 410[0] from an unselectable state to an selectable state by assigning the identifier ID[0] to the IC substrate 410[0].

[0097] In step 1104, an input signal is applied to a conductive structure that passes through the plurality of IC substrates in the stacked structure. For example, the control circuit 430 may apply the input signal S IN Applied to conductive structure 420 shared by IC substrates 410 [ 0 ] - 410 [N].

[0098] In step 1106, the control circuit 430 generates a second identifier by referring to the input signal to identify the second IC substrate. The second IC substrate is adjacent to the first IC substrate. For example, the control circuit 430 can generate a second identifier by referring to the input signal S IN An identifier ID[1] is generated to identify the IC substrate 410[1] (which is in an unselectable state or has not yet been identified).

[0099] In some embodiments, when the input signal S IN When the address corresponding to the identifier ID[0] is indicated, the control circuit can IN IC substrate 410[0] is selected so that IC substrate 410[1] transmits stimulus signal SS[0] to IC substrate 410[1] via wireless coupling (such as inductive or capacitive coupling). IC substrate 410[1] may be enabled to receive stimulus signal SS[0] to generate identifier ID[1].

[0100] Please note that the method 1100 can be applied to chip / wafer identification schemes using voltage distribution. Figure 7In the illustrated embodiment, the control circuit 730 may convert the IC substrate 710[0] from an unselectable state to a selectable state (step 1102), apply a reference voltage Vref to the conductive structure 720 (step 1104), and identify the IC substrate 710[1] by generating an identifier ID[1] with reference to the reference voltage Vref (step 1106).

[0101] In some embodiments, the method 1100 may be applied to wafer level testing. Figure 3C In the illustrated embodiment, the test system 302 may be used Fig.11 The method 1100 shown in FIG. 1 records the IC substrates 110 [0] - 110 [P] with identifiers ID [0] - ID [P]. The test system 302 can store the identifiers ID [0] - ID [P], which can be loaded at the next system power-up. Figures 1 to 10 After reading the relevant paragraphs of the description, the operational details of method 1100 should be understood, so further description will not be repeated here.

[0102] Through the identification scheme disclosed in the present application, each layer in the chip / wafer stack can be assigned a corresponding unique identifier based on the physical spatial relationship between the stacked layers. The identification scheme disclosed in the present application can individually identify the stacked layers based on the corresponding identifiers, thereby ensuring that the system functions can be executed correctly and achieving accurate testing and failure analysis.

[0103] The above description briefly presents the features of certain embodiments of the present application, so that those skilled in the art can more fully understand the various aspects of the present application. Those skilled in the art will understand that they can easily use the content of the present application as a basis to design or modify other processes and structures to achieve the same purpose and / or achieve the same advantages as the embodiments described herein. Those skilled in the art should understand that these equivalent embodiments still belong to the spirit and scope of the present application, and they can be variously changed, replaced and modified without departing from the spirit and scope of the present application.

Claims

1. A semiconductor package, comprising: a plurality of integrated circuit substrates stacked one on top of the other; as well as A conductive structure passes through the plurality of integrated circuit substrates, wherein each integrated circuit substrate includes an identification circuit coupled to the conductive structure, and each identification circuit is used to identify the corresponding integrated circuit substrate by receiving an input signal from the conductive structure and generating an identifier of the corresponding integrated circuit substrate accordingly. 2 . The semiconductor package according to claim 1 , wherein the identification circuits of the plurality of integrated circuit substrates generate respective identifiers in sequence according to the spatial arrangement order of the plurality of integrated circuit substrates.

3. The semiconductor package according to claim 1, wherein the plurality of integrated circuit substrates comprises: a first integrated circuit substrate, wherein when the input signal indicates an address corresponding to the identifier of the first integrated circuit substrate, the identification circuit of the first integrated circuit substrate is used to send an excitation signal when receiving the input signal; as well as The second integrated circuit substrate is adjacent to the first integrated circuit substrate, and the identification circuit of the second integrated circuit substrate is used to receive the excitation signal and generate an identifier of the second integrated circuit substrate.

4. The semiconductor package according to claim 3, wherein the identification circuit of the first integrated circuit substrate includes a first coupling circuit, and the identification circuit of the second integrated circuit substrate includes a second coupling circuit; and the excitation signal is sent from the first integrated circuit substrate to the second integrated circuit substrate through wireless coupling between the first coupling circuit and the second coupling circuit. 5 . The semiconductor package according to claim 4 , wherein the first coupling circuit and the second coupling circuit are both inductive coupling circuits or capacitive coupling circuits.

6. The semiconductor package according to claim 3, wherein the identification circuit of the first integrated circuit substrate comprises: a storage device for storing an identifier of the first integrated circuit substrate; A coupling circuit, used for generating the excitation signal according to the driving signal; as well as The processing circuit is coupled to the storage device and the coupling circuit, and is used to generate the driving signal by determining whether the input signal indicates an address corresponding to the identifier of the first integrated circuit substrate.

7. The semiconductor package according to claim 3, wherein the identification circuit of the second integrated circuit substrate is used to generate an identifier of the second integrated circuit substrate in response to the excitation signal when the second integrated circuit substrate has not been identified; when the second integrated circuit substrate has been identified, the identifier of the second integrated circuit substrate will not be modified by the excitation signal.

8. The semiconductor package according to claim 3, wherein the identification circuit of the second integrated circuit substrate comprises: 。 a storage device for storing status information indicating whether the second integrated circuit substrate has been identified; A coupling circuit, used for generating an induction signal according to the excitation signal; as well as The processing circuit is coupled to the storage device and the coupling circuit, wherein when the status information indicates that the second integrated circuit substrate has not been identified, the processing circuit is used to receive the sensing signal and generate an identifier of the second integrated circuit substrate with reference to the input signal.

9. The semiconductor package according to claim 1, wherein the conductive structure comprises: a first conductive path passing through the plurality of integrated circuit substrates, wherein the input signal is a reference voltage applied to the first conductive path; as well as a second conductive path passing through the plurality of integrated circuit substrates, wherein two ends of the second conductive path are respectively connected to different potentials to form a voltage divider having a plurality of nodes, and a section between two adjacent nodes on the second conductive path serves as a resistive element of the voltage divider; The plurality of identification circuits included in the plurality of integrated circuit substrates are respectively coupled to the plurality of nodes; each identification circuit is used to determine an identifier of the corresponding integrated circuit substrate by comparing the reference voltage with a node voltage of a corresponding node.

10. The semiconductor package according to claim 9, wherein each identification circuit comprises: a comparator, used to compare the reference voltage with the node voltage to generate a comparison result; as well as The processing circuit is coupled to the comparator and is used to generate an identifier of the corresponding integrated circuit substrate according to the comparison result.

11. The semiconductor package according to claim 1, wherein the plurality of integrated circuit substrates comprises: a first integrated circuit substrate; as well as A plurality of second integrated circuit substrates identical to each other, each second integrated circuit substrate being different from the first integrated circuit substrate, wherein the identification circuit of the first integrated circuit substrate is used to identify the identifier of the first integrated circuit substrate before any second integrated circuit substrate is identified.

12. The semiconductor package according to claim 1, further comprising: The control circuit is coupled to the conductive structure and is used to send the input signal to the conductive structure, wherein the control circuit is located in one of the plurality of integrated circuit substrates or outside the plurality of integrated circuit substrates.

13. The semiconductor package according to claim 1, wherein each integrated circuit substrate is a dynamic random access memory. The semiconductor package according to claim 1 , wherein the plurality of integrated circuit substrates are identical to one another. 15 . The semiconductor package according to claim 1 , wherein at least one integrated circuit substrate among the plurality of integrated circuit substrates is different from the other integrated circuit substrates.

16. A method for identifying a plurality of integrated circuit substrates in a stacked structure, comprising: When each integrated circuit substrate is in an unselectable state, assigning a first identifier to a first integrated circuit substrate among the plurality of integrated circuit substrates to convert the first integrated circuit substrate from an unselectable state to a selectable state; applying an input signal to a conductive structure that passes through the plurality of integrated circuit substrates in the stacked structure; as well as A second integrated circuit substrate among the plurality of integrated circuit substrates is identified by referring to the input signal and generating a second identifier, wherein the second integrated circuit substrate is adjacent to the first integrated circuit substrate.

17. The method according to claim 16, wherein the input signal indicates an address corresponding to the first identifier; and the step of identifying the second integrated circuit substrate by referring to the input signal and generating the second identifier comprises: Selecting the first integrated circuit substrate according to the input signal, so that the first integrated circuit substrate sends an excitation signal to the second integrated circuit substrate through wireless coupling; as well as The second integrated circuit substrate is caused to receive the excitation signal to generate the second identifier.

18. The method of claim 17, wherein the wireless coupling is an inductive coupling or a capacitive coupling.

19. The method according to claim 16, wherein the input signal is a reference voltage applied to a first conductive path in the conductive structure; two ends of a second conductive path in the conductive structure are respectively connected to different potentials to form a voltage divider having a plurality of nodes, and a section between two adjacent nodes on the second conductive path serves as a resistive element of the voltage divider; the step of identifying the second integrated circuit substrate by referring to the input signal and generating the second identifier comprises: The second integrated circuit substrate is caused to compare the reference voltage with a node voltage of a corresponding node in the second integrated circuit substrate, thereby generating the second identifier.

20. The method of claim 16, further comprising: When the second identifier of the second integrated circuit substrate is generated, the second integrated circuit substrate is set to a selectable state.

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