Trench gate SiC MOSFET chip and manufacturing method thereof

Abstract

The invention discloses a trench gate SiC MOSFET chip and a manufacturing method thereof.The trench gate SiC MOSFET chip uses a composite trench gate structure, the thicknesses of gate oxide layers at the bottom and the side wall of a trench can be controlled respectively, the gate oxide layer at the bottom of the trench at the position where the electric field intensity is large is thickened, and therefore the long-term reliability of a device in the using process is improved, and the reliability of the device is improved. And a thin gate oxide layer is reserved on the side wall groove part, so that the channel resistance and the conduction loss of the device can be reduced. Therefore, the channel resistance and the conduction loss can be effectively reduced while the high reliability of the device is ensured.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and more specifically, to a trench gate SiC MOSFET chip and a manufacturing method thereof. Background Art

[0002] As a third-generation semiconductor material, SiC (silicon carbide, a semiconductor material that can be used to make semiconductor devices and integrated circuits) has the characteristics of large bandgap width, high breakdown field strength, high saturated electron drift rate, high thermal conductivity, and stable chemical properties. This makes SiC-based power devices have great application prospects in high voltage, high temperature, high frequency, high power, and strong radiation, and is particularly suitable for the production of high-voltage and high-power power electronic devices.

[0003] SiC MOSFET (metal oxide field effect transistor) devices have the advantages of fast switching speed, simple control (voltage controlled), and low on-resistance. They are widely used in application fields that require high-power devices, such as wind power generation, solar power generation, smart grid, rail transportation, and military industry.

[0004] Compared with the planar gate SiC MOSFET device structure, the trench gate SiC MOSFET has a smaller cell size and higher integration density. At the same time, since the influence of the JFET region resistance effect in the on state is eliminated, the on resistance can be further reduced and the current density can be increased. It has greater development potential in the context of the development trend of power electronic devices towards miniaturization and high-density integration. However, the structural evolution from planar gate to trench gate will also introduce new problems. For example, when the position of the gate oxide layer is transferred from the chip surface to the groove surface inside the chip, the electric field strength inside the chip in the device blocking state is much higher than that of traditional silicon-based devices, and from the perspective of materials, the maximum electric field strength that the gate oxide layer can withstand is lower than that of SiC in the chip body region. This will make the gate oxide region at the bottom of the trench without the protection of the Pwell depletion layer easy to be broken down, thereby affecting the long-term reliability of the device during use. One possible solution is to increase the thickness of the gate oxide layer to improve the reliability of the gate oxide, but this will also increase the channel resistance and increase the conduction loss. Another possible solution is to add a deeper Pwell injection on one side of the strip trench, so that when the device is in the blocking state, the depletion layer expansion of the Pwell can completely protect the bottom of the channel, but at the same time, when the device is in the on state, half of the conductive channel area is lost, which is not conducive to reducing the on-resistance of the device. Summary of the invention

[0005] The object of the present invention is to provide a trench gate SiC MOSFET chip and a manufacturing method thereof, which can effectively reduce the channel resistance and conduction loss while ensuring the high reliability of the device.

[0006] A trench gate SiC MOSFET chip, wherein a cell region comprises a trench, a first polysilicon gate, a second polysilicon gate, a first gate oxide layer and a second gate oxide layer, and a transition region comprises a gate metal, a source metal and a plurality of contact holes; wherein the first polysilicon gate is located at the bottom of the trench, the first gate oxide layer is located at the outer surface of the first polysilicon gate, the second polysilicon gate is located at the upper part of the trench, the second gate oxide layer is located at the outer surface of the second polysilicon gate, the thickness of the first gate oxide layer is greater than the thickness of the second gate oxide layer, the first polysilicon gate is connected to the source metal through corresponding contact holes in the transition region, and the second polysilicon gate is connected to the gate metal through corresponding contact holes in the transition region.

[0007] In one embodiment, the cell region also includes an N+ doped region, a P+ contact region and a substrate, and the transition region also includes a drain metal; wherein the number of N+ doped regions and the number of grooves are both two, the two N+ doped regions are located between the two grooves, and are respectively in contact with the two first gate oxide layers, the P+ contact region is sandwiched between the two N+ doped regions and is respectively in contact with the two N+ doped regions, the substrate is located on the back side of the chip, the N+ doped region and the P+ contact region are connected to the source metal in the transition region, and the substrate is connected to the drain metal in the transition region.

[0008] In one of the embodiments, the cell region also includes a back metal, a buffer layer, an epitaxial layer, a SiO2 dielectric layer, a front metal and a PI glue passivation layer; wherein the back metal, the substrate, the buffer layer, the epitaxial layer, the SiO2 dielectric layer, the front metal and the PI glue passivation layer are stacked in sequence from bottom to top, the first polysilicon gate, the second polysilicon gate, the first gate oxide layer, the second gate oxide layer, the N+ doped region and the P+ contact region are all located in the epitaxial layer, the front metal is in contact with the SiO2 dielectric layer, the N+ doped region and the P+ contact region at the same time, and the PI glue passivation layer is in contact with the front metal and the SiO2 dielectric layer respectively.

[0009] In one embodiment, the cell region further includes a Pwell layer, which is located in the epitaxial layer and is in contact with the second gate oxide layer, the N+ doped region and the P+ contact region.

[0010] A method for manufacturing a trench gate SiC MOSFET chip, used to manufacture the above chip, the method comprising: A substrate is provided, and a buffer layer and an epitaxial layer are grown upward in sequence on the substrate; Pwell ions, Source ions and Pplus ions are sequentially implanted into the epitaxial layer to form corresponding Pwell layers, N+ doped regions and P+ contact regions respectively; Depositing and growing a SiO2 etching hard mask layer on the upper surface of the epitaxial layer, etching a groove on the SiO2 etching hard mask layer, growing a sacrificial oxide layer on the inner surface of the groove, removing the sacrificial oxide layer and growing a first gate oxide layer on the inner surface of the groove, growing polysilicon deposition in the first gate oxide layer and etching the polysilicon on the entire surface to obtain a first polysilicon gate; Wet etching the first gate oxide layer located on the inner surface of the upper portion of the trench, growing a second gate oxide layer on the inner surface of the upper portion of the trench, growing polysilicon deposits in the first gate oxide layer and etching the polysilicon on the entire surface to obtain a second polysilicon gate; Photolithography defines the dummy gate contact hole area, removes the upper polysilicon in the trench by etching, and deposits and grows a SiO2 dielectric layer on the upper surface of the epitaxial layer, densifies the SiO2 dielectric layer, and etches the SiO2 dielectric layer to form a source contact hole and a gate contact hole including a dummy gate and a real gate; Metal nickel is sputtered on the upper surface of part of the SiO2 dielectric layer and part of the epitaxial layer, and ohmic contact is formed by thermal annealing. Unreacted metal nickel is wet-etched, and metal aluminum is continuously sputtered and wet-etched for patterning to obtain a front metal layer, and PI glue is covered on part of the front metal layer and part of the SiO2 dielectric layer to form a PI glue passivation layer, and the PI glue passivation layer is photoetched; The lower surface of the substrate is ground to remove silicon oxide, and metal nickel is sputtered, and thermal annealing is performed to form an ohmic contact, and metal titanium, nickel or silver is continuously sputtered to obtain a back metal layer.

[0011] A trench gate SiC MOSFET chip, wherein a cell region comprises a first trench, a second trench, a first polysilicon gate, a second polysilicon gate, a first gate oxide layer and a second gate oxide layer, and a transition region comprises a gate metal, a source metal and a plurality of contact holes; wherein the first polysilicon gate is located in the first trench, the first gate oxide layer is located on the outer surface of the first polysilicon gate, the second polysilicon gate is located in the second trench, the second gate oxide layer is located on the outer surface of the second polysilicon gate, the number of the second trenches is two and they are located on both sides of the first trench respectively, the thickness of the first gate oxide layer is greater than the thickness of the second gate oxide layer, the depth of the first trench is greater than the depth of the second trench, the first polysilicon gate is connected to the source metal through corresponding contact holes in the transition region, and the second polysilicon gate is connected to the gate metal through corresponding contact holes in the transition region.

[0012] In one embodiment, the cell region also includes an N+ doped region, a P+ contact region and a substrate, and the transition region also includes a drain metal; wherein, the number of the N+ doped region and the P+ contact region are both two, the two N+ doped regions are respectively located on the outer sides of the two second trenches relative to the first trench, the two P+ contact regions are respectively located on the outer sides of the two N+ doped regions relative to the second trench, the substrate is located on the back side of the chip, the N+ doped region and the P+ contact region are connected to the source metal in the transition region, and the substrate is connected to the drain metal in the transition region.

[0013] In one of the embodiments, the cell region also includes back metal, buffer layer, epitaxial layer, SiO2 dielectric layer, front metal and PI glue passivation layer; wherein, the back metal, substrate, buffer layer, epitaxial layer, SiO2 dielectric layer, front metal and PI glue passivation layer are stacked in sequence from bottom to top, the first groove, the second groove, the first polysilicon gate, the second polysilicon gate, the first gate oxide layer, the second gate oxide layer, the N+ doped region and the P+ contact region are all located in the epitaxial layer, the front metal is in contact with the SiO2 dielectric layer, the N+ doped region and the P+ contact region at the same time, and the PI glue passivation layer is in contact with the front metal and the SiO2 dielectric layer respectively.

[0014] In one embodiment, the cell region further includes a Pwell layer, which is located in the epitaxial layer and is in contact with the second gate oxide layer, the N+ doped region and the P+ contact region.

[0015] A method for manufacturing a trench gate SiC MOSFET chip, used to manufacture the above chip, the manufacturing method comprising: A substrate is provided, and a buffer layer and an epitaxial layer are grown upward in sequence on the substrate; Pwell ions, Source ions and Pplus ions are sequentially implanted into the epitaxial layer to form corresponding Pwell layers, N+ doped regions and P+ contact regions respectively; Depositing and growing a SiO2 etching hard mask layer on the upper surface of the epitaxial layer, etching a first trench on the SiO2 etching hard mask layer, growing a first sacrificial oxide layer on the inner surface of the first trench, removing the first sacrificial oxide layer and growing a first gate oxide layer on the inner surface of the first trench, growing polysilicon deposition in the first gate oxide layer and etching the polysilicon on the entire surface to obtain a first polysilicon gate; Etching a second trench on the SiO2 etching hard mask layer, growing a second sacrificial oxide layer on the inner surface of the second trench, removing the second sacrificial oxide layer and growing a second gate oxide layer on the inner surface of the second trench, growing polysilicon deposits in the second gate oxide layer and etching the polysilicon on the entire surface to obtain a second polysilicon gate; A SiO2 dielectric layer is deposited and grown on the upper surface of the epitaxial layer, the SiO2 dielectric layer is densified, and the SiO2 dielectric layer is etched to form a source contact hole and a gate contact hole including a dummy gate and a real gate; Metal nickel is sputtered on the upper surface of part of the SiO2 dielectric layer and part of the epitaxial layer, and ohmic contact is formed by thermal annealing. Unreacted metal nickel is wet-etched, and metal aluminum is continuously sputtered and wet-etched for patterning to obtain a front metal layer, and PI glue is covered on part of the front metal layer and part of the SiO2 dielectric layer to form a PI glue passivation layer, and the PI glue passivation layer is photoetched; The lower surface of the substrate is ground to remove silicon oxide, metal nickel is sputtered, and thermal annealing is performed to form an ohmic contact, and metal titanium, nickel or silver is continuously sputtered to obtain a back metal layer.

[0016] The present invention is provided with a protocol interface module, a mapping module and an audio module. After the protocol interface module receives an access request through its own interface, it parses the access request according to the interface protocol corresponding to its own interface to obtain a corresponding protocol address. The mapping module maps the protocol address obtained by parsing the protocol interface module to an access address with a unified coding standard, and transmits the mapped access address to the audio module corresponding to the access address; the audio module that receives the access address provides a corresponding access function. It can be seen that in the present invention, each interface protocol module only needs to be responsible for the protocol parsing of the interface, and then the mapping module realizes access to the corresponding audio module through the mapping between addresses, without setting corresponding registers for each interface protocol, thereby effectively reducing the area overhead of the audio codec chip and greatly saving costs.

[0017] The trench gate SiC MOSFET chip provided by the present invention uses a composite trench gate structure, the thickness of the gate oxide layer at the bottom and sidewall of the trench can be controlled separately, the gate oxide layer at the bottom of the trench where the electric field strength is greater is thickened, thereby improving the long-term reliability of the device during use, and the sidewall trench portion retains a thinner gate oxide layer, which helps to reduce the channel resistance and conduction loss of the device. It can be seen that the present invention can effectively reduce the channel resistance and conduction loss while ensuring that the device has high reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings in the following description are only embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.

[0019] Figure 1 A schematic diagram of a first structure of a trench gate SiC MOSFET chip provided in Embodiment 1 of the present invention; Figure 2 A second structural schematic diagram of a trench gate SiC MOSFET chip provided in Embodiment 1 of the present invention; Figure 3 A flowchart of a method for manufacturing a trench gate SiC MOSFET chip provided in Embodiment 1 of the present invention; Figure 4 A schematic diagram of a first structure of a trench gate SiC MOSFET chip provided in Embodiment 2 of the present invention; Figure 5 A second structural schematic diagram of a trench gate SiC MOSFET chip provided in Embodiment 2 of the present invention; Figure 6 A flowchart of a method for manufacturing a trench gate SiC MOSFET chip provided in Embodiment 2 of the present invention; Among them, PI represents PI glue passivation layer, M1 represents back metal layer, M2 represents front metal layer, M3 represents gate metal, M4 represents source metal, Si represents SiO2 dielectric layer, N represents N+ doping region, P represents P+ contact region, L represents Pwell layer, P1 represents first polysilicon gate, P2 represents second polysilicon gate, S1 represents first gate oxide layer, S2 represents second gate oxide layer, E represents epitaxial layer, B represents Buffer layer, S represents substrate, and H represents contact hole. DETAILED DESCRIPTION

[0020] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0021] A trench gate SiC MOSFET chip and a method for manufacturing the same provided by the embodiment of the present invention can be found in Figures 1 to 6 , wherein PI represents a PI glue passivation layer, M1 represents a back metal layer, M2 represents a front metal layer, M3 represents a gate metal, M4 represents a source metal, Si represents a SiO2 dielectric layer, N represents an N+ doping region, P represents a P+ contact region, L represents a Pwell layer, P1 represents a first polysilicon gate, P2 represents a second polysilicon gate, S1 represents a first gate oxide layer, S2 represents a second gate oxide layer, E represents an epitaxial layer, B represents a buffer layer, S represents a substrate, and H represents a contact hole. The technical solution provided in the embodiment of the present invention is described in detail below.

[0022] See also Figure 1, which shows a schematic structural diagram of a trench gate SiC MOSFET chip provided in Embodiment 1 of the present invention, wherein the cell region includes a trench, a first polysilicon gate, a second polysilicon gate, a first gate oxide layer and a second gate oxide layer, and the transition region includes a gate metal, a source metal and a plurality of contact holes; wherein the first polysilicon gate is located at the bottom of the trench, the first gate oxide layer is located at the outer surface of the first polysilicon gate, the second polysilicon gate is located at the upper part of the trench, the second gate oxide layer is located at the outer surface of the second polysilicon gate, the thickness of the first gate oxide layer is greater than the thickness of the second gate oxide layer, the first polysilicon gate is connected to the source metal through the corresponding contact hole in the transition region, and the second polysilicon gate is connected to the gate metal through the corresponding contact hole in the transition region.

[0023] Embodiment 1 of the present invention provides a high-reliability trench gate SiC MOSFET chip, wherein a basic cell (cell region) comprises a trench, a first polysilicon gate, a second polysilicon gate, a first gate oxide layer and a second gate oxide layer, and a transition region comprises a gate metal, a source metal and a plurality of contact holes; wherein the first polysilicon gate and the first gate oxide layer are located at the bottom of the trench, the first gate oxide layer is between the first polysilicon gate and the inner surface of the trench, and covers the outer surface of the first polysilicon gate; the second polysilicon gate and the second gate oxide layer are located at the upper part of the trench, the second gate oxide layer is located between the second polysilicon gate and the inner surface of the trench, and between the first gate oxide layer and the second polysilicon gate, and covers the outer surface of the second polysilicon gate, the thickness of the first gate oxide layer is greater than the thickness of the second gate oxide layer, the first polysilicon gate is connected to the source metal through a contact hole in the chip transition region, and the second polysilicon gate is connected to the gate metal through another contact hole in the chip transition region. Therefore, when the device is in a blocking state, the first gate oxide layer at the bottom of the trench will be subjected to a larger electric field strength. A larger first gate oxide layer thickness can improve the long-term reliability of the device during use. At the same time, the capacitance of this part of the gate oxide layer is not included in the Miller capacitance, which can reduce the Miller capacitance of the device, increase the switching speed, and reduce the overall loss of the device. When the device is in the on state, the second gate oxide layer on the upper sidewall of the trench has a thinner thickness, which can reduce the channel resistance and conduction loss of the device.

[0024] The trench gate SiC MOSFET chip provided by the present invention uses a composite trench gate structure, the thickness of the gate oxide layer at the bottom and sidewall of the trench can be controlled separately, the gate oxide layer at the bottom of the trench where the electric field strength is greater is thickened, thereby improving the long-term reliability of the device during use, and the sidewall trench portion retains a thinner gate oxide layer, which helps to reduce the channel resistance and conduction loss of the device. It can be seen that the present invention can effectively reduce the channel resistance and conduction loss while ensuring that the device has high reliability.

[0025] In a trench gate SiC MOSFET chip provided in Embodiment 1 of the present invention, the cell region further includes an N+ doped region, a P+ contact region and a substrate, and the transition region further includes a drain metal; wherein the number of N+ doped regions and trenches is two, the two N+ doped regions are located between the two trenches, and are respectively in contact with the two first gate oxide layers, the P+ contact region is sandwiched between the two N+ doped regions and is respectively in contact with the two N+ doped regions, the substrate is located on the back side of the chip, the N+ doped region and the P+ contact region are connected to the source metal in the transition region, and the substrate is connected to the drain metal in the transition region.

[0026] The cell area also includes back metal, buffer layer, epitaxial layer, SiO2 dielectric layer, front metal and PI glue passivation layer; wherein, the back metal, substrate, buffer layer, epitaxial layer, SiO2 dielectric layer, front metal and PI glue passivation layer are stacked in sequence from bottom to top, the first polysilicon gate, the second polysilicon gate, the first gate oxide layer, the second gate oxide layer, the N+ doped region and the P+ contact region are all located in the epitaxial layer, the front metal is in contact with the SiO2 dielectric layer, the N+ doped region and the P+ contact region at the same time, and the PI glue passivation layer is in contact with the front metal and the SiO2 dielectric layer respectively.

[0027] The cell region further includes a Pwell layer, which is located in the epitaxial layer and is in contact with the second gate oxide layer, the N+ doped region and the P+ contact region.

[0028] It should be noted that in the first embodiment of the present invention, two or more trenches can be arranged in parallel. Accordingly, in the transition region of the chip, the first polysilicon gate and the second polysilicon gate can be connected to the gate metal and the source metal by means of two or more trenches in parallel. Therefore, there is no need to excessively reduce the size of the contact hole. When the size of the cell area is reduced, the size of the contact hole will not be restricted by the lithography process capability, thereby improving the process compatibility in the chip manufacturing process.

[0029] In a specific implementation of the first embodiment of the present invention, the number of trenches is 2 for specific description. The structure of the basic cell of the chip may include a substrate, a buffer layer, an epitaxial layer, a Pwell layer, an N+ doping region, a P+ contact region, a first polysilicon gate, a first gate oxide layer, a second polysilicon gate, a second gate oxide layer, a SiO2 dielectric layer, a front metal, a PI glue passivation layer, a trench, and a back metal. The transition region includes a gate metal, a drain metal, a source metal, and a plurality of contact holes. Figure 2 shown.

[0030] The number of N+ doping regions is 2, which are both located between two parallel trenches, and are in contact with two second gate oxide layers one by one, and the depth of the N+ doping region is less than the depth of the second gate oxide layer, and the depths of the two N+ doping regions can be the same; the P+ contact region is located between the two N+ doping regions, and is in contact with the two N+ doping regions, and the depth can be the same as the depth of the N+ doping region; the N+ doping region and the P+ contact region are connected to the source metal in the transition region. The Pwell layer can include three sub-regions, two of which are located on the outsides of the two trenches relative to the N+ doping region, and are in contact with the two second gate oxide layers respectively; another sub-region is located between the two trenches, and is in contact with the N+ doping region, the P+ contact region and the two second gate oxide layers respectively; and the depths of the three sub-regions are greater than the depth of the N+ doping region, and are not greater than the depth of the second gate oxide layer.

[0031] The back metal, substrate, buffer layer, epitaxial layer, SiO2 dielectric layer, front metal and PI glue passivation layer of the chip are stacked in order from bottom to top (from back to front). The first polysilicon gate, the second polysilicon gate, the first gate oxide layer, the second gate oxide layer, the N+ doped area, the P+ contact area and the Pwell layer are all located in the epitaxial layer. The Pwell layer does not extend to the side boundary of the epitaxial layer; the SiO2 dielectric layer is located on the epitaxial layer and is divided into two sub-areas. One sub-area covers from one side boundary of the epitaxial layer to the N+ contact area on that side. The upper surface of the doped area is covered by another sub-area from the other side boundary of the epitaxial layer to the upper surface of the N+ doped area on this side; the front metal layer is located on the SiO2 dielectric layer, does not extend to the side boundary of the epitaxial layer, and fills the gap between the two sub-areas of the SiO2 dielectric layer to contact the upper surface of the P+ contact area and the upper surface of the N+ doped area; the PI glue passivation layer is located on the front metal layer, and fills the gap between the side boundary of the front metal layer and the side boundary of the SiO2 dielectric layer to contact the upper surface of the SiO2 dielectric layer. The substrate on the back of the chip is connected to the drain metal. In the implementation method of the first embodiment of the present invention, in the middle connecting part of the two grooves, there is only a concave angle in the horizontal direction without a convex angle structure, thereby avoiding the electric field concentration effect at the convex angle position of the groove, and further improving the long-term reliability of the device during use.

[0032] The trench gate SiC MOSFET chip provided by the present invention uses a composite trench gate structure, the thickness of the gate oxide layer at the bottom and sidewall of the trench can be controlled separately, the gate oxide layer at the bottom of the trench where the electric field strength is greater is thickened, thereby improving the long-term reliability of the device during use, and the sidewall trench portion retains a thinner gate oxide layer, which helps to reduce the channel resistance and conduction loss of the device. At the same time, the composite trench gate structure can also reduce the Miller capacitance of the device, improve the switching speed, and reduce the overall loss.

[0033] The first embodiment of the present invention further provides a method for manufacturing a trench gate SiC MOSFET chip, which is used to manufacture the chip as in the first embodiment of the present invention. Figure 3 As shown, the specific production method includes: S11: a substrate is provided, and a buffer layer and an epitaxial layer are sequentially grown upward on the substrate; S12: Pwell ions, Source ions and Pplus ions are sequentially implanted into the epitaxial layer to form corresponding Pwell layers, N+ doped regions and P+ contact regions respectively; S13: depositing and growing a SiO2 etching hard mask layer on the upper surface of the epitaxial layer, etching a groove on the SiO2 etching hard mask layer, growing a sacrificial oxide layer on the inner surface of the groove, removing the sacrificial oxide layer and growing a first gate oxide layer on the inner surface of the groove, growing polysilicon deposition in the first gate oxide layer and etching the polysilicon on the entire surface to obtain a first polysilicon gate; S14: wet-etching a first gate oxide layer located on the inner surface of the upper portion of the trench, growing a second gate oxide layer on the inner surface of the upper portion of the trench, growing polysilicon deposition in the first gate oxide layer and etching the entire surface of the polysilicon to obtain a second polysilicon gate; S15: photolithography defines the dummy gate contact hole area, removes the upper polysilicon in the trench by etching, and deposits and grows a SiO2 dielectric layer on the upper surface of the epitaxial layer, densifies the SiO2 dielectric layer, and etches the SiO2 dielectric layer to form a source contact hole and a gate contact hole including a dummy gate and a real gate; S16: sputtering metal nickel on a portion of the SiO2 dielectric layer and a portion of the epitaxial layer, performing thermal annealing to form an ohmic contact, wet-etching the unreacted metal nickel, continuing to sputter metal aluminum and wet-etching for patterning to obtain a front metal layer, and covering a portion of the front metal layer and a portion of the SiO2 dielectric layer with PI glue to form a PI glue passivation layer, and performing photolithography on the PI glue passivation layer; S17: Grind the lower surface of the substrate to remove silicon oxide, sputter metal nickel, perform thermal annealing to form an ohmic contact, and continue to sputter metal titanium or nickel or silver to obtain a back metal layer.

[0034] In the manufacturing process of the trench gate SiC MOSFET chip provided in the first embodiment of the present invention, ion implantation, high temperature activation annealing of impurities, SiO2 wet etching, SiC trench dry etching, sacrificial oxide layer and gate oxide layer growth, polysilicon deposition and dry etching, wafer backside thinning, RTA metal alloy and other process steps are included. The specific manufacturing method can be as follows: 1) Use 4H-SiC single crystal substrate, the wafer size is 4-8 inches, the substrate thickness is 350-500um, the conductivity type is N-type, and the doping concentration is greater than 1E18cm-3; 2) CVD epitaxy is used to grow the buffer layer and epitaxial layer (both are mainly SiC) on the SiC substrate. The thickness of the buffer layer is 0.5-2um, the thickness of the epitaxial layer is 10-30um, the doping concentration of the buffer layer is 5E16-1E18cm-3, and the doping concentration of the epitaxial layer is 1E14-1E17cm-3. During the epitaxial process, the process chamber temperature is 1400℃-1800℃, and the surface of the wafer after epitaxial growth must be kept clean; 3) Implement Pwell ion implantation (Al+ ions) in the epitaxial layer to simultaneously form the Pwell layer (mainly PSiC) and the terminal field limiting ring in the cell area, with an implantation dose of 1E13-1E14 and an implantation energy of 200-800keV; 4) Implement Source ion implantation (N ions) in the epitaxial layer to form a Source region (i.e., N+ doped region, mainly NSiC), with an implantation dose of 5E14-5E15 and an implantation energy of 40-300keV; 5) Implement Pplus ion implantation (Al+ ions) in the epitaxial layer to form a P+ contact region (mainly P SiC), with an implantation dose of 5E14-5E15 and an implantation energy of 50-500keV; 6) The impurities are activated by furnace tube annealing. The process temperature of the furnace tube is above 1600℃, and the one-time activation rate of all impurities must be above 80%; 7) PECVD deposits and grows a SiO2 etching hard mask layer on the upper surface of the epitaxial layer with a thickness of 5000-10000A; 8) The upper surface of the epitaxial layer is grooved downward to a depth of 0.5-3um; 9) Grow a sacrificial oxide layer in the trench with a thickness of 800-1200A and remove the sacrificial oxide layer; 10) The first gate oxide layer (mainly SiO2) is grown in the trench, the process temperature of the furnace tube is above 1400°C, and the thickness of the gate oxide layer is 2000-5000A; 11) Polysilicon deposition growth (Dpoly, LPCVD process) is achieved at the bottom of the trench, with a thickness of 8000-10000A; 12) Etch the entire surface of polysilicon to a depth of 1-2um to obtain the first polysilicon gate (mainly Poly Si); 13) Wet etching of oxide layer at the top of the trench with a thickness of 2000-10000A; 14) A second gate oxide layer (mainly SiO2) is grown on the upper part of the trench. The process temperature of the furnace tube is above 1400°C, and the thickness of the gate oxide layer is 500-1500A; 15) Polysilicon deposition growth (Dpoly, LPCVD process) is achieved on the upper part of the trench, with a thickness of 8000-10000A; 16) Etch the entire surface of polysilicon to a depth of 0.5-1um to obtain a second polysilicon gate (mainly Poly Si); 17) Photolithography defines the pseudo gate contact hole area and etching removes the upper polysilicon in the trench; 18) A SiO2 dielectric layer is deposited and grown on the upper surface of the epitaxial layer using a PECVD process, and the dielectric layer thickness is 9000-12000A; 19) The furnace tube annealing process is used to densify the dielectric layer, and the furnace tube temperature is 600-800℃; 20) Etching in the SiO2 dielectric layer to form contact holes for the true gate, dummy gate and source; 21) Front sputtering of metal Ni, thickness 500-1000A; 22) RTA rapid thermal annealing treatment forms ohmic contact and wet etching of unreacted metal Ni; 23) Sputter metal Al on the front with a thickness of 4-8um, and pattern it by wet etching to obtain the front metal layer; 24) PI glue Coating forms a passivation protective layer (i.e. PI glue passivation layer, mainly PI), and performs photolithography with a thickness of 8-12um; 25) Grind the back of the wafer to remove silicon oxide and reduce the thickness to 120-250um; 26) Sputtering metal Ni on the back, thickness 500-1500A, RTA rapid thermal annealing treatment to form ohmic contact; 27) Sputter metal Ti / Ni / Ag on the back with a thickness of 1-2um to obtain a back metal layer.

[0035] See also Figure 4 , which shows a schematic structural diagram of a trench gate SiC MOSFET chip provided in Embodiment 2 of the present invention, wherein the cell region comprises a first trench, a second trench, a first polysilicon gate, a second polysilicon gate, a first gate oxide layer and a second gate oxide layer, and the transition region comprises a gate metal, a source metal and a plurality of contact holes; wherein, the first polysilicon gate is located in the first trench, the first gate oxide layer is located on the outer surface of the first polysilicon gate, the second polysilicon gate is located in the second trench, the second gate oxide layer is located on the outer surface of the second polysilicon gate, the number of the second trenches is two, and they are respectively located on both sides of the first trench, the thickness of the first gate oxide layer is greater than the thickness of the second gate oxide layer, the depth of the first trench is greater than the depth of the second trench, the first polysilicon gate is connected to the source metal through the corresponding contact hole in the transition region, and the second polysilicon gate is connected to the gate metal through the corresponding contact hole in the transition region.

[0036] Embodiment 2 of the present invention provides a trench gate SiC MOSFET chip with high reliability, wherein a basic cell (cell region) comprises a first trench, a second trench, a first polysilicon gate, a second polysilicon gate, a first gate oxide layer and a second gate oxide layer, and a transition region comprises a gate metal, a source metal and a plurality of contact holes; wherein the first polysilicon gate and the first gate oxide layer are located in the first trench, the first gate oxide layer is between the first polysilicon gate and the inner surface of the first trench, and covers the outer surface of the first polysilicon gate, the second polysilicon gate and the second gate oxide layer are located in the second trench, the second gate oxide layer is between the second polysilicon gate and the inner surface of the second trench, and covers the outer surface of the second polysilicon gate, the number of the second trenches is two, and they are respectively located on both sides of the first trench and respectively contact with the side of the first trench adjacent to itself, the thickness of the first gate oxide layer is greater than the thickness of the second gate oxide layer, the depth of the first trench is greater than the depth of the second trench, the first polysilicon gate is connected to the source metal through the corresponding contact hole in the chip transition region, and the second polysilicon gate is connected to the gate metal through the corresponding contact hole in the chip transition region. Therefore, when the device is in a blocking state, the first gate oxide layer at the bottom of the first trench will be subjected to a larger electric field strength. A larger first gate oxide layer thickness can improve the long-term reliability of the device during use. At the same time, the gate oxide layer capacitance of this part is not included in the Miller capacitance, which can reduce the Miller capacitance of the device, improve the switching speed, and reduce the overall loss of the device. When the device is in the on state, the second gate oxide layer on the sidewall of the second trench has a thinner thickness, which can reduce the channel resistance and conduction loss of the device.

[0037] The trench gate SiC MOSFET chip provided by the present invention uses a composite trench gate structure, the thickness of the gate oxide layer at the bottom and sidewall of the trench can be controlled separately, the gate oxide layer at the bottom of the trench where the electric field strength is greater is thickened, thereby improving the long-term reliability of the device during use, and the sidewall trench portion retains a thinner gate oxide layer, which helps to reduce the channel resistance and conduction loss of the device. It can be seen that the present invention can effectively reduce the channel resistance and conduction loss while ensuring that the device has high reliability.

[0038] In a trench gate SiC MOSFET chip provided in Embodiment 2 of the present invention, the cell region further includes an N+ doped region, a P+ contact region and a substrate, and the transition region further includes a drain metal; wherein, the number of the N+ doped region and the P+ contact region are both two, the two N+ doped regions are respectively located on the outer sides of the two second trenches relative to the first trench, the two P+ contact regions are respectively located on the outer sides of the two N+ doped regions relative to the second trench, the substrate is located on the back side of the chip, the N+ doped region and the P+ contact region are connected to the source metal in the transition region, and the substrate is connected to the drain metal in the transition region.

[0039] The cell area also includes back metal, buffer layer, epitaxial layer, SiO2 dielectric layer, front metal and PI glue passivation layer; wherein, the back metal, substrate, buffer layer, epitaxial layer, SiO2 dielectric layer, front metal and PI glue passivation layer are stacked in sequence from bottom to top, the first trench, the second trench, the first polysilicon gate, the second polysilicon gate, the first gate oxide layer, the second gate oxide layer, the N+ doped region and the P+ contact region are all located in the epitaxial layer, the front metal is in contact with the SiO2 dielectric layer, the N+ doped region and the P+ contact region at the same time, and the PI glue passivation layer is in contact with the front metal and the SiO2 dielectric layer respectively.

[0040] The cell region further includes a Pwell layer, which is located in the epitaxial layer and is in contact with the second gate oxide layer, the N+ doped region and the P+ contact region.

[0041] In the second embodiment of the present invention, the structure of the basic cell of the chip may include a substrate, a buffer layer, an epitaxial layer, a Pwell layer, an N+ doped region, a P+ contact region, a first polysilicon gate, a first gate oxide layer, a second polysilicon gate, a second gate oxide layer, a SiO2 dielectric layer, a front metal, a PI glue passivation layer, a groove, and a back metal. The transition region includes a gate metal, a drain metal, a source metal, and a plurality of contact holes. Figure 5 shown.

[0042] The number of N+ doping regions is 2, which are respectively located on the outer sides of the two second trenches relative to the first trench, and are in contact with the adjacent second gate oxide layer, and the depth of the N+ doping region is less than the depth of the second gate oxide layer, and the depths of the two N+ doping regions may be the same; the number of P+ contact regions is also 2, which are respectively located on the outer sides of the two N+ doping regions relative to the second trench, and are in contact with the adjacent N+ doping region, and the depth of the P+ contact region may be the same as the depth of the N+ doping region; the N+ doping region and the P+ contact region are connected to the source metal in the transition region. The Pwell layer may include two sub-regions, the two sub-regions are respectively located on the outer sides of the two P+ contact regions relative to the N+ doping region, and are respectively in contact with the two P+ contact regions, and the depths of the two sub-regions are greater than the depth of the N+ doping region, and are not greater than the depth of the second gate oxide layer.

[0043] The back metal, substrate, buffer layer, epitaxial layer, SiO2 dielectric layer, front metal and PI glue passivation layer of the chip are stacked in order from bottom to top (from back to front). The first polysilicon gate, the second polysilicon gate, the first gate oxide layer, the second gate oxide layer, the N+ doped area, the P+ contact area and the Pwell layer are all located in the epitaxial layer. The Pwell layer does not extend to the side boundary of the epitaxial layer; the SiO2 dielectric layer is located on the epitaxial layer and is divided into two sub-areas. One sub-area covers from one side boundary of the epitaxial layer to the N+ contact area on that side. The upper surface of the doped area is covered by another sub-area from the other side boundary of the epitaxial layer to the upper surface of the N+ doped area on this side; the front metal layer is located on the SiO2 dielectric layer, does not extend to the side boundary of the epitaxial layer, and fills the gap between the two sub-areas of the SiO2 dielectric layer to contact the upper surface of the P+ contact area and the upper surface of the N+ doped area; the PI glue passivation layer is located on the front metal layer, and fills the gap between the side boundary of the front metal layer and the side boundary of the SiO2 dielectric layer to contact the upper surface of the SiO2 dielectric layer. The substrate on the back of the chip is connected to the drain metal. In the implementation method of the first embodiment of the present invention, in the middle connecting part of the two grooves, there is only a concave angle in the horizontal direction without a convex angle structure, thereby avoiding the electric field concentration effect at the convex angle position of the groove, and further improving the long-term reliability of the device during use.

[0044] The trench gate SiC MOSFET chip provided by the present invention uses a composite trench gate structure, the thickness of the gate oxide layer at the bottom and sidewall of the trench can be controlled separately, the gate oxide layer at the bottom of the trench where the electric field strength is greater is thickened, thereby improving the long-term reliability of the device during use, and the sidewall trench portion retains a thinner gate oxide layer, which helps to reduce the channel resistance and conduction loss of the device. At the same time, the composite trench gate structure can also reduce the Miller capacitance of the device, improve the switching speed, and reduce the overall loss.

[0045] The first embodiment of the present invention further provides a method for manufacturing a trench gate SiC MOSFET chip, which is used to manufacture the chip as in the first embodiment of the present invention. Figure 6 As shown, the manufacturing method may specifically include: S21: setting a substrate, and sequentially growing a buffer layer and an epitaxial layer upward on the substrate; S22: sequentially injecting Pwell ions, Source ions and Pplus ions into the epitaxial layer to form corresponding Pwell layers, N+ doped regions and P+ contact regions respectively; S23: depositing and growing a SiO2 etching hard mask layer on the upper surface of the epitaxial layer, etching a first trench on the SiO2 etching hard mask layer, growing a first sacrificial oxide layer on the inner surface of the first trench, removing the first sacrificial oxide layer and growing a first gate oxide layer on the inner surface of the first trench, growing polysilicon deposition in the first gate oxide layer and etching the polysilicon on the entire surface to obtain a first polysilicon gate; S24: etching a second trench on the SiO2 etching hard mask layer, growing a second sacrificial oxide layer on the inner surface of the second trench, removing the second sacrificial oxide layer and growing a second gate oxide layer on the inner surface of the second trench, growing polysilicon deposition in the second gate oxide layer and etching the polysilicon on the entire surface to obtain a second polysilicon gate; S25: depositing and growing a SiO2 dielectric layer on the upper surface of the epitaxial layer, performing a densification process on the SiO2 dielectric layer, and etching the SiO2 dielectric layer to form a source contact hole and a gate contact hole including a dummy gate and a real gate; S26: sputtering metal nickel on a portion of the SiO2 dielectric layer and a portion of the epitaxial layer, performing thermal annealing to form an ohmic contact, wet-etching the unreacted metal nickel, continuing to sputter metal aluminum and wet-etching for patterning to obtain a front metal layer, and covering a portion of the front metal layer and a portion of the SiO2 dielectric layer with PI glue to form a PI glue passivation layer, and performing photolithography on the PI glue passivation layer; S27: Grind the lower surface of the substrate to remove silicon oxide, sputter metal nickel, perform thermal annealing to form an ohmic contact, and continue to sputter metal titanium or nickel or silver to obtain a back metal layer.

[0046] The manufacturing process of the trench gate SiC MOSFET chip provided in the second embodiment of the present invention includes ion implantation, impurity high temperature activation annealing, SiO2 wet etching, SiC trench dry etching, sacrificial oxide layer and gate oxide layer growth, polysilicon deposition and dry etching, wafer backside thinning, RTA metal alloy and other process steps. The specific manufacturing method is as follows: 1) Use 4H-SiC single crystal substrate, the wafer size is 4-8 inches, the substrate thickness is 350-500um, the conductivity type is N-type, and the doping concentration is greater than 1E18cm-3; 2) CVD epitaxy is used to grow the buffer layer and epitaxial layer (both are mainly SiC) on the SiC substrate. The thickness of the buffer layer is 0.5-2um, the thickness of the epitaxial layer is 10-30um, the doping concentration of the buffer layer is 5E16-1E18cm-3, and the doping concentration of the epitaxial layer is 1E14-1E17cm-3. During the epitaxial process, the process chamber temperature is 1400℃-1800℃, and the surface of the wafer after epitaxial growth must be kept clean; 3) Implement Pwell ion implantation (Al+ ions) in the epitaxial layer to simultaneously form the Pwell layer (mainly PSiC) and the terminal field limiting ring in the cell area, with an implantation dose of 1E13-1E14 and an implantation energy of 200-800keV; 4) Implement Source ion implantation (N ions) in the epitaxial layer to form a Source region (i.e., N+ doped region, mainly NSiC), with an implantation dose of 5E14-5E15 and an implantation energy of 40-300keV; 5) Implement Pplus ion implantation (Al+ ions) in the epitaxial layer to form a P+ contact region (mainly P SiC), with an implantation dose of 5E14-5E15 and an implantation energy of 50-500keV; 6) The impurities are activated by furnace tube annealing. The process temperature of the furnace tube is above 1600℃, and the one-time activation rate of all impurities must be above 80%; 7) PECVD deposits and grows a SiO2 etching hard mask layer on the upper surface of the epitaxial layer with a thickness of 5000-10000A; 8) Perform the first trench etching from the upper surface of the epitaxial layer downwards to a depth of 0.5-3um; 9) A sacrificial oxide layer is grown in the first trench with a thickness of 800-1200A, and the sacrificial oxide layer is removed; 10) The first gate oxide layer (mainly SiO2) is grown in the first trench, the process temperature of the furnace tube is above 1400°C, and the thickness of the gate oxide layer is 2000-5000A; 11) Polysilicon deposition growth (Dpoly, LPCVD process) is achieved in the first trench with a thickness of 8000-10000A; 12) Etch the entire surface of polysilicon to a depth of 8000-10000A to obtain the first polysilicon gate (mainly Poly Si); 13) Etch the second trench region downward from the upper surface of the epitaxial layer to a depth of 0.5-1.5um; 14) A sacrificial oxide layer is grown in the second trench with a thickness of 800-1200A, and the sacrificial oxide layer is removed; 15) A second gate oxide layer (mainly SiO2) is grown in the second trench. The process temperature of the furnace is above 1400°C and the thickness of the gate oxide layer is 500-1500A. 16) Polysilicon deposition growth (Dpoly, LPCVD process) is achieved in the second trench with a thickness of 5000-10000A; 17) Etch the entire surface of polysilicon to a depth of 5000-10000A to obtain a second polysilicon gate (mainly Poly Si); 18) A SiO2 dielectric layer is deposited and grown on the upper surface of the epitaxial layer using a PECVD process, and the dielectric layer thickness is 9000-12000A; 19) The furnace tube annealing process is used to densify the dielectric layer, and the furnace tube temperature is 600-800℃; 20) Etching in the SiO2 dielectric layer to form contact holes for the true gate, dummy gate and source; 21) Front sputtering of metal Ni, thickness 500-1000A; 22) RTA rapid thermal annealing treatment forms ohmic contact and wet etching of unreacted metal Ni; 23) Sputter metal Al on the front with a thickness of 4-8um, and pattern it by wet etching to obtain the front metal layer; 24) PI glue Coating forms a passivation protective layer (i.e. PI glue passivation layer, mainly PI), and performs photolithography with a thickness of 8-12um; 25) Grind the back of the wafer to remove silicon oxide and reduce the thickness to 120-250um; 26) Sputtering metal Ni on the back, thickness 500-1500A, RTA rapid thermal annealing treatment to form ohmic contact; 27) Back-side sputtering of metal Ti / Ni / Ag, thickness 1-2um.

[0047] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present invention. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A trench gate SiC MOSFET chip, characterized in that: The cell region includes a trench, a first polysilicon gate, a second polysilicon gate, a first gate oxide layer and a second gate oxide layer, and the transition region includes a gate metal, a source metal and a plurality of contact holes; wherein the first polysilicon gate is located at the bottom of the trench, the first gate oxide layer is located at the outer surface of the first polysilicon gate, the second polysilicon gate is located at the upper part of the trench, the second gate oxide layer is located at the outer surface of the second polysilicon gate, the thickness of the first gate oxide layer is greater than the thickness of the second gate oxide layer, the first polysilicon gate is connected to the source metal through the corresponding contact holes in the transition region, and the second polysilicon gate is connected to the gate metal through the corresponding contact holes in the transition region.

2. The trench gate SiC MOSFET chip according to claim 1, characterized in that: The cell region also includes an N+ doped region, a P+ contact region and a substrate, and the transition region also includes a drain metal; wherein the number of the N+ doped region and the number of the grooves are both two, the two N+ doped regions are located between the two grooves, and are respectively in contact with the two first gate oxide layers, the P+ contact region is sandwiched between the two N+ doped regions and is respectively in contact with the two N+ doped regions, the substrate is located on the back side of the chip, the N+ doped region and the P+ contact region are connected to the source metal in the transition region, and the substrate is connected to the drain metal in the transition region.

3. The trench gate SiC MOSFET chip according to claim 2, characterized in that: The cell region also includes back metal, Buffer layer, epitaxial layer, SiO2 dielectric layer, front metal and PI glue passivation layer; wherein the back metal, the substrate, the Buffer layer, the epitaxial layer, the SiO2 dielectric layer, the front metal and the PI glue passivation layer are stacked in sequence from bottom to top, the first polysilicon gate, the second polysilicon gate, the first gate oxide layer, the second gate oxide layer, the N+ doped area and the P+ contact area are all located in the epitaxial layer, the front metal is in contact with the SiO2 dielectric layer, the N+ doped area and the P+ contact area at the same time, and the PI glue passivation layer is in contact with the front metal and the SiO2 dielectric layer respectively.

4. The trench gate SiC MOSFET chip according to claim 3, characterized in that: The cell region further includes a Pwell layer, which is located in the epitaxial layer and is in contact with the second gate oxide layer, the N+ doped region and the P+ contact region.

5. A method for manufacturing a trench gate SiC MOSFET chip, characterized in that: Used to manufacture the trench gate SiC MOSFET chip according to any one of claims 1 to 4, the manufacturing method comprising: Providing a substrate, and sequentially growing a buffer layer and an epitaxial layer upward on the substrate; In the epitaxial layer, Pwell ions, Source ions and Pplus ions are sequentially implanted to form corresponding Pwell layers, N+ doped regions and P+ contact regions respectively; Depositing and growing a SiO2 etching hard mask layer on the upper surface of the epitaxial layer, etching a groove on the SiO2 etching hard mask layer, growing a sacrificial oxide layer on the inner surface of the groove, removing the sacrificial oxide layer and growing a first gate oxide layer on the inner surface of the groove, growing polysilicon deposition in the first gate oxide layer and etching the polysilicon on the entire surface to obtain a first polysilicon gate; Wet-etching a first gate oxide layer located on the inner surface of the upper portion of the trench, growing a second gate oxide layer on the inner surface of the upper portion of the trench, growing polysilicon deposits in the first gate oxide layer and etching the entire surface of the polysilicon to obtain a second polysilicon gate; Photolithography defines a dummy gate contact hole region, removes the upper polysilicon in the trench by etching, deposits and grows a SiO2 dielectric layer on the upper surface of the epitaxial layer, densifies the SiO2 dielectric layer, and etches the SiO2 dielectric layer to form a source contact hole and a gate contact hole including a dummy gate and a real gate; Sputtering metal nickel on the upper surface of part of the SiO2 dielectric layer and part of the epitaxial layer, performing thermal annealing to form ohmic contact, wet-etching unreacted metal nickel, continuing to sputter metal aluminum and wet-etching for patterning to obtain a front metal layer, and covering part of the front metal layer and part of the SiO2 dielectric layer with PI glue to form a PI glue passivation layer, and performing photolithography on the PI glue passivation layer; The lower surface of the substrate is ground to remove silicon oxide, and metal nickel is sputtered, and thermal annealing is performed to form an ohmic contact, and metal titanium, nickel or silver is continuously sputtered to obtain a back metal layer.

6. A trench gate SiC MOSFET chip, characterized in that: The cell region includes a first trench, a second trench, a first polysilicon gate, a second polysilicon gate, a first gate oxide layer and a second gate oxide layer, and the transition region includes a gate metal, a source metal and a plurality of contact holes; wherein the first polysilicon gate is located in the first trench, the first gate oxide layer is located on the outer surface of the first polysilicon gate, the second polysilicon gate is located in the second trench, the second gate oxide layer is located on the outer surface of the second polysilicon gate, the number of the second trenches is two, and they are respectively located on both sides of the first trench, the thickness of the first gate oxide layer is greater than the thickness of the second gate oxide layer, the depth of the first trench is greater than the depth of the second trench, the first polysilicon gate is connected to the source metal through the corresponding contact holes in the transition region, and the second polysilicon gate is connected to the gate metal through the corresponding contact holes in the transition region.

7. The trench gate SiC MOSFET chip according to claim 6, characterized in that: The cell region also includes an N+ doped region, a P+ contact region and a substrate, and the transition region also includes a drain metal; wherein, the number of the N+ doped region and the P+ contact region are both two, the two N+ doped regions are respectively located on the outer sides of the two second grooves relative to the first groove, the two P+ contact regions are respectively located on the outer sides of the two N+ doped regions relative to the second groove, the substrate is located on the back side of the chip, the N+ doped region and the P+ contact region are connected to the source metal in the transition region, and the substrate is connected to the drain metal in the transition region.

8. The trench gate SiC MOSFET chip according to claim 7, characterized in that: The cell region also includes back metal, Buffer layer, epitaxial layer, SiO2 dielectric layer, front metal and PI glue passivation layer; wherein the back metal, the substrate, the Buffer layer, the epitaxial layer, the SiO2 dielectric layer, the front metal and the PI glue passivation layer are stacked in sequence from bottom to top, the first trench, the second trench, the first polysilicon gate, the second polysilicon gate, the first gate oxide layer, the second gate oxide layer, the N+ doped area and the P+ contact area are all located in the epitaxial layer, the front metal is in contact with the SiO2 dielectric layer, the N+ doped area and the P+ contact area at the same time, and the PI glue passivation layer is in contact with the front metal and the SiO2 dielectric layer respectively.

9. The trench gate SiC MOSFET chip according to claim 8, characterized in that: The cell region further includes a Pwell layer, which is located in the epitaxial layer and is in contact with the second gate oxide layer, the N+ doped region and the P+ contact region.

10. A method for manufacturing a trench gate SiC MOSFET chip, characterized in that: Used to manufacture the trench gate SiC MOSFET chip according to any one of claims 6 to 9, the manufacturing method comprising: Providing a substrate, and sequentially growing a buffer layer and an epitaxial layer upward on the substrate; In the epitaxial layer, Pwell ions, Source ions and Pplus ions are sequentially implanted to form corresponding Pwell layers, N+ doped regions and P+ contact regions respectively; Depositing and growing a SiO2 etching hard mask layer on the upper surface of the epitaxial layer, etching a first trench on the SiO2 etching hard mask layer, growing a first sacrificial oxide layer on the inner surface of the first trench, removing the first sacrificial oxide layer and growing a first gate oxide layer on the inner surface of the first trench, growing polysilicon deposition in the first gate oxide layer and etching the polysilicon on the entire surface to obtain a first polysilicon gate; Etching a second trench on the SiO2 etching hard mask layer, growing a second sacrificial oxide layer on the inner surface of the second trench, removing the second sacrificial oxide layer and growing a second gate oxide layer on the inner surface of the second trench, growing polysilicon deposits in the second gate oxide layer and etching the polysilicon on the entire surface to obtain a second polysilicon gate; Depositing and growing a SiO2 dielectric layer on the upper surface of the epitaxial layer, performing a densification process on the SiO2 dielectric layer, and etching the SiO2 dielectric layer to form a source contact hole and a gate contact hole including a dummy gate and a real gate; Sputtering metal nickel on the upper surface of part of the SiO2 dielectric layer and part of the epitaxial layer, performing thermal annealing to form ohmic contact, wet-etching unreacted metal nickel, continuing to sputter metal aluminum and wet-etching for patterning to obtain a front metal layer, and covering part of the front metal layer and part of the SiO2 dielectric layer with PI glue to form a PI glue passivation layer, and performing photolithography on the PI glue passivation layer; The lower surface of the substrate is ground to remove silicon oxide, metal nickel is sputtered, and thermal annealing is performed to form an ohmic contact, and metal titanium, nickel or silver is continuously sputtered to obtain a back metal layer.

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