Mask structure and photoetching method

Abstract

The invention relates to a mask structure and a photoetching method. The mask structure comprises a functional area used for forming a graphical semiconductor structure in the middle area of a wafer through photoetching; the first cutting channel region is arranged around the functional region, the first cutting channel region at least comprises a first pattern, and the first pattern is used for positioning a target photoetching position when a patterned semiconductor structure is formed by photoetching; the second cutting channel area is located on the first outer side of the first cutting channel area, the second cutting channel area comprises a second pattern, and the second pattern is used for forming a first positioning mark on the first edge of the wafer through photoetching. The mask structure provided by the embodiment of the invention can be simultaneously applied to photoetching of a patterned semiconductor structure and photoetching of the first positioning mark at the edge of the wafer, the number of masks for the first positioning mark is reduced, the cost is reduced, the data processing flow and the process frequency are reduced, and the time is shortened.

Description

Technical Field

[0001] The invention relates to the field of semiconductor technology, in particular to a mask structure and a photolithography method. Background Art

[0002] Semiconductor manufacturing forms effective chips on wafers, usually in the smallest exposure unit (shot). Generally, the wafer is manufactured in a circular shape, and the chip is formed by photolithography in the middle area of ​​the circular wafer through a mask.

[0003] In order to form positioning marks in the non-chip area at the edge of the wafer to facilitate subsequent processing of the wafer, different masks are designed in traditional technology, and the masks are placed at the edge of the wafer for photolithography to form positioning marks.

[0004] However, the structures of the mask used to form the chip and the mask used to form the positioning mark are different, which leads to an increase in the number of masks, increased costs, and the need for multiple design processes, which increases the time and complexity of the operation. Summary of the invention

[0005] Based on this, it is necessary to provide a mask structure and a photolithography method to address the problems of high production cost and complicated process for forming positioning marks in the edge area of ​​a wafer.

[0006] In a first aspect, the present application provides a mask structure, the mask structure comprising:

[0007] A functional area for forming a patterned semiconductor structure in a middle area of ​​the wafer by photolithography;

[0008] A first cutting road area is arranged around the functional area, the first cutting road area at least includes a first pattern, and the first pattern is used to locate a target lithography position when forming a patterned semiconductor structure by lithography;

[0009] The second cutting street area is located at a first outer side of the first cutting street area. The second cutting street area includes a second pattern. The second pattern is used to form a first positioning mark on a first edge of the wafer by photolithography.

[0010] In one embodiment, the mask structure further includes a third cutting street area, the third cutting street area is located at a second outer side of the first cutting street area, the third cutting street area includes a third pattern, and the third pattern is used to form a second positioning mark on the second edge of the chip by photolithography.

[0011] In one embodiment, a first outer side of the first scribe line area is on the same side as a first edge of the wafer; and / or a second outer side of the first scribe line area is on the same side as a second edge of the wafer.

[0012] In one embodiment, the first edge and the second edge of the wafer are located on two opposite sides, or on two adjacent sides.

[0013] In one embodiment, the mask structure is rectangular, the functional area is rectangular, the first cutting street area is square ring-shaped, the second cutting street area is strip-shaped, and the wafer is circular.

[0014] In one embodiment, the width of the first cutting street area at the long side of the functional area is smaller than the width at the wide side of the functional area.

[0015] In one embodiment, the second cutting street area is located on a side of a long side of the first cutting street area.

[0016] In a second aspect, the present application further provides a photolithography method using the mask structure, the method comprising the following steps:

[0017] The second cutting street area is used as a shielding area, the functional area and the first cutting street area are used as light-seeing areas, and the position is changed by the mask structure to form a plurality of patterned semiconductor structures in the middle area of ​​the wafer;

[0018] The second cutting path area is used as a light-visible area, and a first positioning mark is formed on the first edge of the wafer.

[0019] In one embodiment, the step of using the second cutting path area as the light-visible area and forming a first positioning mark on the first edge of the wafer includes:

[0020] The second scribe line area, the first scribe line area and the functional area are used as light-seeing areas, and the first positioning mark located at the first edge and the patterned semiconductor structure adjacent to the first edge are simultaneously formed on the wafer; or,

[0021] The second cutting street area is used as a light-seeing area, the first cutting street area and the functional area are used as shielding areas, and a first positioning mark is formed only on a first edge of the wafer.

[0022] In one embodiment, the method further comprises:

[0023] The third cutting path area is used as a light-seeing area, and a second positioning mark is formed on the second edge of the wafer.

[0024] In the above-mentioned mask structure, the mask structure adds a second cutting road area outside the functional area and the first cutting road area, and the second cutting road area has a second pattern. In this way, the second cutting road area is shielded, and a patterned semiconductor structure can be formed in the center of the wafer when the functional area and the first cutting road area are the visible light area; when it is necessary to form a first positioning mark on the wafer, the second cutting road area is made the visible light area, and the first positioning mark can be formed by photolithography. The mask structure provided in this embodiment can be simultaneously applied to the photolithography of the patterned semiconductor structure and the photolithography of the first positioning mark at the edge of the wafer, reducing the number of masks for the first positioning mark, reducing costs, and reducing the data processing flow and the number of processes, shortening the time. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] FIG. 1 is a schematic diagram showing the positions of auxiliary positioning marks on a wafer.

[0026] FIG. 2 is a schematic diagram showing the structure of a mask for positioning marks.

[0027] FIG. 3 is a schematic diagram showing the position of a mask plate used for positioning marks when forming auxiliary positioning marks in conventional technology.

[0028] FIG. 4 is a schematic structural diagram of a mask structure in an embodiment.

[0029] FIG. 5 is a schematic diagram of forming a positioning mark using a mask structure in one embodiment.

[0030] FIG6 is a schematic diagram of a light-seeing area when the mask structure is located at a non-first edge position of a wafer in one embodiment;

[0031] FIG. 7 is a schematic diagram of a light-seeing area when the mask structure is located at a first edge position of a wafer in one embodiment.

[0032] FIG. 8 is a flow chart of a photolithography method in one embodiment.

[0033] Description of reference numerals:

[0034] 10. Wafer; 11. Patterned semiconductor structure; 12. First positioning mark; 13. Second positioning mark; M1. Mask for positioning mark; M11. Marking pattern; 20. Mask structure; 21. Functional area; 22. First cutting area; 221. First pattern; 23. Second cutting area; 231. Second pattern; 24. Third cutting area; 241. Third pattern. DETAILED DESCRIPTION

[0035] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the specific embodiments of the present invention are described in detail below in conjunction with the accompanying drawings. In the following description, many specific details are set forth to facilitate a full understanding of the present invention. However, the present invention can be implemented in many other ways different from those described herein, and those skilled in the art can make similar improvements without violating the connotation of the present invention, so the present invention is not limited by the specific embodiments disclosed below.

[0036] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0037] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of the present invention, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0038] In the present invention, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0039] In the present invention, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, a first feature being "above", "above" or "above" a second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. A first feature being "below", "below" or "below" a second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.

[0040] It should be noted that when an element is referred to as being "fixed to" or "disposed on" another element, it may be directly on the other element or there may be a central element. When an element is considered to be "connected to" another element, it may be directly connected to the other element or there may be a central element at the same time. The terms "vertical", "horizontal", "upper", "lower", "left", "right" and similar expressions used herein are for illustrative purposes only and are not intended to be the only implementation method.

[0041] Photolithography is the foundation of large-scale integrated circuit manufacturing technology, which largely determines the integration of integrated circuits. Photolithography is the process of transferring the pattern on the mask, i.e., the photomask, to a wafer coated with photoresist by exposure. After development, the pattern on the mask appears on the wafer. In the manufacturing process of integrated circuits, it is usually necessary to expose several or even dozens of layers of mask patterns on the wafer to form a complete circuit structure. Before each photolithography exposure, the mask used for the photolithography needs to be accurately aligned with the first layer of pattern or the previous layer or layers of pattern that have been exposed on the wafer.

[0042] As shown in FIG1 , in the process of preparing an integrated circuit, in order to facilitate the identification of the position of the wafer 10 in the subsequent process, it is necessary to form auxiliary positioning marks on the wafer 10. Generally, the middle area of ​​the wafer 10 is used to form a patterned semiconductor structure 11, and through multiple processes, a layer-stacked patterned semiconductor structure 11 is formed to obtain a chip. The edge area of ​​the wafer is used to form auxiliary positioning marks, such as forming a first positioning mark 12 at the first edge of the wafer 10 and forming a second positioning mark 13 at the second edge of the wafer 10. Exemplarily, the mask structure includes a central functional area and a cutting road area located on the side of the functional area. The cutting road area can be used as a mask frame. When designing a mask, the same mask frame can be used to design only the graphics of the functional area, thereby obtaining different semiconductor structures in the photolithography process.

[0043] In the conventional technology, in order to form auxiliary positioning marks in the edge area of ​​the wafer 10, two mask designs are used, one is a mask for chips, and the other is a mask for positioning marks M1. Referring to FIG2, FIG2 shows a schematic diagram of the structure of the mask for positioning marks M1. For example, the mask for chips and the mask for positioning marks M1 have the same mask frame, that is, the cutting road area is the same. In the photolithography process, a plurality of chips in an array are formed in the middle area of ​​the wafer 10 by using the mask for chips, and auxiliary positioning marks are formed in the edge area of ​​the wafer 10 by using the mask for positioning marks M1. The functional area 21 of the mask for positioning marks M1 has a mark pattern M11 for forming auxiliary positioning marks. After positioning by the cutting road area, auxiliary positioning marks can be formed on the wafer 10 by photolithography. Referring to FIG3, FIG3 shows a schematic diagram of the position of the mask for positioning marks M1 when forming auxiliary positioning marks in the conventional technology, that is, the positioning marks on the wafer 10 are essentially processed by the same process as the photolithography chip, so the functional area 21 needs to be designed.

[0044] However, the conventional technology has the following problems: first, one or more masks need to be added, one for the chip and one for the positioning mark, which increases the cost; second, using the positioning mark as chip lithography requires multiple data processing and mask structure design 20, which increases the operation time and complexity.

[0045] Referring to FIG. 4, FIG. 4 shows a schematic diagram of the structure of a mask structure 20 in an embodiment of the present invention. The mask structure 20 provided in an embodiment of the present invention includes a functional area 21, a first scribe area 22, and a second scribe area 23. The first scribe area 22 is arranged around the functional area 21, and the second scribe area 23 is located at a first outer side of the first scribe area 22. The functional area 21 is used to form a patterned semiconductor structure, the first scribe area 22 is used for positioning, and the second scribe area 23 is used to form a positioning mark on the wafer 10.

[0046] Specifically, the functional area 21 is used to form a patterned semiconductor structure 11 in the middle area of ​​the chip 10 by photolithography. Exemplarily, the chip 10 can be a wafer, and the size of the chip 10 is not limited. Exemplarily, one layer of patterned semiconductor structure 11 is formed by photolithography, and multiple layers of patterned semiconductor structure 11 are formed by photolithography to obtain a chip.

[0047] The first scribe line region 22 includes at least a first pattern 221, and the first pattern 221 is used to locate the target lithography position when the patterned semiconductor structure 11 is formed by lithography. Exemplarily, the first pattern 221 is used to form a third positioning mark on the wafer 10, and the third positioning mark is used for positioning when forming a multi-layer patterned semiconductor to ensure that each layer of the patterned semiconductor is aligned.

[0048] Exemplarily, forming a chip requires multiple photolithography processes, and each photolithography process must ensure that the position corresponds to the position of the patterned semiconductor structure 11 layer formed in the previous process. By setting a first pattern 221 on the first cutting path and forming a third positioning mark on the chip 10, position alignment can be ensured in each photolithography process.

[0049] The second scribe line area 23 includes a second pattern 231, and the second pattern 231 is used to form a first positioning mark 12 on the first edge of the wafer 10 by photolithography. Exemplarily, the first positioning mark 12 is used to locate the wafer position. As shown in FIG. 5, FIG. 5 shows a schematic diagram of forming a positioning mark using a mask structure 20 in an embodiment, and each patterned semiconductor structure 11 is hidden. With the second scribe line area 23 as a visible area, a first positioning mark 12 corresponding to the second pattern 231 can be formed on the wafer 10. In a feasible photolithography method, referring to FIG6 , the dotted-line box is used as a visible light area. When the mask structure 20 is located at a non-first edge position of the chip 10, the functional area 21 and the first cutting path area 22 are visible light areas, and the second cutting path area 23 is a shielding area; referring to FIG7 , the dotted-line box is used as a visible light area. When the mask structure 20 is located at the first edge position of the chip 10, the functional area 21, the first cutting path area 22 and the second cutting path area 23 are all visible light areas. In this way, the first patterned semiconductor structure and the first positioning mark 12 can be formed at the same time, thereby reducing the number of processes.

[0050] In the above-mentioned mask structure 20, the mask structure 20 is provided with a second cutting street area 23 outside the functional area 21 and the first cutting street area 22, and the second cutting street area 23 has a second pattern 231. In this way, the second cutting street area 23 is shielded, and a patterned semiconductor structure can be formed in the center of the wafer 10 when the functional area 21 and the first cutting street area 22 are the light-visible areas; when it is necessary to form the first positioning mark 12 on the wafer 10, the second cutting street area 23 is made into the light-visible area, and the first positioning mark 12 can be formed by photolithography. The mask structure 20 provided in this embodiment can be simultaneously applied to the photolithography of the patterned semiconductor structure 11 and the photolithography of the first positioning mark 12 at the edge of the wafer 10, reducing the number of masks for the first positioning mark 12, reducing costs, and reducing data processing procedures and process times, shortening time.

[0051] Continuing to refer to FIG. 4 , in order to better position the wafer 10, it is necessary to form positioning marks on different sides of the wafer 10. In some embodiments, the mask structure 20 further includes a third cutting street area 24, and the third cutting street area 24 is located at the second outer side of the first cutting street area 22, and the second outer side is a side of the first cutting street area 22 different from the first outer side. The third cutting street area 24 includes a third pattern 241, and the third pattern 241 is used to form a second positioning mark 13 on the second edge of the wafer 10 by photolithography. Similar to the second cutting street area 23, when the third cutting street area 24 is used as a light-seeing area, a second positioning mark 13 can be formed on the second edge of the wafer 10. Compared with the case of a single positioning mark, by respectively forming the first positioning mark 12 and the second positioning mark 13 at different edges of the wafer 10, accurate positioning of the wafer 10 can be achieved to prevent the wafer 10 from being offset.

[0052] Optionally, the first positioning mark 12 may be a cross-shaped mark or other shapes that are easy to identify, and the second positioning mark 13 may also be a cross-shaped mark or other shapes that are easy to identify.

[0053] In some embodiments, the first outer side of the first cutting street area 22 is on the same side as the first edge of the chip 10; as shown in Figure 5, in a feasible implementation, the first outer side of the first cutting street area 22 is the left side, and the first edge of the chip 10 is also the left side. Therefore, when the mask is located at the target formation position of the first positioning mark 12, the first positioning mark 12 and the adjacent patterned semiconductor structure can be formed simultaneously by photolithography, saving the number of processes.

[0054] Optionally, the second outer side of the first scribe line area 22 is on the same side as the second edge of the wafer 10. Similar to the design of the first scribe line area 22, when the mask is located at the second edge of the wafer 10, the second positioning mark 13 and the adjacent patterned semiconductor structure can be formed simultaneously by photolithography.

[0055] In some embodiments, the first edge and the second edge of the wafer 10 are located on opposite sides, or on adjacent sides. In a specific embodiment, as shown in FIG4 , the first edge and the second edge of the wafer 10 are located on opposite sides, and the first positioning mark 12 and the second positioning mark 13 are located on opposite sides, respectively. In another specific embodiment, the first edge and the second edge of the wafer 10 are located on adjacent sides, and the first positioning mark 12 and the second positioning mark 13 are located on adjacent sides, respectively.

[0056] Generally, the chip 10 is constructed in a circular shape as a wafer. To facilitate the photolithography process, the mask structure 20 is rectangular, the functional area 21 is also rectangular, the first cutting road area 22 is a square ring, and is arranged around the functional area 21 as a mask frame, and the second cutting road area 23 is a strip. By changing the position of the mask structure 20 above the chip 10 for photolithography, the functional area 21 can be used to form an array of patterned semiconductor structures 11 on the chip 10.

[0057] However, the square mask cannot fully utilize the surface space of the wafer, and multiple markable spaces will be formed on the edge of the wafer, including at least the mark spaces on the left and right sides. For example, the left space can form the first positioning mark 12, and the right space can form the second positioning mark 13.

[0058] In some embodiments, the width of the first scribe line area 22 on the long side of the functional area 21 is smaller than the width on the wide side of the functional area 21. In this way, the positioning space formed by the wafer 10 in the long side direction of the functional area 21 is larger than that in the wide side direction. As shown in FIG. 4 , the second scribe line area 23 is located on one side of the long side of the first scribe line area 22, so as to facilitate the formation of the first positioning mark 12.

[0059] As shown in FIG. 8 , in some embodiments, a photolithography method using a mask structure 20 includes the following steps S802 to S804 .

[0060] S802 , taking the second scribe line area 23 as the shielding area, the functional area 21 and the first scribe line area 22 as the light-seeing area, and changing the position of the mask structure 20 to form a plurality of patterned semiconductor structures 11 in the middle area of ​​the wafer 10 .

[0061] Exemplarily, the shielding area refers to a light-proof area, and the light-seeing area refers to a light-transmitting area. The photoresist is developed and exposed by irradiating the light in the light-seeing area, thereby forming a patterned semiconductor structure 11.

[0062] Exemplarily, the mask structure 20 is developed at different positions in the middle region of the wafer 10 to form a patterned semiconductor structure 11 in an array.

[0063] S804 , forming a first positioning mark 12 on a first edge of the wafer 10 by using the second scribe line area 23 as a light-exposed area.

[0064] In this way, the mask structure 20 provided in this embodiment can be directly used to form the first positioning mark 12 without the need for additional mask design, thereby reducing the number of masks, lowering costs, and reducing the number of processes and shortening the process time.

[0065] In some embodiments, step S804 uses the second cutting street area 23 as the visible area to form a first positioning mark 12 on the first edge of the chip 10, including: using the second cutting street area 23, the first cutting street area 22 and the functional area 21 as the visible area, and simultaneously forming the first positioning mark 12 located at the first edge and the graphic semiconductor structure 11 adjacent to the first edge on the chip 10; or, using the second cutting street area 23 as the visible area, the first cutting street area 22 and the functional area 21 as the shielding area, and only forming the first positioning mark 12 on the first edge of the chip 10.

[0066] In a feasible implementation, the second cutting street area 23, the first cutting street area 22 and the functional area 21 are all used as light-visible areas. When the mask structure 20 is located at the first edge of the chip 10, a patterned semiconductor structure 11, a first positioning mark 12 and a third positioning mark can be simultaneously formed on the chip 10 through exposure and development.

[0067] In another feasible implementation, the second cutting street area 23 is the light-visible area, the first cutting street area 22 and the functional area 21 are the shielding areas, and when the mask structure 20 is located at the first edge of the chip 10, through development and exposure, light can only pass through the second pattern 231 to form a first positioning mark 12 on the first edge of the chip 10.

[0068] In both of the above two implementations, there is no need to design a mask structure 20 for the first positioning mark 12. Compared with the conventional method of constructing the functional area 21 as the pattern of the first positioning mark 12, this embodiment can reduce the design process.

[0069] In some embodiments, the photolithography method using the mask structure 20 further includes: using the third scribe area 24 as the visible light area, forming a second positioning mark 13 on the second edge of the wafer 10. Exemplarily, it includes: using the third scribe area 24, the first scribe area 22 and the functional area 21 as the visible light area, forming the second positioning mark 13 and the patterned semiconductor structure 11 adjacent to the second edge on the wafer 10 at the same time; or, using the third scribe area 24 as the visible light area, the first scribe area 22 and the functional area 21 as the shielding area, and forming the second positioning mark 13 only on the second edge of the wafer 10.

[0070] In a feasible implementation, the third cutting street area 24, the first cutting street area 22 and the functional area 21 are all used as light-visible areas. When the mask structure 20 is located at the second edge of the chip 10, a patterned semiconductor structure 11, a second positioning mark 13 and a third positioning mark can be simultaneously formed on the chip 10 through exposure and development.

[0071] In another feasible implementation, the third cutting street area 24 is the light-visible area, the first cutting street area 22 and the functional area 21 are the shielding areas, and when the mask structure 20 is located at the second edge of the chip 10, through development and exposure, light can only pass through the third pattern 241 to form a second positioning mark 13 on the second edge of the chip 10.

[0072] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0073] The above-mentioned embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A mask structure, characterized in that: The mask structure comprises: A functional area for forming a patterned semiconductor structure in a middle area of ​​the wafer by photolithography; A first cutting road area is arranged around the functional area, the first cutting road area at least includes a first pattern, and the first pattern is used to locate a target lithography position when forming a patterned semiconductor structure by lithography; The second cutting street area is located at a first outer side of the first cutting street area. The second cutting street area includes a second pattern. The second pattern is used to form a first positioning mark on a first edge of the wafer by photolithography.

2. The mask structure according to claim 1, characterized in that: The mask structure further includes a third cutting street area, the third cutting street area is located at a second outer side of the first cutting street area, the third cutting street area includes a third pattern, and the third pattern is used to form a second positioning mark on the second edge of the wafer by photolithography.

3. The mask structure according to claim 2, characterized in that: A first outer side of the first scribe line area is on the same side as a first edge of the wafer; and / or a second outer side of the first scribe line area is on the same side as a second edge of the wafer.

4. The mask structure according to claim 2, characterized in that: The first edge and the second edge of the wafer are located on two opposite sides, or on two adjacent sides.

5. The mask structure according to claim 1, characterized in that: The mask structure is rectangular, the functional area is rectangular, the first cutting road area is square ring-shaped, the second cutting road area is strip-shaped, and the wafer is circular.

6. The mask structure according to claim 5, characterized in that: The width of the first cutting street area at the long side of the functional area is smaller than the width at the wide side of the functional area.

7. The mask structure according to claim 1, characterized in that: The second cutting street area is located at one side of the long side of the first cutting street area.

8. A photolithography method using the mask structure according to any one of claims 1 to 7, characterized in that: The method comprises the following steps: The second cutting street area is used as a shielding area, the functional area and the first cutting street area are used as light-seeing areas, and the position is changed by the mask structure to form a plurality of patterned semiconductor structures in the middle area of ​​the wafer; The second cutting path area is used as a light-visible area, and a first positioning mark is formed on the first edge of the wafer.

9. The method according to claim 8, characterized in that The step of forming a first positioning mark on the first edge of the wafer by using the second cutting path area as the light-seeing area includes: The second scribe line area, the first scribe line area and the functional area are used as light-seeing areas, and the first positioning mark located at the first edge and the patterned semiconductor structure adjacent to the first edge are simultaneously formed on the wafer; or, The second cutting street area is used as a light-seeing area, the first cutting street area and the functional area are used as shielding areas, and a first positioning mark is formed only on a first edge of the wafer.

10. The method according to claim 8, characterized in that The method further comprises: The third cutting path area is used as a light-seeing area, and a second positioning mark is formed on the second edge of the wafer.

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