High-speed interconnection adapter plate and multi-node server system
Through the time domain reflection technology of high-speed interconnection adapter board combined with TDR chip and MUX chip, the problem of fault location of high-speed interconnection signal links in multi-node server systems is solved, accurate fault location and maintenance is achieved, and maintenance costs are reduced.
Patent Information
- Application Number
- CN202411433025.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-14
- Publication Date
- 2025-01-03
AI Technical Summary
In multi-node server systems, traditional troubleshooting methods are difficult to accurately locate fault points in high-speed interconnected signal links, resulting in high maintenance costs and long time.
A high-speed interconnection adapter board is adopted, combined with TDR chip and MUX chip, and time-domain reflection technology is used to locate faults. The transmission of TDR chip test signals is controlled through the MUX chip to avoid interference with the transmission of high-speed interconnection signals.
It realizes accurate positioning of high-speed interconnected signal failure points in multi-node server systems, improves maintenance efficiency and reduces maintenance costs.
Smart Images
Figure CN119248591A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of fault detection, and in particular to a high-speed interconnection adapter board and a multi-node server system. Background Art
[0002] In the traditional multi-node server architecture, server nodes are interconnected through high-speed interconnection cables to realize CPU (Central Processing Unit) signals, such as SMP (Symmetric multiprocessing) signals, UPI (Ultra Path Interconnect, point-to-point processor interconnect) signals, etc., thereby forming a multi-node server system. At the same time, server nodes can also be connected to storage nodes or I / O (Input / Outout) nodes through high-speed interconnection cables to realize I / O expansion functions, which involve SAS (Serial Attached SCSI, serial connection SCSI interface signal) signals, PCIe (peripheral component interconnect express, high-speed serial computer expansion bus standard) signals or CXL (Compute ExpressLink, a high-speed serial protocol) signals, etc. The above signals all belong to the category of high-speed interconnection signals and are widely used in the interconnection system of multi-way servers and multi-node servers.
[0003] However, the interconnection system is usually composed of multiple high-speed interconnection cables and boards. Once a link in the interconnection system fails, it is often difficult to directly locate which high-speed interconnection cable or board on which node has a problem. Traditional troubleshooting methods usually include replacing the high-speed interconnection cables and boards on the faulty link one by one or all of them, which not only increases maintenance costs, but also greatly increases the time and workload of on-site maintenance.
[0004] Therefore, it is urgent to propose a high-speed interconnect adapter board to solve the above problems. Summary of the invention
[0005] In view of this, the present invention proposes a high-speed interconnection adapter board and a multi-node server system, which solves the problem of being unable to accurately locate the fault point in the multi-section high-speed interconnection signal link between multiple server nodes in the multi-node server system, greatly improves maintenance efficiency and reduces maintenance costs.
[0006] Based on the above purpose, an embodiment of the present invention provides a high-speed interconnect adapter board, which is applied to a multi-node server system, including: A plurality of connectors, each of which is connected to a server node in the multi-node server system and is used to receive and forward a high-speed interconnection signal of the server node; A plurality of MUX chips, each of which is connected to a plurality of the connectors, and is used to receive and forward the high-speed interconnection signal between the plurality of the connectors; A TDR chip is connected to the plurality of MUX chips and is used for sending a test signal to each MUX chip and receiving a reflected signal returned by the MUX chip in response to an abnormal signal sent by a server node being received by the connector, so as to locate a fault point in the multi-node server system based on the reflected signal.
[0007] In some embodiments, the high-speed interconnect adapter board also includes a CPLD, which is respectively connected to the TDR chip, all the MUX chips and all the connectors, and is used to send a control signal to each MUX chip in response to receiving an abnormal signal sent by the connector, so as to control each MUX chip to open a signal link with the TDR chip.
[0008] In some embodiments, the connector includes a first connector and a second connector, the MUX chip includes a first MUX chip and a second MUX chip, The output end of the first connector is connected to the input end of the first MUX chip through a first input link, and is used to send a first high-speed interconnect signal to the first MUX chip. The output end of the second connector is connected to the input end of the second MUX chip through a second input link, and is used to send a second high-speed interconnect signal to the second MUX chip. The output end of the first MUX chip is connected to the input end of the second connector through a first output link, and is used to forward the first high-speed interconnect signal to the second connector. The output end of the second MUX chip is connected to the input end of the first connector through a second output link, and is used to forward the second high-speed interconnect signal to the first connector.
[0009] In some implementations, the first MUX chip is further configured to: In response to receiving the control signal sent by the CPLD, closing the first input link and opening the first signal link with the TDR chip to receive the test signal; The test signal is forwarded to the second connector via the first output link, and in response to receiving the reflection signal corresponding to the test signal returned by the second connector, the reflection signal is sent to the TDR chip.
[0010] In some implementations, the second MUX chip is further configured to: In response to receiving the control signal sent by the CPLD, closing the second input link and opening a second signal link with the TDR chip to receive the test signal; The test signal is forwarded to the first connector through the second output link, and in response to receiving the reflection signal corresponding to the test signal returned by the first connector, the reflection signal is sent to the TDR chip.
[0011] In some implementations, each of the connectors is configured to forward the abnormal signal to the CPLD in response to receiving an abnormal signal sent by the server node to which it is connected.
[0012] In some implementations, the CPLD is configured to send the high-speed interconnect signal transmission abnormality information to the TDR chip in response to receiving the abnormal signal.
[0013] In some embodiments, the high-speed interconnect adapter board further includes an integrated circuit board, and the TDR chip is disposed on the integrated circuit board.
[0014] In some implementations, each of the connectors is connected to the server node or to other high-speed interconnect adapter boards except the high-speed interconnect adapter board where the connector is located through a high-speed cable.
[0015] Another aspect of the embodiment of the present invention further provides a multi-node server system, the multi-node server system comprising a plurality of server nodes, and a plurality of high-speed interconnect adapter boards as described above connected between the server nodes, each of the server nodes further comprising: The host central processor is configured to send an abnormal signal to the high-speed interconnect adapter board to which it is connected in response to detecting abnormal information of high-speed interconnect signal transmission.
[0016] The present invention has at least the following beneficial technical effects: the present invention provides a high-speed interconnect adapter card with fault detection technology, combines a TDR chip with a MUX chip, uses time domain reflection technology to detect faults of high-speed interconnect cables and boards, and accurately locates the fault point of the high-speed interconnect signal in the server system, and controls the transmission of the TDR chip test signal through the MUX chip, effectively avoiding transmission interference with the high-speed interconnect signal, which not only meets the use requirements of high-speed interconnection scenarios between nodes in a multi-node server system, but also can accurately locate the fault point in the high-speed interconnect signal link, solves the problem that the fault point of multi-section high-speed interconnect signals in a multi-node server system cannot be accurately located, and realizes accurate maintenance and replacement of faulty cables or faulty boards, greatly improving maintenance efficiency and reducing maintenance costs. BRIEF DESCRIPTION OF THE DRAWINGS
[0017] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present invention. For ordinary technicians in this field, other embodiments can be obtained based on these drawings without paying creative work.
[0018] Figure 1 A schematic diagram of an embodiment of a link failure in a traditional multi-node server system; Figure 2 A schematic diagram of an embodiment of a high-speed interconnect adapter board provided by the present invention; Figure 3 A schematic structural diagram of an embodiment of a high-speed interconnect adapter board provided by the present invention; Figure 4 A schematic diagram of an embodiment of the present invention providing fault detection of a cable 1 based on a high-speed interconnect adapter board; Figure 5 A schematic diagram of an embodiment of the present invention for detecting cable 2 faults based on a high-speed interconnect adapter board; Figure 6 A schematic diagram of an embodiment of the present invention for detecting cable 3 faults based on a high-speed interconnect adapter board; Figure 7 A schematic diagram of an embodiment of the present invention providing a method for detecting a fault of a board based on a high-speed interconnect adapter board; Figure 8 A schematic diagram of the structure of an embodiment of a multi-node server system provided by the present invention. DETAILED DESCRIPTION
[0019] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the embodiments of the present invention are further described in detail below in combination with specific embodiments and with reference to the accompanying drawings.
[0020] It should be noted that all expressions using "first" and "second" in the embodiments of the present invention are for distinguishing two non-identical entities with the same name or non-identical parameters. It can be seen that "first" and "second" are only for the convenience of expression and should not be understood as limitations on the embodiments of the present invention. The subsequent embodiments will not explain this one by one.
[0021] The schematic diagram of link failure in a traditional multi-node server system is as follows: Figure 1 As shown, the traditional multi-node server system includes two server nodes, each server node includes a board, and the boards are connected by three sections of high-speed interconnect cables, such as cable 1, cable 2 and cable 3, and each section of the cable is connected by an adapter. However, in the traditional multi-node server system, there is a lack of high-speed interconnect signal fault detection technology. When a link fails in the multi-node server system, it is difficult to accurately determine whether the fault point is located in the board, cable 1, adapter board 1, cable 2, adapter board 2 or cable 3. In this case, it is difficult for maintenance personnel to accurately identify the specific fault location and have to adopt two relatively inefficient solutions: one is to fully replace all cables and boards involved in the link, and the other is to replace the cables and boards in the link one by one to troubleshoot the problem. This leads to increased maintenance costs and maintenance time.
[0022] Based on the above objectives, a first aspect of an embodiment of the present invention provides a high-speed interconnect adapter board, which is applied to a multi-node server system, such as Figure 2 As shown, the high-speed interconnect adapter board includes: A plurality of connectors 10, each connector 10 is connected to a server node in the multi-node server system, and is used to receive and forward high-speed interconnection signals of the server node; A plurality of MUX (Multiplexer) chips 20, each MUX chip 20 is connected to a plurality of connectors 10, and is used to receive and forward high-speed interconnection signals between the plurality of connectors 10; A TDR (Time Domain Reflectometry) chip 30 is connected to a plurality of MUX chips 20 and is used to send a test signal to each MUX chip 20 and receive a reflected signal returned by the MUX chip 20 in response to a connector 10 receiving an abnormal signal sent by a server node, so as to locate a fault point in the multi-node server system based on the reflected signal.
[0023] In some embodiments, the MUX chip has the function of selecting one of the outputs from multiple input signals. It usually includes multiple input channels and a selector, which connects the corresponding input channel to the output according to the specified selection signal, while other input channels are disconnected. By using a control signal to control the MUX chip to select different input channels, the MUX chip can transmit a large amount of information on a few output lines.
[0024] In some embodiments, the TDR chip can detect faults through TDR technology, which is a method for efficiently measuring the propagation speed of electrical signals in cables or wires. This technology sends a short pulse signal to the cable and monitors the echo generated by the reflected signal inside the cable in real time, thereby accurately calculating the transmission characteristics of the electrical signal. TDR technology is widely used in cable fault diagnosis, cable length measurement, cable positioning, and cable quality assessment. The core principle of TDR technology is based on the propagation characteristics of electromagnetic waves in cables. When electromagnetic waves propagate in cables, they will encounter various changes in cable structures or characteristics, such as connectors, joints, and potential fault points. These changes will cause electromagnetic waves to be reflected and refracted. Therefore, the TDR chip sends a broadband pulse signal (i.e., a test signal) to the MUX chip, and then the MUX chip and connector forward the test signal to the cable. The TDR chip accurately records and analyzes the signals reflected from the inside of the cable (i.e., reflected signals). By monitoring parameters such as the arrival time, amplitude, and phase of these reflected signals, the transmission characteristics of the electrical signals in the cable, such as propagation speed, attenuation, impedance change, etc., can be inferred. By analyzing the position of the reflected signal, the fault point and fault type of the link in the multi-node server system can be quickly located.
[0025] In some embodiments, a board is fixed in the chassis of each server node, and the board includes a CPU chip. A high-speed interconnect cable is used inside the chassis to connect the board to a high-speed interconnect adapter board, and a high-speed interconnect cable is used outside the chassis to connect two server nodes through the high-speed interconnect adapter board, thereby forming a high-speed signal link in the form of CPU chip-internal high-speed interconnect cable-high-speed interconnect adapter card-external high-speed interconnect cable-high-speed interconnect adapter card-internal high-speed interconnect cable-CPU chip in the multi-node server system. Figure 3-7 As shown, the above links are used to realize the interconnection between server nodes or the interconnection with I / O nodes in a multi-node server system. The TDR chip is connected to the high-speed signal link through the MUX chip.
[0026] The present invention provides a high-speed interconnect adapter card with fault detection technology, which combines a TDR chip with a MUX chip, uses time domain reflection technology to detect faults of high-speed interconnect cables and board faults, and accurately locates the fault point of the high-speed interconnect signal in the server system. The MUX chip controls the transmission of the TDR chip test signal, effectively avoiding transmission interference with the high-speed interconnect signal, which not only meets the use requirements of high-speed interconnection scenarios between nodes in a multi-node server system, but also can accurately locate the fault point in the high-speed interconnect signal link.
[0027] In some embodiments, the high-speed interconnect adapter board of the present invention also includes a CPLD, which is respectively connected to the TDR chip 30, all MUX chips 20 and all connectors 10, and is used to send a control signal to each MUX chip in response to receiving an abnormal signal sent by the connector 10, so as to control each MUX chip to open a signal link with the TDR chip 30.
[0028] In some embodiments, Figure 3 The CPLD shown in the figure communicates with the TDR chip and all connectors through I2C (Inter-Integrated Circuit). The CPLD is used to control the MUX chip to open or close the signal link with the TRD chip. The multi-node server system determines the link status through in-band identification. When a high-speed link fails, the HOST CPU (i.e., host central processing unit) in the server node sends an abnormal signal to the CPLD to instruct the CPLD to control the MUX chip to open the signal link with the TDR chip through the SEL (Compute Express Link, high-speed interconnect technology) signal (i.e., control signal).
[0029] In some embodiments, the connector 10 includes a first connector and a second connector, and the MUX chip 20 includes a first MUX chip and a second MUX chip. The output end of the first connector is connected to the input end of the first MUX chip through a first input link, and is used to send a first high-speed interconnection signal to the first MUX chip. The output end of the second connector is connected to the input end of the second MUX chip through a second input link, and is used to send a second high-speed interconnection signal to the second MUX chip. The output end of the first MUX chip is connected to the input end of the second connector through a first output link, and is used to forward the first high-speed interconnection signal to the second connector. The output end of the second MUX chip is connected to the input end of the first connector through a second output link, and is used to forward the second high-speed interconnection signal to the first connector.
[0030] In some embodiments, the first MUX chip is further configured to: in response to receiving a control signal sent by the CPLD, close the first input link, and open the first signal link with the TDR chip to receive a test signal; forward the test signal to the second connector through the first output link, and in response to receiving a reflected signal corresponding to the test signal returned by the second connector, send a reflected signal to the TDR chip.
[0031] In some embodiments, the second MUX chip is further configured to: in response to receiving a control signal sent by the CPLD, close the second input link, and open the second signal link with the TDR chip to receive a test signal; forward the test signal to the first connector through the second output link, and in response to receiving a reflected signal corresponding to the test signal returned by the first connector, send a reflected signal to the TDR chip.
[0032] In some embodiments, the MUX chip has multiple signal input channels, such as Figure 3 As shown, the signal input channel of the first MUX chip includes a first input link and a first signal link, and the signal input channel of the second MUX chip includes a second input link and a second signal link. The first MUX chip and the second MUX chip respectively select corresponding input channels to connect to the first output link or the second output link according to the control signal sent by the CPLD.
[0033] In some embodiments, when the multi-node server system operates normally, that is, the high-speed interconnect signal transmission is normal, the first MUX chip selects the first input link to be connected to the first output link, and the first signal link is disconnected, and the second MUX chip selects the second input link to be connected to the second output link, and the second signal link is disconnected to prevent the test signal from interfering with the transmission of the high-speed interconnect signal.
[0034] In some embodiments, when the multi-node server system works abnormally, that is, the high-speed interconnect signal transmission is abnormal, the CPLD selects to send a control signal to the first MUX chip and / or the second MUX chip according to the server node that sends the abnormal signal, so as to control the first MUX chip and / or the second MUX chip to open or close the first signal link and / or the second signal link. Figure 4-7For example, when the CPU chip in board 1 recognizes that the link is abnormal, it sends an abnormal signal to the high-speed interconnect adapter board (i.e., adapter board 1) connected to it. The first connector in adapter board 1 receives the abnormal signal and forwards it to the CPLD. The CPLD in adapter board 1 responds to the abnormal signal and sends control signals to the first MUX chip and the second MUX chip respectively. At this time, the first MUX chip selects the first signal link to connect to the first output link according to the control signal, disconnects the first input link, and uses the TDR chip as the signal input source of the first MUX chip. The second MUX chip selects the second signal link to connect to the second output link according to the control signal, disconnects the second input link, and uses the TDR chip as the signal input source of the second MUX chip. The TDR chip sends test signals to the first MUX chip and the second MUX chip respectively (such as Figure 4-7 The incident signal is shown in Figure 2 to detect faults in the high-speed signal link. When the reflected signal returned from the first MUX chip to the TRD chip is abnormal, the fault point and fault type of cable 1 or board 1 can be located by analyzing the transmission characteristics of the reflected signal. When the reflected signal returned from the second MUX chip to the TRD chip is abnormal, the fault point and fault type of cable 2, cable 3 or board 2 can be located by analyzing the transmission characteristics of the reflected signal. The working process of adapter board 2 and board 2 is the same. Among them, the first high-speed interconnection signal and the second high-speed interconnection signal are high-speed interconnection signals transmitted in different directions.
[0035] In some embodiments, each connector 10 is configured to forward an abnormal signal to the CPLD in response to receiving an abnormal signal sent by the server node to which it is connected.
[0036] In some embodiments, the CPLD is configured to send high-speed interconnect signal transmission abnormality information to the TDR chip 30 in response to receiving the abnormal signal.
[0037] In some embodiments, the high-speed interconnect adapter board of the present invention further includes an integrated circuit board, and the TDR chip 30 is disposed on the integrated circuit board.
[0038] In some implementations, each connector 10 is connected to a server node or to other high-speed interconnect adapter boards other than the high-speed interconnect adapter board where the connector 10 is located through a high-speed cable.
[0039] The high-speed interconnect adapter board of the present invention solves the problem that multi-section high-speed interconnect signals in a multi-node server system cannot accurately locate the fault point, and realizes accurate maintenance and replacement of faulty cables or faulty boards, greatly improving maintenance efficiency and reducing maintenance costs.
[0040] Based on the same inventive concept, according to another aspect of the present invention, Figure 8As shown, an embodiment of the present invention further provides a multi-node server system 100, the multi-node server system 100 includes a plurality of server nodes 110 and a plurality of high-speed interconnect adapters as described above, each server node 110 further includes: The host central processor 111 is configured to send an abnormal signal to the high-speed interconnect adapter board to which it is connected in response to detecting abnormal information of high-speed interconnect signal transmission.
[0041] The multi-node server system of the present invention, through a high-speed interconnection adapter card with fault detection technology, not only meets the use requirements of high-speed interconnection scenarios between nodes of the multi-node server system, but also can accurately locate the fault point in the high-speed interconnection signal link, solves the problem that the multi-section high-speed interconnection signal in the multi-node server system cannot accurately locate the fault point, and realizes accurate maintenance and replacement of faulty cables or faulty boards in the multi-node server system, greatly improving maintenance efficiency and reducing maintenance costs.
[0042] Finally, it should be noted that a person of ordinary skill in the art can understand that all or part of the processes in the above-mentioned embodiments can be implemented by instructing the relevant hardware through a computer program, and the program can be stored in a computer-readable storage medium. When the program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, the storage medium of the program can be a disk, an optical disk, a read-only storage memory (ROM) or a random access memory (RAM), etc. The above-mentioned computer program embodiments can achieve the same or similar effects as the corresponding above-mentioned any method embodiments.
[0043] It will also be appreciated by those skilled in the art that various exemplary logic blocks, modules, circuits and algorithm steps described in conjunction with the disclosure herein can be implemented as electronic hardware, computer software or a combination of the two. In order to clearly illustrate this interchangeability of hardware and software, a general description has been given to the functions of various schematic components, blocks, modules, circuits and steps. Whether this function is implemented as software or hardware depends on specific applications and the design constraints imposed on the entire system. Those skilled in the art can implement the function in various ways for each specific application, but this implementation decision should not be interpreted as causing a departure from the disclosed scope of the embodiments of the present invention.
[0044] The above are exemplary embodiments disclosed in the present invention, but it should be noted that various changes and modifications may be made without departing from the scope of the embodiments disclosed in the present invention as defined in the claims. The functions, steps and / or actions of the method claims according to the disclosed embodiments described herein do not need to be performed in any particular order. The serial numbers of the embodiments disclosed in the above embodiments of the present invention are for description only and do not represent the advantages and disadvantages of the embodiments. In addition, although the elements disclosed in the embodiments of the present invention may be described or required in individual form, they may also be understood as multiple unless explicitly limited to the singular.
[0045] It should be understood that, as used herein, the singular forms "a", "an" are intended to include the plural forms as well, unless the context clearly supports an exception. It should also be understood that, as used herein, "and / or" refers to any and all possible combinations including one or more of the associated listed items.
[0046] A person skilled in the art should understand that the discussion of any of the above embodiments is only exemplary and is not intended to imply that the scope of the disclosure of the embodiments of the present invention (including the claims) is limited to these examples; under the concept of the embodiments of the present invention, the technical features in the above embodiments or different embodiments can also be combined, and there are many other changes in different aspects of the above embodiments of the present invention, which are not provided in detail for the sake of simplicity. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the embodiments of the present invention should be included in the protection scope of the embodiments of the present invention.
Claims
1. A high-speed interconnect adapter board, characterized in that: Applicable to multi-node server systems, including: A plurality of connectors, each of which is connected to a server node in the multi-node server system and is used to receive and forward a high-speed interconnection signal of the server node; A plurality of MUX chips, each of which is connected to a plurality of the connectors, and is used to receive and forward the high-speed interconnection signal between the plurality of the connectors; A TDR chip is connected to the plurality of MUX chips and is used for sending a test signal to each MUX chip and receiving a reflected signal returned by the MUX chip in response to the connector receiving an abnormal signal sent by the server node, so as to locate the fault point in the multi-node server system based on the reflected signal.
2. The high-speed interconnect adapter board according to claim 1, characterized in that: It also includes a CPLD, which is connected to the TDR chip, all the MUX chips and all the connectors respectively, and is used to send a control signal to each MUX chip in response to receiving an abnormal signal sent by the connector, so as to control each MUX chip to open a signal link with the TDR chip.
3. The high-speed interconnect adapter board according to claim 2, characterized in that: The connector includes a first connector and a second connector, the MUX chip includes a first MUX chip and a second MUX chip, The output end of the first connector is connected to the input end of the first MUX chip through a first input link, and is used to send a first high-speed interconnect signal to the first MUX chip. The output end of the second connector is connected to the input end of the second MUX chip through a second input link, and is used to send a second high-speed interconnect signal to the second MUX chip. The output end of the first MUX chip is connected to the input end of the second connector through a first output link, and is used to forward the first high-speed interconnect signal to the second connector. The output end of the second MUX chip is connected to the input end of the first connector through a second output link, and is used to forward the second high-speed interconnect signal to the first connector.
4. The high-speed interconnect adapter board according to claim 3, characterized in that: The first MUX chip is further configured to: In response to receiving the control signal sent by the CPLD, closing the first input link and opening the first signal link with the TDR chip to receive the test signal; The test signal is forwarded to the second connector via the first output link, and in response to receiving the reflection signal corresponding to the test signal returned by the second connector, the reflection signal is sent to the TDR chip.
5. The high-speed interconnect adapter board according to claim 3, characterized in that: The second MUX chip is further configured to: In response to receiving the control signal sent by the CPLD, closing the second input link and opening a second signal link with the TDR chip to receive the test signal; The test signal is forwarded to the first connector through the second output link, and in response to receiving the reflection signal corresponding to the test signal returned by the first connector, the reflection signal is sent to the TDR chip.
6. The high-speed interconnect adapter board according to claim 2, characterized in that: Each of the connectors is configured to forward the abnormal signal to the CPLD in response to receiving the abnormal signal sent by the server node to which it is connected.
7. The high-speed interconnect adapter board according to claim 6, characterized in that: The CPLD is configured to send the high-speed interconnect signal transmission abnormality information to the TDR chip in response to receiving the abnormal signal.
8. The high-speed interconnect adapter board according to claim 2, characterized in that: It also includes an integrated circuit board, and the TDR chip is arranged on the integrated circuit board.
9. The high-speed interconnect adapter board according to claim 1, characterized in that: Each of the connectors is connected to the server node or to other high-speed interconnect adapter boards except the high-speed interconnect adapter board where the connector itself is located through a high-speed cable.
10. A multi-node server system, characterized in that: The multi-node server system comprises a plurality of server nodes, and a plurality of high-speed interconnect adapters as claimed in any one of claims 1 to 9 connected between the server nodes, and each of the server nodes further comprises: The host central processor is configured to send an abnormal signal to the high-speed interconnect adapter board to which it is connected in response to detecting abnormal information of high-speed interconnect signal transmission.