Cross-hardware architecture operator adaptive generation method and device, equipment and medium

Abstract

The invention discloses a cross-hardware architecture operator adaptive generation method and device, equipment and a medium, and relates to the technical field of computers, and the method comprises the steps: extracting a first feature vector from operator description corresponding to an operator type of a to-be-generated operator; determining a weighted summation result of the target architecture configuration information and the first feature vector to obtain a first identifier, so as to screen a target calculation accelerator architecture adaptive network from each preset calculation accelerator architecture adaptive network corresponding to each calculation accelerator type; binarization is carried out on the first feature vector to obtain a second identifier, so that a target operator type adaptive network is screened from preset operator type adaptive networks corresponding to the operator types; and performing feature transformation on the first feature vector by using the target computing accelerator architecture adaptation network and the target operator type adaptation network, and generating an operator sequence of an operator to be generated based on a second feature vector and a third feature vector obtained after transformation. And the flexibility and simplicity of operator generation are improved.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a method, device, equipment and medium for adaptively generating operators across hardware architectures. Background Art

[0002] In modern high-performance computing architectures, the widespread use of heterogeneous systems reflects the diversity and complexity of computing needs. The optimal implementation of the same operator on different computing accelerators varies significantly due to different hardware architectures. Efficient operator implementation usually requires detailed adaptation and optimization.

[0003] At present, the automatic operator implementation methods mainly include the following: template-based generation method, rule-based generation method, and intermediate representation-based generation method. Among them, the template-based generation method realizes automatic generation by using predefined templates, the rule-based generation method improves the performance of operators by formulating different optimization rules, and the intermediate representation-based generation method realizes "write once, generate on multiple platforms" by using intermediate representation. These cross-hardware architecture operator adaptive generation methods have low flexibility and increase system complexity.

[0004] It can be seen that how to improve the flexibility and simplicity of operator generation is a problem that technical personnel in this field need to solve. Summary of the invention

[0005] The purpose of the embodiments of the present invention is to provide a method, device, equipment and medium for adaptively generating operators across hardware architectures, so as to improve the flexibility and simplicity of operator generation. The specific scheme is as follows:

[0006] In a first aspect, the present invention discloses a method for adaptively generating a cross-hardware architecture operator, comprising:

[0007] extracting a first eigenvector from an operator description corresponding to an operator type of the operator to be generated;

[0008] Determine a weighted summation result of the target architecture configuration information and the first feature vector, determine the binarized weighted summation result as a first identifier, and select a target computing accelerator architecture adaptation network identified as the first identifier from each preset computing accelerator architecture adaptation network; wherein the target architecture configuration information is the architecture configuration information of the target computing accelerator corresponding to the operator to be generated, and each of the preset computing accelerator architecture adaptation networks corresponds to each computing accelerator type respectively;

[0009] Binarizing the first feature vector to obtain a second identifier, and selecting a target operator type adaptation network identified as the second identifier from each preset operator type adaptation network; wherein each of the preset operator type adaptation networks corresponds to each operator type respectively;

[0010] The target computing accelerator architecture adaptation network and the target operator type adaptation network are used to perform feature transformation on the first feature vector respectively, and an operator sequence of the operator to be generated is generated based on the second feature vector and the third feature vector obtained after the transformation.

[0011] Optionally, before selecting the target computing accelerator architecture adaptation network identified as the first identifier from the preset computing accelerator architecture adaptation networks, the method further includes:

[0012] Collecting a first training set including computing accelerator architecture feature information and operator instances, and dividing the first training set into first sub-training sets according to computing accelerator types;

[0013] Constructing an initial computing accelerator adaptation network, and using each of the first sub-training sets to train the initial computing accelerator adaptation network respectively, so as to obtain a preset computing accelerator architecture adaptation network corresponding to each of the computing accelerator types;

[0014] The identifier of the corresponding preset computing accelerator architecture adaptation network is generated according to the architecture configuration information of each computing accelerator type.

[0015] Optionally, before selecting the target operator type adaptation network identified as the second identifier from the preset operator type adaptation networks, the method further includes:

[0016] Collecting a second training set including operator feature information and operator instances, and dividing the second training set into second sub-training sets according to each operator type;

[0017] Constructing an initial operator type adaptation network, and using each of the second sub-training sets to train the initial operator type adaptation network respectively, so as to obtain a preset operator type adaptation network corresponding to each of the operator types;

[0018] The identifier of the corresponding preset operator type architecture adaptation network is generated according to the characteristic information of each operator type.

[0019] Optionally, the using each of the first sub-training sets to respectively train the initial computing accelerator adaptation network to obtain a preset computing accelerator architecture adaptation network corresponding to each of the computing accelerator types, includes:

[0020] Based on a preset network parameter update algorithm and using each of the first sub-training sets, the initial computing accelerator adaptation network is trained respectively to update the weight of the initial computing accelerator adaptation network, and obtain a preset computing accelerator architecture adaptation network corresponding to each of the computing accelerator types; the preset network parameter update algorithm is any one of a back propagation algorithm, a gradient descent algorithm, and an adaptive moment estimation algorithm;

[0021] Correspondingly, the using of each of the second sub-training sets to respectively train the initial operator type adaptation network to obtain a preset operator type adaptation network corresponding to each of the operator types, includes:

[0022] Based on the preset network parameter update algorithm and using each of the second sub-training sets, the initial operator type adaptation network is trained respectively to update the weight of the initial operator type adaptation network, and a preset operator type adaptation network corresponding to each of the operator types is obtained.

[0023] Optionally, determining a weighted sum of the target architecture configuration information and the first feature vector, and determining the binarized weighted sum as the first identifier includes:

[0024] Determine a first weight coefficient of the target architecture configuration information of the to-be-generated operator and a second weight coefficient of the first feature vector;

[0025] Using the first weight coefficient and the second weight coefficient, respectively, to perform weighted summation on the target architecture configuration information and the first feature vector to obtain a weighted summation result;

[0026] Using a multi-layer fully connected network, nonlinearly transform the weighted sum result to obtain a first transformed result, and probabilistically process the first transformed result to obtain a first probabilistic result, and determine the first probabilistic result after binarization as a first identifier;

[0027] Accordingly, binarizing the first feature vector to obtain a second identifier includes:

[0028] Using the multi-layer fully connected network, a nonlinear transformation is performed on the first feature vector to obtain a second transformed result;

[0029] The second transformed result is subjected to probabilistic processing to obtain a second probabilistic result, and the second probabilistic result after binarization is determined as a second identifier.

[0030] Optionally, the generating the operator sequence of the to-be-generated operator based on the second eigenvector and the third eigenvector obtained after the transformation includes:

[0031] Fusing the second eigenvector with the third eigenvector to obtain a fused eigenvector, and using the fused eigenvector to generate an initial sequence of the operator to be generated;

[0032] Redundant elements in the initial sequence are removed to obtain a cleaned sequence, and the order of each element in the cleaned sequence is adjusted to obtain the operator sequence of the operator to be generated.

[0033] Optionally, the fusing the second feature vector with the third feature vector to obtain a fused feature vector includes:

[0034] Determine a first mean and a first variance of the second eigenvector and a second mean and a second variance of the third eigenvector;

[0035] Standardizing the second eigenvector using the first mean and the first variance to obtain a standardized second eigenvector, and standardizing the second eigenvector using the second mean and the second variance to obtain a standardized third eigenvector;

[0036] Obtaining a first product of the first variance and the standardized third eigenvector and a second product of the second variance and the standardized second eigenvector;

[0037] A first weight value is configured for a first sum value of the first product and the first mean, and a second weight value is configured for a second sum value of the second product and the second mean, and then the first sum value and the second sum value are weightedly calculated based on the first weight value and the second weight value to obtain a corresponding fused feature vector.

[0038] In a second aspect, the present invention discloses a device for adaptively generating a cross-hardware architecture operator, comprising:

[0039] A first feature acquisition module, used to extract a first feature vector from an operator description corresponding to an operator type of the operator to be generated;

[0040] A first network screening module is used to determine a weighted summation result of the target architecture configuration information and the first feature vector, determine the binarized weighted summation result as a first identifier, and screen out a target computing accelerator architecture adaptation network identified as the first identifier from each preset computing accelerator architecture adaptation network; wherein the target architecture configuration information is the architecture configuration information of the target computing accelerator corresponding to the operator to be generated, and each of the preset computing accelerator architecture adaptation networks corresponds to each computing accelerator type respectively;

[0041] A second network screening module, used for binarizing the first feature vector to obtain a second identifier, and screening out a target operator type adaptation network identified as the second identifier from each preset operator type adaptation network; wherein each of the preset operator type adaptation networks corresponds to each operator type respectively;

[0042] An operator sequence generation module is used to use the target computing accelerator architecture adaptation network and the target operator type adaptation network to perform feature transformation on the first feature vector respectively, and generate an operator sequence of the operator to be generated based on the second feature vector and the third feature vector obtained after the transformation.

[0043] In a third aspect, the present invention discloses an electronic device, comprising:

[0044] Memory, used to store computer programs;

[0045] A processor is used to execute the computer program to implement the steps of the above-disclosed cross-hardware architecture operator adaptive generation method.

[0046] In a fourth aspect, the present invention discloses a computer-readable storage medium for storing a computer program; wherein, when the computer program is executed by a processor, the steps of the aforementioned disclosed cross-hardware architecture operator adaptive generation method are implemented.

[0047] It can be seen that the present invention extracts a first eigenvector from an operator description corresponding to the operator type of the operator to be generated; determines a weighted summation result of the target architecture configuration information and the first eigenvector, and determines the binarized weighted summation result as a first identifier, and selects a target computing accelerator architecture adaptation network identified as the first identifier from each preset computing accelerator architecture adaptation network; wherein the target architecture configuration information is the architecture configuration information of the target computing accelerator corresponding to the operator to be generated, and each of the preset computing accelerator architecture adaptation networks corresponds to each computing accelerator type respectively; binarizes the first eigenvector to obtain a second identifier, and selects a target operator type adaptation network identified as the second identifier from each preset operator type adaptation network; wherein each of the preset operator type adaptation networks corresponds to each operator type respectively; uses the target computing accelerator architecture adaptation network and the target operator type adaptation network to perform feature transformation on the first eigenvector respectively, and generates an operator sequence of the operator to be generated based on the second eigenvector and the third eigenvector obtained after the transformation.

[0048] Beneficial effect: In the present invention, each preset computing accelerator architecture adaptation network corresponds to each computing accelerator type, each preset operator type adaptation network corresponds to each operator type, and the target architecture configuration information corresponds to the architecture configuration information of the target computing accelerator corresponding to the operator to be generated. Therefore, the target computing accelerator architecture adaptation network screened out from each preset computing accelerator architecture adaptation network using the target architecture configuration information corresponds to the target computing accelerator of the operator to be generated. Similarly, the operator description includes a description corresponding to the operator type of the operator to be generated. Then, the first eigenvector is extracted from the operator description of the operator to be generated, and the target operator type adaptation network screened out from each preset operator type adaptation network using the first eigenvector corresponds to the operator type of the operator to be generated. In this way, the second eigenvector output by the target computing accelerator architecture adaptation network and the third eigenvector output by the target operator type adaptation network are The characteristic vectors are respectively adapted to the target computing accelerator and operator type of the operator to be generated. Finally, the operator sequence of the operator to be generated obtained by fusing the second characteristic vector with the third characteristic vector can be adapted to the target computing accelerator and also satisfies the operator type of the operator to be generated. Therefore, the present invention can flexibly generate operator sequences even in the face of different computing accelerators and operator types. Moreover, because each preset computing accelerator architecture adaptation network corresponds to each computing accelerator type, and each preset operator type adaptation network corresponds to each operator type, that is to say, when there is a new computing accelerator or a new operator type, a new preset computing accelerator architecture adaptation network and a new preset operator type adaptation network can be added separately. There is no need to retrain the entire preset computing accelerator architecture adaptation network and the preset computing accelerator architecture adaptation network. The training difficulty is greatly reduced, thereby improving the simplicity of operator generation. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] In order to more clearly illustrate the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0050] Figure 1 A flow chart of a method for adaptively generating a cross-hardware architecture operator provided by an embodiment of the present invention;

[0051] Figure 2 A flow chart of a specific cross-hardware architecture operator adaptive generation method provided by an embodiment of the present invention;

[0052] Figure 3 A schematic diagram of a specific operator adaptive generation architecture provided by an embodiment of the present invention;

[0053] Figure 4A schematic diagram of the structure of a cross-hardware architecture operator adaptive generation device provided by an embodiment of the present invention;

[0054] Figure 5 A structural diagram of an electronic device provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0055] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0056] In modern high-performance computing architectures, the widespread use of heterogeneous systems reflects the diversity and complexity of computing needs. The optimal implementation of the same operator on different computing accelerators varies significantly due to different hardware architectures. Efficient operator implementation usually requires detailed adaptation and optimization.

[0057] At present, the automatic operator implementation methods mainly include the following: template-based generation method, rule-based generation method, and intermediate representation-based generation method. Among them, the template-based generation method realizes automatic generation by using predefined templates, the rule-based generation method improves the performance of operators by formulating different optimization rules, and the intermediate representation-based generation method realizes "write once, generate on multiple platforms" by using intermediate representation. These cross-hardware architecture operator adaptive generation methods have low flexibility and increase system complexity.

[0058] The terms "including" and "having" in the specification of the present invention and the above-mentioned drawings, as well as any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device including a series of steps or units is not limited to the listed steps or units, but may include steps or units that are not listed.

[0059] In order to enable those skilled in the art to better understand the solution of the present invention, the present invention is further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0060] Next, an operator generation solution provided by an embodiment of the present invention is introduced in detail. Figure 1 A method for adaptively generating a cross-hardware architecture operator provided in an embodiment of the present invention includes:

[0061] Step S11: extracting a first feature vector from an operator description corresponding to the operator type of the operator to be generated.

[0062] A first eigenvector is extracted from an operator description corresponding to the operator type of the operator to be generated, wherein the operator description includes not only a description corresponding to the operator type of the operator to be generated, but also a description related to the function, performance, and constraints of the operator to be generated.

[0063] The Transformer-Decoder base can be used to extract the first feature vector. The extracted first feature vector can be a feature vector semantically related to the operator to be generated. The Transformer-Decoder base is based on the Transformer-Decoder architecture and has a powerful model capability to generate high-quality operator implementations and optimization strategies. The Transformer-Decoder base can generate optimized code for specific applications and hardware by learning a large amount of operator data and hardware characteristics, thereby providing comprehensive support and efficient performance for the system.

[0064] Step S12: Determine a weighted sum of the target architecture configuration information and the first feature vector, determine the binarized weighted sum as a first identifier, and select a target computing accelerator architecture adaptation network identified as the first identifier from each preset computing accelerator architecture adaptation network; wherein the target architecture configuration information is the architecture configuration information of the target computing accelerator corresponding to the operator to be generated, and each of the preset computing accelerator architecture adaptation networks corresponds to each computing accelerator type, respectively.

[0065] In this embodiment, before selecting the target computing accelerator architecture adaptation network identified as the first identifier from each preset computing accelerator architecture adaptation network, it also includes: collecting a first training set containing computing accelerator architecture feature information and operator instances, and dividing the first training set into first sub-training sets according to each computing accelerator type; constructing an initial computing accelerator adaptation network, and using each of the first sub-training sets to train the initial computing accelerator adaptation network respectively to obtain a preset computing accelerator architecture adaptation network corresponding to each of the computing accelerator types; generating the identifier of the corresponding preset computing accelerator architecture adaptation network according to the architecture configuration information of each of the computing accelerator types. Before selecting the target computing accelerator architecture adaptation network identified as the first identifier from each preset computing accelerator architecture adaptation network, it is necessary to construct each preset computing accelerator architecture adaptation network corresponding to each computing accelerator type, and the construction process is as follows:

[0066] 1.1) Collecting training data sets: Collect a first training set containing computing accelerator architecture feature information and operator instances, and divide the first training set into first sub-training sets according to the types of computing accelerators; the types of computing accelerators include graphics processing unit (GPU), field programmable gate array (FPGA), application specific integrated circuit (ASIC), TPU (tensor processing unit), etc. The first training set is divided into a first sub-training set a corresponding to GPU, a first sub-training set b corresponding to FPGA, a first sub-training set c corresponding to ASIC, and a first sub-training set d corresponding to TPU;

[0067] 1.2) Constructing an initial computing accelerator adaptation network, which is a Transformer network, and using each first sub-training set to train the initial computing accelerator adaptation network respectively, so as to obtain a preset computing accelerator architecture adaptation network corresponding to each computing accelerator type; that is, using the first sub-training set a to train the initial computing accelerator adaptation network, a preset computing accelerator architecture adaptation network A is obtained, using the first sub-training set b to train the initial computing accelerator adaptation network, a preset computing accelerator architecture adaptation network B is obtained, using the first sub-training set c to train the initial computing accelerator adaptation network, a preset computing accelerator architecture adaptation network C is obtained, using the first sub-training set d to train the initial computing accelerator adaptation network, a preset computing accelerator architecture adaptation network D is obtained, in this way, different computing accelerators correspond to different preset computing accelerator architecture adaptation networks;

[0068] 1.3) Generate the identifier of the corresponding preset computing accelerator architecture adaptation network according to the architecture configuration information of each computing accelerator type, that is, perform eight-bit binary encoding according to the architecture configuration information of each computing accelerator type to obtain the identifier of the preset computing accelerator architecture adaptation network. The manufacturer will publish relevant documents for different computing accelerators, including the architecture configuration information. The architecture configuration information includes the storage hierarchy, power consumption, heat dissipation, external interface, data flow mode and other information of the corresponding computing accelerator.

[0069] Therefore, when there is a new computing accelerator e, it means that it is necessary to build a preset computing accelerator architecture adaptation network E corresponding to the new computing accelerator e. However, because each preset computing accelerator architecture adaptation network corresponds to a different computing accelerator, that is, the decoupling of the preset computing accelerator architecture adaptation network is realized in this embodiment, so that the scale and complexity of each preset computing accelerator architecture adaptation network are relatively small. Therefore, it is less difficult to build a new preset computing accelerator architecture adaptation network, and there is no need to train, adjust, etc. the already constructed preset computing accelerator architecture adaptation network. Compared with the undecoupled preset computing accelerator architecture adaptation network, the cost is lower and the efficiency is higher.

[0070] In this embodiment, the initial computing accelerator adaptation network is trained using each of the first sub-training sets to obtain a preset computing accelerator architecture adaptation network corresponding to each of the computing accelerator types, including: based on a preset network parameter update algorithm and using each of the first sub-training sets to train the initial computing accelerator adaptation network to update the weights of the initial computing accelerator adaptation network to obtain a preset computing accelerator architecture adaptation network corresponding to each of the computing accelerator types; the preset network parameter update algorithm is any one of a back propagation algorithm, a gradient descent algorithm, and an adaptive moment estimation algorithm.

[0071] During the training process of the computing accelerator adaptation network, the computing accelerator adaptation network is allowed to continuously learn the feature information in the first sub-training set, which includes both the relevant features of the generated operator sequence and the features related to the computing accelerator. During the learning process, the network parameters, i.e., the weights of the computing accelerator adaptation network, need to be updated, wherein the preset network parameter update algorithm can be specifically any one of the back propagation algorithm, the gradient descent algorithm, and the adaptive moment estimation algorithm, wherein the back propagation algorithm can simultaneously calculate the gradients of all weights in the network without calculating the partial derivatives of each weight separately. This batch calculation method greatly improves the calculation efficiency and facilitates the use of the parallel computing capabilities of modern computers, such as GPU acceleration, thereby further shortening the training time; the gradient descent algorithm allows the learning rate to be flexibly adjusted during the training process, and the size of the learning rate directly affects the convergence speed and stability of the algorithm. By adjusting the learning rate, the training speed can be accelerated and the training efficiency of the model can be improved while ensuring the convergence of the algorithm; the adaptive moment estimation algorithm is relatively robust to the selection of hyperparameters and is not sensitive to parameters such as the initial learning rate and exponential decay rate. This means that during the training process, even if the selection of hyperparameters is not optimal, the adaptive moment estimation algorithm can still ensure the stability and convergence of the training process to a certain extent.

[0072] During the training process of the computing accelerator adaptation network, the loss function (Loss) value of the current computing accelerator adaptation network can be calculated to determine whether the loss function value is less than a first preset threshold value. If so, it means that the convergence degree of the current computing accelerator adaptation network has met the requirements, so the training of the computing accelerator adaptation network can be stopped. The current iterative training number of the computing accelerator adaptation network can also be determined. If the current iterative training number is greater than a second preset threshold value, it means that the computing accelerator adaptation network has been fully trained and no further training is required, so the training of the computing accelerator adaptation network can be stopped.

[0073] In this embodiment, the determination of the weighted sum of the target architecture configuration information and the first eigenvector, and determining the binarized weighted sum result as the first identifier, includes: determining the first weight coefficient of the target architecture configuration information of the operator to be generated and the second weight coefficient of the first eigenvector; using the first weight coefficient and the second weight coefficient to perform weighted summation on the target architecture configuration information and the first eigenvector, respectively, to obtain a weighted summation result; using a multi-layer fully connected network to perform a nonlinear transformation on the weighted summation result to obtain a first transformed result, and performing probabilistic processing on the first transformed result to obtain a first probabilistic result, and determining the first probabilistic binarized result as the first identifier. Different preset computing accelerator architecture adaptation networks have corresponding identifiers. When selecting a target computing accelerator architecture adaptation network, it is necessary to first determine the identifier of the target computing accelerator architecture adaptation network. The formula for determining the identifier of the target computing accelerator architecture adaptation network is as follows:

[0074] ;

[0075] In the formula, represents the first eigenvector, Represents the target architecture configuration information, represents the first weight coefficient, represents the second weight coefficient, determines the first weight coefficient of the target architecture configuration information of the operator to be generated and the second weight coefficient of the first eigenvector, and uses the first weight coefficient and the second weight coefficient to perform weighted summation on the target architecture configuration information and the first eigenvector respectively to obtain the weighted summation result; MLP (Multi-Layer Perceptron) represents a multi-layer fully connected network, that is, a multi-layer fully connected network is used to perform a nonlinear transformation on the weighted summation result to obtain a first transformed result, and then a sigmoid activation function is used to probabilistically process the first transformed result to obtain a first probabilized result, and finally the first probabilized result after binarization is determined as the first identifier.

[0076] Step S13: binarizing the first feature vector to obtain a second identifier, and selecting a target operator type adaptation network identified as the second identifier from each preset operator type adaptation network; wherein each of the preset operator type adaptation networks corresponds to each operator type respectively.

[0077] In this embodiment, before selecting the target operator type adaptation network identified as the second identifier from each preset operator type adaptation network, it also includes: collecting a second training set containing operator feature information and operator instances, and dividing the second training set into second sub-training sets according to each operator type; constructing an initial operator type adaptation network, and using each of the second sub-training sets to train the initial operator type adaptation network respectively to obtain a preset operator type adaptation network corresponding to each of the operator types; generating the identifier of the corresponding preset operator type architecture adaptation network according to the feature information of each of the operator types. Before selecting the target operator type adaptation network identified as the second identifier from each of the preset operator type architecture adaptation networks, it is necessary to construct each preset operator type adaptation network corresponding to each operator type, and the construction process is as follows:

[0078] 2.1) Collecting a second training set including operator feature information and operator instances, and dividing the second training set into second sub-training sets according to operator types; operator types include element-by-element operation, broadcast operation, reduction operation, matrix operation operator, etc. After collecting the second training set including operator feature information and operator instances, the second training set is divided into second sub-training sets according to operator types such as element-by-element operation, broadcast operation, reduction operation, matrix operation operator, etc.;

[0079] 2.2) Constructing an initial operator type adaptation network, and using each second sub-training set to train the initial operator type adaptation network respectively, so as to obtain a preset operator type adaptation network corresponding to each operator type; the constructed initial operator type adaptation network adopts the Transformer architecture, and uses each second sub-training set to train the initial operator type adaptation network respectively, specifically, the preset operator type adaptation network corresponding to the element-by-element operation operator type, the preset operator type adaptation network corresponding to the broadcast operation operator type, the preset operator type adaptation network corresponding to the reduction operation operator type, and the preset operator type adaptation network corresponding to the matrix operation operator type can be obtained;

[0080] 2.3) Generate the identifier of the corresponding preset operator type architecture adaptation network according to the characteristic information of each operator type. The characteristic information may specifically include information such as computing logic, performance characteristics, and implementation methods, so that each preset operator type architecture adaptation network has a unique identifier.

[0081] It can be understood that when there is a new operator type, the initial operator type adaptation network can be trained using the operator feature information and operator instances of the operator type to obtain a preset operator type architecture adaptation network corresponding to the operator type. In other words, this embodiment realizes the decoupling of the operator type architecture adaptation network. Each operator type has a corresponding preset operator type architecture adaptation network, which also reduces the complexity of each preset operator type architecture adaptation network. Even if it is necessary to train the operator type architecture adaptation network corresponding to the new operator type, the training cost and difficulty are much smaller than training the non-decoupled operator type architecture adaptation network, which also reduces the difficulty of network maintenance.

[0082] In this embodiment, the use of each of the second sub-training sets to train the initial operator type adaptation network respectively to obtain the preset operator type adaptation network corresponding to each of the operator types includes: based on the preset network parameter update algorithm and using each of the second sub-training sets to train the initial operator type adaptation network respectively to update the weight of the initial operator type adaptation network to obtain the preset operator type adaptation network corresponding to each of the operator types. The preset network parameter update algorithm specifically includes any one of the back propagation algorithm, the gradient descent algorithm, and the adaptive moment estimation algorithm. The network parameter update method is determined according to the advantages of different network parameter update algorithms, so as to update the weight of the operator type adaptation network and obtain the preset operator type adaptation network corresponding to each of the operator types.

[0083] In this embodiment, the binarization of the first feature vector to obtain the second identifier includes: using the multi-layer fully connected network to perform a nonlinear transformation on the first feature vector to obtain a second transformed result; performing probabilistic processing on the second transformed result to obtain a second probabilistic result, and determining the second probabilistic result after binarization as the second identifier. The second identifier determination formula is specifically as follows:

[0084] ;

[0085] In the formula, represents the first eigenvector, MLP represents a multi-layer fully connected network, that is, the first eigenvector is nonlinearly transformed using the multi-layer fully connected network to obtain a second transformed result, and then the sigmoid activation function performs probabilistic processing on the second transformed result to obtain a second probabilistic result, and finally the second probabilistic result after binarization is determined as the second identifier.

[0086] Step S14: using the target computing accelerator architecture adaptation network and the target operator type adaptation network to perform feature transformation on the first feature vector respectively, and generating an operator sequence of the operator to be generated based on the second feature vector and the third feature vector obtained after the transformation.

[0087] After screening out the appropriate target computing accelerator architecture adaptation network and target operator type adaptation network, the target computing accelerator architecture adaptation network is used to perform feature transformation on the first eigenvector to obtain a second eigenvector related to the computing accelerator configuration, and the target operator type adaptation network is used to perform feature transformation on the first eigenvector to obtain a third eigenvector related to the operator type. The second eigenvector and the third eigenvector are fused to obtain a fused eigenvector, and then an operator sequence of the operator to be generated is generated based on the fused eigenvector. The generated operator sequence can be executed in the target computing accelerator to enable the target computing accelerator to complete the corresponding task. For example, GPU usually uses CUDA (Compute Unified Device Architecture) or OpenCL (Open Computing Language), and GPU is often used for graphic design, animation production, video editing and other tasks. FPGA uses HDL (High-Level Design Language) or HLS (High-Level Synthesis), and FPGA is suitable for audio processing, video encoding and decoding, radar signal processing and other tasks. ASIC is often used as the core processing unit of routers, switches, base stations and other equipment. The programming of ASIC usually involves a dedicated hardware description language, and the adaptation and optimization requirements for different programming models are also different.

[0088] It can be seen that the present invention extracts a first eigenvector from an operator description corresponding to the operator type of the operator to be generated; determines a weighted summation result of the target architecture configuration information and the first eigenvector, and determines the binarized weighted summation result as a first identifier, and selects a target computing accelerator architecture adaptation network identified as the first identifier from each preset computing accelerator architecture adaptation network; wherein the target architecture configuration information is the architecture configuration information of the target computing accelerator corresponding to the operator to be generated, and each of the preset computing accelerator architecture adaptation networks corresponds to each computing accelerator type respectively; binarizes the first eigenvector to obtain a second identifier, and selects a target operator type adaptation network identified as the second identifier from each preset operator type adaptation network; wherein each of the preset operator type adaptation networks corresponds to each operator type respectively; uses the target computing accelerator architecture adaptation network and the target operator type adaptation network to perform feature transformation on the first eigenvector respectively, and generates an operator sequence of the operator to be generated based on the second eigenvector and the third eigenvector obtained after the transformation.

[0089] Beneficial effect: In the present invention, each preset computing accelerator architecture adaptation network corresponds to each computing accelerator type, each preset operator type adaptation network corresponds to each operator type, and the target architecture configuration information corresponds to the architecture configuration information of the target computing accelerator corresponding to the operator to be generated. Therefore, the target computing accelerator architecture adaptation network screened out from each preset computing accelerator architecture adaptation network using the target architecture configuration information corresponds to the target computing accelerator of the operator to be generated. Similarly, the operator description includes a description corresponding to the operator type of the operator to be generated. Then, the first eigenvector is extracted from the operator description of the operator to be generated, and the target operator type adaptation network screened out from each preset operator type adaptation network using the first eigenvector corresponds to the operator type of the operator to be generated. In this way, the second eigenvector output by the target computing accelerator architecture adaptation network and the third eigenvector output by the target operator type adaptation network are The characteristic vectors are respectively adapted to the target computing accelerator and operator type of the operator to be generated. Finally, the operator sequence of the operator to be generated obtained by fusing the second characteristic vector with the third characteristic vector can be adapted to the target computing accelerator and also satisfies the operator type of the operator to be generated. Therefore, the present invention can flexibly generate operator sequences even in the face of different computing accelerators and operator types. Moreover, because each preset computing accelerator architecture adaptation network corresponds to each computing accelerator type, and each preset operator type adaptation network corresponds to each operator type, that is to say, when there is a new computing accelerator or a new operator type, a new preset computing accelerator architecture adaptation network and a new preset operator type adaptation network can be added separately. There is no need to retrain the entire preset computing accelerator architecture adaptation network and the preset computing accelerator architecture adaptation network. The training difficulty is greatly reduced, thereby improving the simplicity of operator generation.

[0090] See also Figure 2 The embodiment of the present invention discloses a specific cross-hardware architecture operator adaptive generation method. Compared with the previous embodiment, this embodiment further explains and optimizes the technical solution. It includes:

[0091] Step S21: extracting a first feature vector from an operator description corresponding to the operator type of the operator to be generated.

[0092] For example Figure 3 A specific schematic diagram of an operator adaptive generation architecture is shown, where the operator adaptive generation architecture includes a Transformer-Decoder base, an architecture gating unit, multiple chip architecture adaptation modules (i.e., a preset computing accelerator architecture adaptation network), multiple operator type adaptation modules (i.e., a preset operator type adaptation network), an operator gating unit, and a fusion module.

[0093] The Transformer-Decoder base extracts the first eigenvector from the operator description corresponding to the operator type to be generated. The Transformer-Decoder base is the core component of the entire system and is responsible for providing the main functions of operator generation and optimization. As the part with the largest number of parameters among all modules, it is based on the Transformer-Decoder architecture and has a strong model capability to generate high-quality operator implementations and optimization strategies. This part can generate optimized codes for specific applications and hardware by learning a large amount of operator data and hardware characteristics, thus providing comprehensive support and efficient performance for the system.

[0094] Step S22: Determine a weighted sum of the target architecture configuration information and the first feature vector, determine the binarized weighted sum as a first identifier, and select a target computing accelerator architecture adaptation network identified as the first identifier from each preset computing accelerator architecture adaptation network; wherein the target architecture configuration information is the architecture configuration information of the target computing accelerator corresponding to the operator to be generated, and each of the preset computing accelerator architecture adaptation networks corresponds to each computing accelerator type, respectively.

[0095] The chip architecture adaptation related parts mainly include the chip architecture adaptation module and the architecture gating unit. These two modules work closely together to ensure that the generated operators can be optimized for different acceleration chips. The core task of the chip architecture adaptation module is to map the intermediate results generated by the Transformer-Decoder base to outputs suitable for a specific chip architecture based on the characteristics of different acceleration chips. This module can identify the computing and storage architectures of different chips, so that when generating operators, special optimization strategies can be applied to fully utilize the unique advantages of various chips.

[0096] The chip architecture adaptation module adopts a Transformer-based network, mainly for two key considerations. First, this network structure does not need to retrain the entire chip architecture adaptation module when facing minor changes in the architecture, but can be fine-tuned in a way similar to LoRA (Low-Rank Adaptation). This method not only reduces the computational overhead, but also enhances the versatility of the adaptation module, enabling it to respond more flexibly to different hardware changes. Secondly, the Transformer-based design can significantly reduce the number of chip architecture adaptation modules required, thereby simplifying the complexity of the system and improving overall efficiency.

[0097] The architecture gating unit is responsible for activating the corresponding chip architecture adaptation module according to the type of acceleration chip currently in use. This means that when the system recognizes different types of hardware platforms, the architecture gating unit will adaptively select the most appropriate architecture adaptation strategy to ensure that the operator generation process can match the hardware characteristics and achieve optimal performance.

[0098] Step S23: binarizing the first feature vector to obtain a second identifier, and selecting a target operator type adaptation network identified as the second identifier from each preset operator type adaptation network; wherein each of the preset operator type adaptation networks corresponds to each operator type, respectively.

[0099] The operator type-related part mainly involves the operator type adaptation module and the operator gating unit. These modules are designed to handle different categories of operator operations and ensure that each operator type can be optimized. The operator type adaptation module provides specific mapping strategies for different operator types, converting the output of the Transformer-Decoder base into a result suitable for the operator type. Through this modular design, the system can automatically select the most appropriate calculation path and optimization strategy according to the different operator categories, ensuring that each operator achieves the best performance during execution.

[0100] The operator gating unit is used to activate the appropriate operator type adaptation module. According to the type of operator currently being processed, the operator gating unit will select the corresponding adaptation module to apply the most appropriate data movement strategy and computing optimization strategy. This dynamic selection mechanism based on operator type can significantly improve the system's adaptability to different tasks, allowing the system to always remain efficient when processing a variety of operator operations.

[0101] Step S24: using the target computing accelerator architecture adaptation network and the target operator type adaptation network to perform feature transformation on the first feature vector respectively to obtain a second feature vector and a third feature vector.

[0102] Step S25: Fusing the second eigenvector with the third eigenvector to obtain a fused eigenvector, and using the fused eigenvector to generate an initial sequence of the operator to be generated; removing redundant elements in the initial sequence to obtain a cleaned sequence, and adjusting the order of each element in the cleaned sequence to obtain an operator sequence of the operator to be generated.

[0103] In this embodiment, the fusing of the second eigenvector and the third eigenvector to obtain a fused eigenvector includes: determining a first mean and a first variance of the second eigenvector and a second mean and a second variance of the third eigenvector; standardizing the second eigenvector using the first mean and the first variance to obtain a standardized second eigenvector, and standardizing the second eigenvector using the second mean and the second variance to obtain a standardized third eigenvector; obtaining a first product of the first variance and the standardized third eigenvector and a second product of the second variance and the standardized second eigenvector; configuring a first weight value for a first sum of the first product and the first mean, and configuring a second weight value for a second sum of the second product and the second mean, and then performing weighted calculation on the first sum and the second sum based on the first weight value and the second weight value to obtain a corresponding fused eigenvector.

[0104] The role of the fusion module is to match different types of operators with different acceleration chip architectures to achieve optimal performance. It contains two key components: feature fusion component and feature mapping component. The feature fusion component combines operator characteristics and chip architecture information to generate the optimal computing strategy. Feature fusion uses the following formula:

[0105] ;

[0106] In the formula, X represents the second eigenvector, Y represents the third eigenvector, represents the variance, μ represents the mean, so the fusion process is as follows:

[0107] 3.1) determining a first mean and a first variance of the second eigenvector and a second mean and a second variance of the third eigenvector;

[0108] 3.2) Using the first mean and the first variance to normalize the second eigenvector to obtain a standardized second eigenvector, as shown below:

[0109] ;

[0110] The second eigenvector is standardized by using the second mean and the second variance to obtain a standardized third eigenvector, as shown below:

[0111] ;

[0112] 3.4) Obtain a first product of the first variance and the standardized third eigenvector and a second product of the second variance and the standardized second eigenvector; configure a first weight value for a first sum of the first product and the first mean , and configure a second weight value for the second sum of the second product and the second mean , and then weighted calculation is performed on the first sum value and the second sum value based on the first weight value and the second weight value to obtain the corresponding fused feature vector.

[0113] In this way, the obtained fused feature vector can be adapted to the target computing accelerator and also meet the operator type of the operator to be generated. Therefore, the present invention can flexibly generate operator sequences even in the face of different computing accelerators and operator types.

[0114] Furthermore, the feature mapping component uses the fused feature vector to generate an initial sequence of operators to be generated, and then identifies and removes redundant elements in the sequence, removes the redundant elements in the initial sequence to obtain a cleaned sequence, thereby generating a streamlined sequence, and then optimizes and reorganizes the order of elements in the streamlined sequence to finally form an operator sequence of operators to be generated for subsequent operations.

[0115] It should be noted that, in this embodiment, the cross-hardware architecture operator adaptive generation architecture can be a large pre-trained model, and training data is collected for training before actual application. The model is trained on a large-scale operator class data set. The purpose of this process is to allow the model to learn common operator features and patterns, thereby laying a solid foundation for the subsequent fine-tuning stage. In the pre-training stage, all parameters of the model will be updated to ensure its wide adaptability to various operator types and chip architectures. After the pre-training stage, there is a fine-tuning stage, and the model will be adjusted more finely according to specific application requirements. In this stage, only the parameters of the chip architecture adaptation module and the operator type adaptation module will be updated in sequence, while the parameters of other parts remain frozen. This strategy helps to retain the common features learned in the pre-training process, and at the same time, it is optimized according to specific hardware requirements. That is to say, when there are new computing accelerators and new operator types, a new preset computing accelerator architecture adaptation network and a new preset operator type adaptation network can be added separately, and there is no need to retrain the entire preset computing accelerator architecture adaptation network and the preset computing accelerator architecture adaptation network.

[0116] It can be seen that the present application can effectively adapt to a variety of acceleration chips, such as GPU, FPGA and TPU, solve the problem of hardware diversity, and ensure the best performance on different platforms, with strong cross-platform adaptability; by optimizing for specific hardware architectures, the execution efficiency of operators is improved, overcoming the complexity of traditional manual optimization; automated adjustment reduces manual writing and adjustment for each platform, reducing the complexity and cost of development and maintenance; it can quickly respond to the rapid progress of acceleration chip technology, solving the challenge that traditional optimization methods are difficult to keep up with hardware evolution; automatically adjusting operator implementations to meet the latest needs, improving the adaptability of operators in different scenarios; ensuring the performance consistency of operators on various hardware platforms, and improving the reliability and stability of cross-platform applications.

[0117] Figure 4 A schematic diagram of the structure of a cross-hardware architecture operator adaptive generation device provided by an embodiment of the present invention includes:

[0118] A first feature acquisition module 11, used to extract a first feature vector from an operator description corresponding to an operator type of an operator to be generated;

[0119] The first network screening module 12 is used to determine the weighted sum of the target architecture configuration information and the first feature vector, determine the binarized weighted sum as a first identifier, and screen out the target computing accelerator architecture adaptation network identified as the first identifier from each preset computing accelerator architecture adaptation network; wherein the target architecture configuration information is the architecture configuration information of the target computing accelerator corresponding to the operator to be generated, and each of the preset computing accelerator architecture adaptation networks corresponds to each computing accelerator type respectively;

[0120] The second network screening module 13 is used to binarize the first feature vector to obtain a second identifier, and screen out a target operator type adaptation network identified as the second identifier from each preset operator type adaptation network; wherein each of the preset operator type adaptation networks corresponds to each operator type respectively;

[0121] The operator sequence generation module 14 is used to use the target computing accelerator architecture adaptation network and the target operator type adaptation network to perform feature transformation on the first feature vector respectively, and generate the operator sequence of the operator to be generated based on the second feature vector and the third feature vector obtained after the transformation.

[0122] It can be seen that the present invention extracts a first eigenvector from an operator description corresponding to the operator type of the operator to be generated; determines a weighted summation result of the target architecture configuration information and the first eigenvector, and determines the binarized weighted summation result as a first identifier, and selects a target computing accelerator architecture adaptation network identified as the first identifier from each preset computing accelerator architecture adaptation network; wherein the target architecture configuration information is the architecture configuration information of the target computing accelerator corresponding to the operator to be generated, and each of the preset computing accelerator architecture adaptation networks corresponds to each computing accelerator type respectively; binarizes the first eigenvector to obtain a second identifier, and selects a target operator type adaptation network identified as the second identifier from each preset operator type adaptation network; wherein each of the preset operator type adaptation networks corresponds to each operator type respectively; uses the target computing accelerator architecture adaptation network and the target operator type adaptation network to perform feature transformation on the first eigenvector respectively, and generates an operator sequence of the operator to be generated based on the second eigenvector and the third eigenvector obtained after the transformation.

[0123] Beneficial effect: In the present invention, each preset computing accelerator architecture adaptation network corresponds to each computing accelerator type, each preset operator type adaptation network corresponds to each operator type, and the target architecture configuration information corresponds to the architecture configuration information of the target computing accelerator corresponding to the operator to be generated. Therefore, the target computing accelerator architecture adaptation network screened out from each preset computing accelerator architecture adaptation network using the target architecture configuration information corresponds to the target computing accelerator of the operator to be generated. Similarly, the operator description includes a description corresponding to the operator type of the operator to be generated. Then, the first eigenvector is extracted from the operator description of the operator to be generated, and the target operator type adaptation network screened out from each preset operator type adaptation network using the first eigenvector corresponds to the operator type of the operator to be generated. In this way, the second eigenvector output by the target computing accelerator architecture adaptation network and the third eigenvector output by the target operator type adaptation network are The characteristic vectors are respectively adapted to the target computing accelerator and operator type of the operator to be generated. Finally, the operator sequence of the operator to be generated obtained by fusing the second characteristic vector with the third characteristic vector can be adapted to the target computing accelerator and also satisfies the operator type of the operator to be generated. Therefore, the present invention can flexibly generate operator sequences even in the face of different computing accelerators and operator types. Moreover, because each preset computing accelerator architecture adaptation network corresponds to each computing accelerator type, and each preset operator type adaptation network corresponds to each operator type, that is to say, when there is a new computing accelerator or a new operator type, a new preset computing accelerator architecture adaptation network and a new preset operator type adaptation network can be added separately. There is no need to retrain the entire preset computing accelerator architecture adaptation network and the preset computing accelerator architecture adaptation network. The training difficulty is greatly reduced, thereby improving the simplicity of operator generation.

[0124] Furthermore, the present application also discloses an electronic device. Figure 5 It is a structural diagram of an electronic device according to an exemplary embodiment, and the content in the figure cannot be regarded as any limitation on the scope of use of this application. The electronic device may specifically include: at least one processor 21, at least one memory 22, a power supply 23, a communication interface 24, an input and output interface 25 and a communication bus 26. Among them, the memory 22 is used to store a computer program, and the computer program is loaded and executed by the processor 21 to implement the relevant steps in the cross-hardware architecture operator adaptive generation method disclosed in any of the aforementioned embodiments. In addition, the electronic device in this embodiment may specifically be an electronic computer.

[0125] In this embodiment, the power supply 23 is used to provide working voltage for each hardware device on the electronic device; the communication interface 24 can create a data transmission channel between the electronic device and the external device, and the communication protocol it follows is any communication protocol that can be applied to the technical solution of the present application, and is not specifically limited here; the input and output interface 25 is used to obtain external input data or output data to the outside world, and its specific interface type can be selected according to specific application needs and is not specifically limited here.

[0126] In addition, the memory 22, as a carrier for storing resources, can be a read-only memory, a random access memory, a disk or an optical disk, etc. The resources stored thereon can include an operating system 221, a computer program 222, etc., and the storage method can be temporary storage or permanent storage.

[0127] The operating system 221 is used to manage and control various hardware devices on the electronic device and the computer program 222, which can be Windows Server, Netware, Unix, Linux, etc. In addition to including a computer program that can be used to complete the cross-hardware architecture operator adaptive generation method performed by the electronic device disclosed in any of the aforementioned embodiments, the computer program 222 can further include a computer program that can be used to complete other specific tasks.

[0128] Furthermore, the present application also discloses a computer-readable storage medium for storing a computer program; wherein, when the computer program is executed by a processor, the above-disclosed cross-hardware architecture operator adaptive generation method is implemented. For the specific steps of the method, reference can be made to the corresponding contents disclosed in the above-disclosed embodiments, and no further description will be given here.

[0129] In this specification, each embodiment is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part.

[0130] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in the above description according to function. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0131] The steps of the method or algorithm described in conjunction with the embodiments disclosed herein may be implemented directly using hardware, a software module executed by a processor, or a combination of the two. The software module may be placed in a random access memory (RAM), a memory, a read-only memory (ROM), an electrically programmable ROM, an electrically erasable programmable ROM, a register, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.

[0132] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0133] The technical solution provided by the present application is introduced in detail above. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for general technicians in this field, according to the idea of ​​the present application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A method for adaptively generating operators across hardware architectures, characterized in that: include: extracting a first eigenvector from an operator description corresponding to an operator type of the operator to be generated; Determine a weighted summation result of the target architecture configuration information and the first feature vector, determine the binarized weighted summation result as a first identifier, and select a target computing accelerator architecture adaptation network identified as the first identifier from each preset computing accelerator architecture adaptation network; wherein the target architecture configuration information is the architecture configuration information of the target computing accelerator corresponding to the operator to be generated, and each of the preset computing accelerator architecture adaptation networks corresponds to each computing accelerator type respectively; Binarizing the first feature vector to obtain a second identifier, and selecting a target operator type adaptation network identified as the second identifier from each preset operator type adaptation network; wherein each of the preset operator type adaptation networks corresponds to each operator type respectively; The target computing accelerator architecture adaptation network and the target operator type adaptation network are used to perform feature transformation on the first feature vector respectively, and an operator sequence of the operator to be generated is generated based on the second feature vector and the third feature vector obtained after the transformation.

2. The cross-hardware architecture operator adaptive generation method according to claim 1, characterized in that: Before selecting the target computing accelerator architecture adaptation network identified as the first identifier from the preset computing accelerator architecture adaptation networks, the method further includes: Collecting a first training set including computing accelerator architecture feature information and operator instances, and dividing the first training set into first sub-training sets according to computing accelerator types; Constructing an initial computing accelerator adaptation network, and using each of the first sub-training sets to train the initial computing accelerator adaptation network respectively, so as to obtain a preset computing accelerator architecture adaptation network corresponding to each of the computing accelerator types; The identifier of the corresponding preset computing accelerator architecture adaptation network is generated according to the architecture configuration information of each computing accelerator type.

3. The cross-hardware architecture operator adaptive generation method according to claim 2, characterized in that: Before selecting the target operator type adaptation network identified as the second identifier from the preset operator type adaptation networks, the method further includes: Collecting a second training set including operator feature information and operator instances, and dividing the second training set into second sub-training sets according to each operator type; Constructing an initial operator type adaptation network, and using each of the second sub-training sets to train the initial operator type adaptation network respectively, so as to obtain a preset operator type adaptation network corresponding to each of the operator types; The identifier of the corresponding preset operator type architecture adaptation network is generated according to the characteristic information of each operator type.

4. The cross-hardware architecture operator adaptive generation method according to claim 3, characterized in that: The using each of the first sub-training sets to respectively train the initial computing accelerator adaptation network to obtain a preset computing accelerator architecture adaptation network corresponding to each of the computing accelerator types, includes: Based on a preset network parameter update algorithm and using each of the first sub-training sets, the initial computing accelerator adaptation network is trained respectively to update the weight of the initial computing accelerator adaptation network, and obtain a preset computing accelerator architecture adaptation network corresponding to each of the computing accelerator types; the preset network parameter update algorithm is any one of a back propagation algorithm, a gradient descent algorithm, and an adaptive moment estimation algorithm; Correspondingly, the using of each of the second sub-training sets to respectively train the initial operator type adaptation network to obtain a preset operator type adaptation network corresponding to each of the operator types, includes: Based on the preset network parameter update algorithm and using each of the second sub-training sets, the initial operator type adaptation network is trained respectively to update the weight of the initial operator type adaptation network, and a preset operator type adaptation network corresponding to each of the operator types is obtained.

5. The cross-hardware architecture operator adaptive generation method according to any one of claims 1 to 4, characterized in that: The step of determining a weighted sum of the target architecture configuration information and the first feature vector, and determining the binarized weighted sum as a first identifier, includes: Determine a first weight coefficient of the target architecture configuration information of the to-be-generated operator and a second weight coefficient of the first feature vector; Using the first weight coefficient and the second weight coefficient, respectively, to perform weighted summation on the target architecture configuration information and the first feature vector to obtain a weighted summation result; Using a multi-layer fully connected network, nonlinearly transform the weighted sum result to obtain a first transformed result, and probabilistically process the first transformed result to obtain a first probabilistic result, and determine the first probabilistic result after binarization as a first identifier; Accordingly, binarizing the first feature vector to obtain a second identifier includes: Using the multi-layer fully connected network, a nonlinear transformation is performed on the first feature vector to obtain a second transformed result; The second transformed result is subjected to probabilistic processing to obtain a second probabilistic result, and the second probabilistic result after binarization is determined as a second identifier.

6. The cross-hardware architecture operator adaptive generation method according to claim 1, characterized in that: The generating the operator sequence of the to-be-generated operator based on the second eigenvector and the third eigenvector obtained after the transformation includes: Fusing the second eigenvector with the third eigenvector to obtain a fused eigenvector, and using the fused eigenvector to generate an initial sequence of the operator to be generated; Redundant elements in the initial sequence are removed to obtain a cleaned sequence, and the order of each element in the cleaned sequence is adjusted to obtain the operator sequence of the operator to be generated.

7. The cross-hardware architecture operator adaptive generation method according to claim 6, characterized in that: The step of fusing the second feature vector with the third feature vector to obtain a fused feature vector includes: Determine a first mean and a first variance of the second eigenvector and a second mean and a second variance of the third eigenvector; Standardizing the second eigenvector using the first mean and the first variance to obtain a standardized second eigenvector, and standardizing the second eigenvector using the second mean and the second variance to obtain a standardized third eigenvector; Obtaining a first product of the first variance and the standardized third eigenvector and a second product of the second variance and the standardized second eigenvector; A first weight value is configured for a first sum value of the first product and the first mean, and a second weight value is configured for a second sum value of the second product and the second mean, and then the first sum value and the second sum value are weightedly calculated based on the first weight value and the second weight value to obtain a corresponding fused feature vector.

8. A cross-hardware architecture operator adaptive generation device, characterized in that: include: A first feature acquisition module, used to extract a first feature vector from an operator description corresponding to an operator type of the operator to be generated; A first network screening module is used to determine a weighted summation result of the target architecture configuration information and the first feature vector, determine the binarized weighted summation result as a first identifier, and screen out a target computing accelerator architecture adaptation network identified as the first identifier from each preset computing accelerator architecture adaptation network; wherein the target architecture configuration information is the architecture configuration information of the target computing accelerator corresponding to the operator to be generated, and each of the preset computing accelerator architecture adaptation networks corresponds to each computing accelerator type respectively; A second network screening module, used for binarizing the first feature vector to obtain a second identifier, and screening out a target operator type adaptation network identified as the second identifier from each preset operator type adaptation network; wherein each of the preset operator type adaptation networks corresponds to each operator type respectively; An operator sequence generation module is used to use the target computing accelerator architecture adaptation network and the target operator type adaptation network to perform feature transformation on the first feature vector respectively, and generate an operator sequence of the operator to be generated based on the second feature vector and the third feature vector obtained after the transformation.

9. An electronic device, characterized in that: include: Memory for storing computer programs; A processor, configured to execute the computer program to implement the steps of the cross-hardware architecture operator adaptive generation method as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the cross-hardware architecture operator adaptive generation method as claimed in any one of claims 1 to 7 are implemented.

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