Design method and system of solar system marginal on-orbit image recognition equipment

Abstract

The invention discloses a design method and system of solar system marginal on-orbit image recognition equipment, and relates to the technical field of solar system marginal detection. The method comprises the following steps of: analyzing a solar system imaging detection type load demand, and determining a load type; and according to the determined load type, interface circuit design of the on-orbit image recognition equipment is carried out for realizing acquisition of image information, and specifically, the interface circuit mainly comprises a load high-speed interface circuit design, a main processor and plug-in storage circuit design and a monitoring circuit design. According to the method, obtaining of an on-orbit image in a solar system marginal detection task is taken as a target, load configuration of the solar system marginal detection task is analyzed, camera loads compatible with various interface types are designed, a hardware platform is provided for obtaining high-value image multi-source information fusion processing, redundant and online configurable hardware design is adopted, and the method is suitable for large-scale popularization and application. The reliability of the in-orbit image recognition equipment is improved, and the single event upset resistance of a single machine is enhanced.

Description

Technical Field

[0001] The present invention relates to the field of solar system edge detection technology, and specifically to a design method for an on-orbit image recognition device for the solar system edge. Background Art

[0002] The solar system edge detection is a scientific exploration activity carried out at the edge of the heliosphere, about 80-150AU (AU is an astronomical unit, 1AU refers to the distance from the earth to the sun, about 150 million kilometers) from the sun. It is the farthest area controlled by the solar wind and the edge of the solar system is detected. Major scientific discoveries can be made in the origin and evolution of star systems, the composition and characteristics of solar system matter, and the dynamic process of solar wind in the heliosphere. Astronomical phenomena carry rich information about celestial bodies themselves and the evolution of the universe. The detection and research of astronomical phenomena are of extremely important scientific value. The radiation peaks of astronomical phenomena are mostly in the high-energy band. Therefore, space-based detection is relatively more suitable for in-orbit observation of astronomical phenomena due to the influence of the earth's atmosphere.

[0003] However, the exploration of the edge of the solar system has the characteristics of extremely long flight distance, extremely low communication rate, and extremely long time in orbit. Due to the limitation of the communication link bandwidth, the engineering cost of transmitting a large number of images taken by the camera back to the ground is high. Therefore, in order to identify valuable images and improve the ability of autonomous intelligent scientific discovery, it is necessary to carry out research on on-orbit image processing. To this end, we propose a design method and system for on-orbit image recognition equipment at the edge of the solar system. Summary of the invention

[0004] The purpose of the present invention is to provide a design method for an on-orbit image recognition device at the edge of the solar system to solve the problems raised in the above-mentioned background technology.

[0005] To achieve the above object, the present invention provides the following technical solution: a design method for an on-orbit image recognition device for the edge of the solar system, comprising the following steps:

[0006] Analyze the payload requirements for solar system imaging and detection and determine the payload type;

[0007] According to the determined payload type, the interface circuit design of the on-orbit image recognition equipment is carried out to realize the collection of image information. Specifically, the interface circuit mainly includes the payload high-speed interface circuit design, the main processor and external storage circuit design, the monitoring circuit design, the communication interface circuit design and the redundancy circuit design;

[0008] Design on-orbit image information processing circuits to realize image information processing, including main and auxiliary processing boards, external storage circuit design, and configuration circuit design;

[0009] The on-orbit image backplane circuit is designed to realize information interconnection between the interface circuit and the image information processing circuit.

[0010] Furthermore, the solar system imaging detection payload types include three types of camera payloads: visible light camera, ultraviolet light camera and infrared light camera.

[0011] Furthermore, the load high-speed interface circuit design specifically includes:

[0012] (1) 2711 interface data circuit design;

[0013] (2) LVDS interface data circuit design;

[0014] (3) CameraLink interface data circuit design;

[0015] (4) Design of Gigabit Ethernet interface data transceiver circuit.

[0016] Furthermore, the main and secondary processors and the external storage circuit design method are as follows:

[0017] (1) The main processor uses Xilinx Virtex7 series FPGA: XC7V690T-2FFG1157I. Two groups of DDR3 caches are mounted on the periphery of the FPGA for ping-pong operations. Each group of DDR3 caches uses four 16-bit DDR3 chips, each with a storage capacity of 4 Gbits, for a total of 16 Gbits, which is used for data caching during algorithm execution;

[0018] (2) SRAM is mounted as cache on the periphery of A3P1000, and DDR3 is mounted as cache on the periphery of V7.

[0019] Furthermore, the monitoring circuit design method is as follows:

[0020] (1) Temperature monitoring design

[0021] A temperature sensor chip is installed at each temperature monitoring point on the board. Multiple chips are connected to the FPGA via the I2C bus to read the temperature data regularly and upload it.

[0022] (2) Voltage monitoring circuit design

[0023] The ADC is used to sample the voltage and the sampled value is sent to the FPGA to determine the voltage value. For voltage values ​​that exceed the dynamic range of the ADC sampling, the voltage is processed by voltage division.

[0024] Furthermore, the communication interface circuit is designed as follows:

[0025] The communication display interface circuit mainly includes the design of HDMI and RS422 asynchronous interface circuit

[0026] (1) HDMI interface circuit design

[0027] The HDMI output circuit uses ADV7511W from Analog Device to implement HDMI encoding output of video data.

[0028] The non-volatile storage circuit design reserves an EEPROM non-volatile storage circuit on the board, and the EEPROM is connected to the FPGA using an I2C interface.

[0029] (2) RS422 interface circuit design

[0030] A magnetic isolation chip design is used to reduce the impact of external electromagnetic interference on the board. The magnetic isolation chip uses ADM2582E from ADI.

[0031] Furthermore, the redundancy circuit is designed as follows:

[0032] The V7 program is divided into three identical functional modules, which are all embedded in the A3P1000's external NorFlash. After power-on, the A3P1000 votes on the output results of the three functional modules. After the vote, the V7 program is read out from the NorFlash and loaded into the V7 through the SelectMAP interface for execution. The program stored in the NorFlash is remotely updated through the remote control interface on the interface board.

[0033] Furthermore, the image information processing circuit is designed as follows:

[0034] (1) Design of main and auxiliary processing boards and external storage circuits

[0035] (1.1) The design of the processing board is as follows: the main FPGA uses Xilinx's Virtex7 series FPGA, the specific model is XC7V690T-2FFG1157I;

[0036] The main FPGA1 and the main FPGA2 are interconnected using GTH and IO, GTH is used for high-speed data transmission, and IO is used as an indication signal or interrupt signal;

[0037] (1.2) MSATA storage circuit design uses MSATA disk as storage medium for data storage, and uses SATAIP core inside FPGA to manage the stored data;

[0038] (2) The configuration circuit design of the information processing circuit is as follows:

[0039] The programs of the two V7 chips are solidified into the NorFlash of the A3P1000 plug-in. After power-on, the A3P1000 reads the programs of the two V7 chips from the NorFlash and loads them into the two V7 chips through the SelectMAP interface for execution. The programs stored in the NorFlash are remotely updated through the remote control interface on the interface board.

[0040] Furthermore, the backplane circuit is designed as follows:

[0041] Two VPX architecture computer platforms are used to realize the transmission of image data. Two VPX slots are opened in the middle of the backplane, and the boards are fastened by brackets.

[0042] According to another aspect of the present invention, the present invention provides a design system for an on-orbit image recognition device at the edge of the solar system, specifically comprising:

[0043] The analysis module is used to analyze the load requirements of solar system imaging exploration and determine the load type;

[0044] The interface circuit design module is used to design the interface circuit of the on-orbit image recognition equipment according to the determined payload type, so as to realize the collection of image information. Specifically, the interface circuit mainly includes the payload high-speed interface circuit design, the main processor and external storage circuit design, the monitoring circuit design, the communication interface circuit design and the redundancy circuit design;

[0045] Image information processing circuit design module, used to design on-orbit image information processing circuits to realize image information processing, specifically including main and auxiliary processing boards and external storage circuit design, configuration circuit design;

[0046] The backplane circuit design module is used to design the on-orbit image backplane circuit and to realize the information interconnection between the interface circuit and the image information processing circuit.

[0047] The present invention has at least the following beneficial effects:

[0048] This embodiment aims to obtain on-orbit images in the solar system edge exploration mission, analyzes the payload configuration of the solar system edge exploration mission, designs a camera payload compatible with multiple interface types, provides a hardware platform for obtaining multi-source information fusion processing of high-value images, adopts redundant and online configurable hardware design, improves the reliability of on-orbit image recognition equipment, and enhances the single-particle flip resistance of a single machine.

[0049] Of course, any product implementing the present invention does not necessarily need to achieve all of the advantages described above at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] Figure 1It is a schematic diagram of the overall process of the design method of the present invention;

[0051] Figure 2 This is the overall block diagram of the interface circuit of the on-orbit image recognition device of the present invention;

[0052] Figure 3 This is a schematic diagram of the 2711 interface data circuit of the present invention;

[0053] Figure 4 This is a schematic diagram of the LVDS interface data circuit of the present invention;

[0054] Figure 5 This is a schematic diagram of the CameraLink interface data of the present invention;

[0055] Figure 6 This is a schematic diagram of Gigabit Ethernet interface data according to the present invention;

[0056] Figure 7 Design of the current and voltage monitoring circuit of the present invention;

[0057] Figure 8 This is a schematic diagram of the communication interface circuit of the present invention;

[0058] Fig. 9 This is an overall block diagram of information processing of the on-orbit image recognition device of the present invention;

[0059] Fig.10 This is an overall block diagram of the backplane described in the present invention. DETAILED DESCRIPTION

[0060] The following will be combined with the drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0061] Embodiment 1:

[0062] The detection rate of images in the solar system edge exploration mission is limited by the detector's orbit, observation mode and payload performance, resulting in the mutual constraints of spatial, temporal and spectral resolution, and the inability to achieve the goals of "seeing clearly", "measuring quickly" and "calculating accurately" at the same time. On-orbit image recognition equipment can more easily obtain high-value images, break through the limitations of single payload observation, and realize the comprehensive processing and application of multi-payload data complementarity.

[0063] See also Figure 1-Figure 10 The present invention provides a technical solution: a design method for an on-orbit image recognition device at the edge of the solar system, which specifically includes the following steps:

[0064] S1. Analyze the payload requirements for solar system imaging and detection and determine the payload type;

[0065] There are various types of imaging detection payloads in the detection mission, including CCD stereo camera, topographic camera (RGB full color), lunar optical telescope (near ultraviolet band), extreme ultraviolet camera (30.4nm), infrared imaging spectrometer, multispectral camera and mid-infrared ultra-fine spectrometer. Camera payloads are configured according to mission requirements. The camera resolutions include 2352×1728, 720×576, 1024×1024, etc. The image data frame transmission is between 1fps-5fps, not exceeding 10fps, and the image data transmission rate includes 1Mbps, 16Mbps, 30Mbps, and the maximum does not exceed 40Mbps.

[0066] The interface types for image data transmission include synchronous RS422 bus and LVDS bus (the interface type currently used on cameras). Considering the scalability, the network interface and TLK2711 bus interface are reserved, and the control data transmission interface type mainly uses asynchronous RS422 bus.

[0067] S2. According to the determined payload type, the interface circuit design of the on-orbit image recognition equipment is carried out to realize the collection of image information. Specifically, the interface circuit mainly includes the payload high-speed interface circuit design, the main processor and external storage circuit design, the monitoring circuit design, the communication interface circuit design and the redundancy circuit design, as follows:

[0068] S2.1 Load high-speed interface circuit design, including:

[0069] (S2.11) 2711 interface data circuit design;

[0070] like Figure 3 As shown in the figure, TLK2711A is a bit-level serial transceiver launched by TI, which is suitable for ultra-high-speed bidirectional long-distance point-to-point data transmission system; TLK2711A is a 1.6 to 2.7Gbps high-speed serializer / deserializer, which mainly completes the high-speed parallel-to-serial and serial-to-parallel conversion functions of data, providing an effective data bandwidth of up to 2.16Gbps. Its internal components mainly integrate its parallel / serial and serial / parallel conversion units, clock synthesis and recovery units, 8B / 10B encoder / decoder, comma detection functional unit, pseudo-random sequence generation and verification unit, and phase-locked loop, etc.; the serial output end has a programmable pre-emphasis function, and the receiving end has an internal integrated 50-ohm terminal matching resistor;

[0071] (S2.12) LVDS interface data circuit design;

[0072] like Figure 4As shown, the camera outputs image data to the on-orbit image device through the LVDS interface. According to the requirements, the LVDS interface includes a gate signal (DATA_CS), a clock signal (DATA_CLK), and a data signal (DATA_LVDS). Each signal is output in a differential manner. The maximum data rate of the LVDS port is 20Mbps. The camera uses the LVDS chip SN65LVDS31D from TI.

[0073] (S2.13) CameraLink interface data circuit design;

[0074] like Figure 5 As shown in the figure, CameraLink is a video transmission specification. According to the different transmission rates, it can be divided into three modes: Base, Medium and Full. The signal definition is shown in the figure below. This specification uses 7:1 serialization for data transmission. At the sending end, the parallel LVTTL data is serialized into LVDS data; at the receiving end, the LVDS data is deserialized into LVTTL data.

[0075] (S2.14) Gigabit Ethernet interface data transceiver circuit design;

[0076] like Figure 6 As shown, the Gigabit Ethernet port circuit is implemented by the MACIP core inside the FPGA + the external Gigabit Ethernet PHY chip solution. The PHY chip adopts Marvell's 88E1111, which can provide RGMII, GMII and other interfaces to connect to the main chip. This embodiment adopts the GMII interface, and the PHY supports 1000MBase-T / 100MBase-T / 10MBase-T adaptive Ethernet;

[0077] S2.2 The design method of the main and auxiliary processors and external storage circuit is as follows:

[0078] (S2.21) The main processor uses Xilinx Virtex7 series FPGA: XC7V690T-2FFG1157I. In order to ensure the demand for cache resources for algorithm processing, two groups of DDR3 cache are mounted on the periphery of FPGA for ping-pong operation. Each group of DDR3 cache uses four 16-bit DDR3 chips, each with a storage capacity of 4 Gbits, for a total of 16 Gbits, which is used for data caching during algorithm execution;

[0079] It should be noted that the DDR3 memory chip uses Micron's MT41J256M16DA-093:K, which has a data bit width of 16 bits, a storage capacity of 512MB, and an operating clock of 800MHz dual-edge;

[0080] (S2.22) Mount SRAM as cache on the periphery of A3P1000 and mount DDR3 as cache on the periphery of V7;

[0081] The solution adopted by the configuration circuit is: fix the V7 program into the NorFlash of the A3P1000 plug-in. After power-on, the A3P1000 reads the V7 program from the NorFlash and loads it into the V7 through the SelectMAP interface for operation. The program stored in the NorFlash can be remotely updated through the remote control interface. The SRAM chip selected is the XM7A01M36 of Xingyi Microelectronics.

[0082] S2.3 Figure 7 As shown, the monitoring circuit design method is as follows:

[0083] (S2.31) Temperature monitoring design

[0084] The temperature sensor uses CT7117 from Shenshiling Microelectronics. This chip can provide a temperature recognition accuracy of 0.5°C within the range of -50°C to 150°C. The chip interface is the I2C bus. One chip is placed at each temperature monitoring point on the board. Multiple chips can be connected to the FPGA through the I2C bus. The FPGA reads the temperature data regularly and reports it. The chips that mainly need to be temperature monitored are FPGAs, power chips and other high-power devices.

[0085] (S2.32) Voltage monitoring circuit design

[0086] The design idea of ​​the voltage monitoring circuit is to sample the voltage to be monitored with a high-precision ADC, send the sampled value to the FPGA, determine the voltage value, and use voltage division to process the voltage value that exceeds the dynamic range of the ADC sampling;

[0087] The ADC chip used in the voltage monitoring circuit is Ruimeng Technology's MS5188N. The MS5188N is an 8-channel, 16-bit, charge redistribution successive approximation analog-to-digital converter powered by a single power supply. The MS5188N has all the components required for a multi-channel, low-power data acquisition system, including: a 16-bit SAR ADC with no missing codes; an 8-channel low-crosstalk multiplexer for configuring the input as a single-ended input (with or without a reference ground), differential input, or bipolar input, an internal low-drift reference source (4.096V) and buffer, a temperature sensor, a selectable single-pole filter, and a sequencer that is very useful when multiple passes are sampled in sequence;

[0088] The MS5188N uses a simple SPI interface to write configuration registers and receive conversion results. The SPI interface uses a separate power supply (VIO), which is set to the host logic level. The power consumption is proportional to the conversion rate. The MS5188N uses a small QFN20 package and has an operating temperature range of -40°C to +120°C.

[0090] The S2.4 communication interface circuit design is as follows:

[0091] The communication display interface circuit mainly includes the design of HDMI and RS422 asynchronous interface circuit

[0092] (S2.41) HDMI interface circuit design

[0093] The HDMI output circuit uses the ADV7511W from Analog Device. Its functional block diagram is as follows: Figure 8 As shown, the chip can realize HDMI encoding output of 4k high-definition video. The non-volatile storage circuit design reserves the design of EEPROM non-volatile storage circuit on the board. The EEPROM is connected to FPGA via I2C interface and has a storage capacity of 512Bytes. The model is BL24C04F of Shanghai Belling, Huada Semiconductor;

[0094] (S2.42) RS422 interface circuit design

[0095] The magnetic isolation design is used to reduce the impact of external electromagnetic interference on the board. The magnetic isolation chip is ADI's ADM2582E. Its functional block diagram is as follows: Figure 8 As shown, the main features of the isolation chip are as follows:

[0096] 1) Powered by a single 3.3V power supply, the chip generates an isolated voltage and ground for internal use;

[0097] 2) Can provide ±15kVESD protection;

[0098] 3) Support RS422 data transmission rate up to 16Mbps;

[0099] S2.5 Redundancy Circuit Design

[0100] like Fig. 9As shown in the figure, redundancy design is an effective technology commonly used in aerospace. The circuit adopts the following scheme: divide the V7 program into three identical modules, all of which are solidified into the NorFlash of the A3P1000 plug-in. After power-on, the A3P1000 votes on the output results of the three functional modules. After the vote, the V7 program is read out from the NorFlash and loaded into the V7 through the SelectMAP interface for operation. The program stored in the NorFlash can be remotely updated through the remote control interface on the interface board.

[0101] Specifically, through the above interface design, the recognition device can realize the collection of image information of cameras with multiple interface types;

[0102] S3. Design the on-orbit image information processing circuit to realize the processing of image information, including the design of main and auxiliary processing boards and external storage circuits, and configuration circuits;

[0103] like Fig. 9 As shown, the information processing circuit mainly includes the design of the main and auxiliary processing boards, external storage circuits, configuration circuits, and reset circuits:

[0104] S3.1 Main and auxiliary processing boards and external storage circuit design

[0105] The design of the processing board is as follows: the specific model of the main FPGA is XC7V690T2FFG1157I. Considering the domestic substitution, the FPGA of the Virtex7 series of Xilinx is selected. The resources of this series of FPGA are shown in the following table. The specific model selected is XC7V690T-2FFG1157I;

[0106] The main FPGA1 and the main FPGA2 are interconnected using GTH and IO. GTH is used for high-speed data transmission, and IO can be used as an indication signal or an interrupt signal.

[0107] The MSATA storage circuit design uses MSATA disk as the storage medium for data storage, and uses the SATAIP core inside the FPGA to manage the stored data.

[0108] S3.2 Configuration circuit design of information processing circuit

[0109] The configuration circuit design is: the programs of the two V7 chips are fixed in the NorFlash of the A3P1000 plug-in. After power-on, the A3P1000 reads the programs of the two V7 chips from the NorFlash and loads them into the two V7 chips through the SelectMAP interface for operation. In terms of redundancy design, the programs stored in the NorFlash can be remotely updated through the remote control interface on the interface board.

[0110] Specifically, after the above-mentioned design of the processing board, the on-orbit image recognition device can realize the processing of image information of various types of cameras;

[0111] S4. Design the on-orbit image backplane circuit to realize the information interconnection between the interface circuit and the image information processing circuit:

[0112] like Fig.10 As shown, in terms of backplane design, two VPX architecture computer platforms are used with high-speed backplane exchange speed to realize the transmission of image data. Two VPX slots are opened in the middle of the backplane to serve as brackets to fasten the boards, which is convenient for protecting the box and plugging and unplugging. The backplane is designed as above to realize information interconnection between the interface board and the processing board, and complete the fastening of the boards.

[0113] To summarize, this embodiment aims to obtain on-orbit images in the solar system edge exploration mission, analyzes the payload configuration of the solar system edge exploration mission, designs a camera payload compatible with multiple interface types, provides a hardware platform for obtaining multi-source information fusion processing of high-value images, adopts redundant and online configurable hardware design, improves the reliability of on-orbit image recognition equipment, and enhances the single-particle flip resistance of a single machine.

[0114] Embodiment 2:

[0115] The present invention provides a design system for an on-orbit image recognition device at the edge of the solar system, specifically comprising:

[0116] The analysis module is used to analyze the load requirements of solar system imaging exploration and determine the load type;

[0117] The interface circuit design module is used to design the interface circuit of the on-orbit image recognition equipment according to the determined payload type, so as to realize the collection of image information. Specifically, the interface circuit mainly includes the payload high-speed interface circuit design, the main processor and external storage circuit design, the monitoring circuit design, the communication interface circuit design and the redundancy circuit design;

[0118] Image information processing circuit design module, used to design on-orbit image information processing circuits to realize image information processing, specifically including main and auxiliary processing boards and external storage circuit design, configuration circuit design;

[0119] The backplane circuit design module is used to design the on-orbit image backplane circuit and to realize the information interconnection between the interface circuit and the image information processing circuit.

[0120] Specifically, the above-mentioned analysis module, interface circuit design module, image information processing circuit design module, and backplane circuit design module can be embedded in a computer processing system. The computer calls the above-mentioned modules to complete the image recognition task based on the above-mentioned design method of the on-orbit image recognition device at the edge of the solar system; the above-mentioned analysis module, interface circuit design module, image information processing circuit design module, and backplane circuit design module can perform operations according to the specific steps given in the design method of the on-orbit image recognition device at the edge of the solar system.

[0121] It should be noted that it should be understood that the division of the various modules of the above system is only the division of logical functions. In actual implementation, they can be fully or partially integrated into one physical entity, or they can be physically separated, and these modules can all be implemented in the form of software calling through processing elements; they can also be all implemented in the form of hardware; some modules can also be implemented in the form of software calling through processing elements, and some modules can be implemented in the form of hardware. For example, the analysis module can be a separately established processing element, or it can be integrated in a certain chip of the above device. In addition, it can also be stored in the memory of the above device in the form of program code, and called and executed by a certain processing element of the above device. The implementation of other modules is similar. In addition, these modules can be fully or partially integrated together, or they can be implemented independently. The processing element described here can be an integrated circuit with signal processing capabilities. In the implementation process, each step of the above method or each module above can be completed by the hardware integrated logic circuit in the processor element or the instruction in the form of software.

[0122] For example, the above modules may be one or more integrated circuits configured to implement the above methods, such as one or more application specific integrated circuits (ASIC), or one or more digital signal processors (DSP), or one or more field programmable gate arrays (FPGA). For another example, when a module is implemented in the form of a processing element scheduling program code, the processing element may be a general-purpose processor, such as a central processing unit (CPU) or other processor that can call program code. For another example, these modules may be integrated together and implemented in the form of a system-on-a-chip (SOC).

[0123] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device.

[0124] For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to the specific circumstances. When an element is referred to as being "assembled on", "installed on", "fixed on" or "set on" another element, it can be directly on the other element or there can also be a centered element. When an element is considered to be "connected" to another element, it can be directly connected to the other element or there may be a centered element at the same time. The terms "vertical", "horizontal", "up", "down", "left", "right" and similar expressions used herein are only for illustrative purposes and are not intended to be the only implementation method.

[0125] Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the appended claims and their equivalents.

[0126] In the description of this specification, the description with reference to the terms "one embodiment", "example", "specific example", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present disclosure. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

Claims

1. A design method for an on-orbit image recognition device at the edge of the solar system, characterized in that: The following steps are involved: Analyze the payload requirements for solar system imaging and detection and determine the payload type; According to the determined payload type, the interface circuit design of the on-orbit image recognition equipment is carried out to realize the collection of image information. Specifically, the interface circuit mainly includes the payload high-speed interface circuit design, the main processor and external storage circuit design, the monitoring circuit design, the communication interface circuit design and the redundancy circuit design; Design on-orbit image information processing circuits to realize image information processing, including main and auxiliary processing boards, external storage circuit design, and configuration circuit design; The on-orbit image backplane circuit is designed to realize information interconnection between the interface circuit and the image information processing circuit.

2. The design method of the solar system marginal on-orbit image recognition device according to claim 1 is characterized in that: The solar system imaging detection payload types include three types of camera payloads: visible light camera, ultraviolet light camera and infrared light camera.

3. The design method of the solar system edge on-orbit image recognition device according to claim 2 is characterized in that: The load high-speed interface circuit design specifically includes: (1) 2711 interface data circuit design; (2) LVDS interface data circuit design; (3) CameraLink interface data circuit design; (4) Design of Gigabit Ethernet interface data transceiver circuit.

4. The design method of the solar system edge on-orbit image recognition device according to claim 2 is characterized in that: The design method of the main and auxiliary processors and the external storage circuit is as follows: (1) The main processor uses Xilinx Virtex7 series FPGA: XC7V690T-2FFG1157I. Two groups of DDR3 caches are mounted on the periphery of the FPGA for ping-pong operations. Each group of DDR3 caches uses four 16-bit DDR3 chips, each with a storage capacity of 4 Gbits, for a total of 16 Gbits, which is used for data caching during algorithm execution; (2) SRAM is mounted as cache on the periphery of A3P1000, and DDR3 is mounted as cache on the periphery of V7.

5. The design method of the solar system edge on-orbit image recognition device according to claim 4 is characterized in that: The monitoring circuit design method is as follows: (1) Temperature monitoring design A temperature sensor chip is installed at each temperature monitoring point on the board. Multiple chips are connected to the FPGA via the I2C bus to read the temperature data regularly and upload it. (2) Voltage monitoring circuit design The ADC is used to sample the voltage and the sampled value is sent to the FPGA to determine the voltage value. For voltage values ​​that exceed the dynamic range of the ADC sampling, the voltage is processed by voltage division.

6. The design method of the solar system edge on-orbit image recognition device according to claim 5 is characterized by: The communication interface circuit is designed as follows: The communication display interface circuit mainly includes the design of HDMI and RS422 asynchronous interface circuit (1) HDMI interface circuit design The HDMI output circuit uses ADV7511W from Analog Device to implement HDMI encoding output of video data. The non-volatile storage circuit design reserves an EEPROM non-volatile storage circuit on the board, and the EEPROM is connected to the FPGA using an I2C interface. (2) RS422 interface circuit design A magnetic isolation chip design is used to reduce the impact of external electromagnetic interference on the board. The magnetic isolation chip uses ADM2582E from ADI.

7. The design method of the solar system edge on-orbit image recognition device according to claim 5 is characterized by: The redundancy circuit is designed as follows: The V7 program is divided into three identical functional modules, which are all embedded in the A3P1000's external NorFlash. After power-on, the A3P1000 votes on the output results of the three functional modules. After the vote, the V7 program is read out from the NorFlash and loaded into the V7 through the SelectMAP interface for execution. The program stored in the NorFlash is remotely updated through the remote control interface on the interface board.

8. The design method of the solar system marginal on-orbit image recognition device according to claim 7 is characterized in that: The image information processing circuit is designed as follows: (1) Design of main and auxiliary processing boards and external storage circuits (1.1) The design of the processing board is as follows: the main FPGA uses Xilinx's Virtex7 series FPGA, the specific model is XC7V690T-2FFG1157I; The main FPGA1 and the main FPGA2 are interconnected using GTH and IO, GTH is used for high-speed data transmission, and IO is used as an indication signal or interrupt signal; (1.2) MSATA storage circuit design uses MSATA disk as storage medium for data storage, and uses SATAIP core inside FPGA to manage the stored data; (2) The configuration circuit design of the information processing circuit is as follows: The programs of the two V7 chips are solidified into the NorFlash of the A3P1000 plug-in. After power-on, the A3P1000 reads the programs of the two V7 chips from the NorFlash and loads them into the two V7 chips through the SelectMAP interface for execution. The programs stored in the NorFlash are remotely updated through the remote control interface on the interface board.

9. The design method of the solar system marginal on-orbit image recognition device according to claim 1 is characterized in that: The backplane circuit design is as follows: Two VPX architecture computer platforms are used to realize the transmission of image data. Two VPX slots are opened in the middle of the backplane, and the boards are fastened by brackets.

10. Design system for on-orbit image recognition equipment at the edge of the solar system, characterized in that: Specifically include: The analysis module is used to analyze the load requirements of solar system imaging exploration and determine the load type; The interface circuit design module is used to design the interface circuit of the on-orbit image recognition equipment according to the determined payload type, so as to realize the collection of image information. Specifically, the interface circuit mainly includes the payload high-speed interface circuit design, the main processor and external storage circuit design, the monitoring circuit design, the communication interface circuit design and the redundancy circuit design; Image information processing circuit design module, used to design on-orbit image information processing circuits to realize image information processing, specifically including main and auxiliary processing boards and external storage circuit design, configuration circuit design; The backplane circuit design module is used to design the on-orbit image backplane circuit and to realize the information interconnection between the interface circuit and the image information processing circuit.

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