Memory erasing method of memory device and memory device thereof

Abstract

The invention provides a memory erasing method of a memory device and the memory device thereof. The memory device is a three-dimensional NAND gate flash memory with high capacity and high performance. The memory erasing method comprises the following steps: providing a memory block which comprises a plurality of memory cell strings, and the memory cell strings comprise a plurality of memory cell strings, a plurality of string selection transistors and a plurality of grounding selection transistors; corresponding erase voltages are respectively applied to the corresponding word line, the common source line, the corresponding bit line, the string selection transistor and the string selection transistor of each of the memory cell strings. A voltage difference between a bit line erase voltage and a string selection line erase voltage or a voltage difference between a common source line erase voltage and a ground selection line erase voltage is less than or equal to a predetermined voltage difference, and the memory cells in the memory cell string are randomly divided into a first type erase bit or a second type erase bit.

Description

Technical Field

[0001] The present invention relates to a memory erasing technology applied to a memory device (eg, NAND cache memory), and more particularly to a memory erasing method of the memory device and the memory device. Background Art

[0002] High-capacity and high-performance integrated circuit memories, including 3D NAND flash memory, are continuing to develop, hoping to use three-dimensional stacking technology and multi-level cells (MLC) to reduce the size of storage cells and increase data storage density. On the other hand, Physical Unclonable Functions (PUF) technology is based on process variability and material characteristics, so that objects manufactured through semiconductor processes will produce highly random and unpredictable data. This data can be used for authentication, device keys, communication security, etc., and has uniqueness.

[0003] PUF technology in 3D flash memory can be implemented based on program disturb, read disturb or program operation latency, but these methods may be limited by the program erase cycle (P / E cycle) in flash memory. In other words, after a large number of programming / erasing, the cache memory may change the physical characteristics of the storage unit, making the PUF data unstable. Summary of the invention

[0004] The present invention provides an erasing method of a memory device and a memory device thereof, which erases a memory block so that memory cells in a memory cell string randomly generate different threshold voltage distributions, thereby obtaining PUF data.

[0005] The erasing method of a memory device of an embodiment of the present invention includes the following steps: providing a memory block, wherein the memory block includes a plurality of memory cell strings, the memory cell strings include a plurality of memory cells, a plurality of string selection transistors and a plurality of ground selection transistors, wherein each of the memory cell strings includes a string selection transistor connected in series with each other, a plurality of memory cells among the plurality of memory cells and a ground selection transistor, the memory cell strings are coupled to corresponding bit lines through corresponding string selection transistors, and are coupled to common source lines through corresponding ground selection transistors, and the plurality of memory cells are respectively connected to a plurality of corresponding word lines; applying a word line erasing voltage to the plurality of corresponding word lines of each of the memory cell strings; applying a common source line erasing voltage to the common source line; applying a bit line erasing voltage to the corresponding bit line of each of the memory cell strings; applying a string selection line erasing voltage to the string selection transistor of each of the memory cell strings; and applying a ground selection line erasing voltage to the ground selection transistor of each of the memory cell strings. The voltage difference between the bit line erase voltage and the string selection line erase voltage or the voltage difference between the common source line erase voltage and the ground selection line erase voltage is less than or equal to a predetermined voltage difference, and the memory cells in the memory cell string are randomly divided into first type erase bits or second type erase bits.

[0006] A memory device according to an embodiment of the present invention includes a memory block and a memory controller. The memory block includes a plurality of memory cell strings, the memory cell strings include a plurality of memory cells, a plurality of string selection transistors, and a plurality of ground selection transistors, each of the memory cell strings includes a string selection transistor connected in series, a plurality of memory cells among the plurality of memory cells, and a ground selection transistor, the memory cell strings are coupled to corresponding bit lines through corresponding string selection transistors, and are coupled to a common source line through corresponding ground selection transistors, and the plurality of memory cells are each connected to a plurality of corresponding word lines; a memory controller is coupled to the memory block and controls a plurality of voltage drivers to: supply voltages to the plurality of corresponding word lines of each of the memory cell strings; A word line erase voltage is applied, a common source line erase voltage is applied to the common source line, a bit line erase voltage is applied to the corresponding bit line of each of the memory cell strings, a string selection line erase voltage is applied to the string selection transistor of each of the memory cell strings, and a ground selection line erase voltage is applied to the ground selection transistor of each of the memory cell strings, wherein the voltage difference between the bit line erase voltage and the string selection line erase voltage or the voltage difference between the common source line erase voltage and the ground selection line erase voltage is less than or equal to a predetermined voltage difference, and the memory cells in the memory cell string are randomly divided into first type erase bits or second type erase bits.

[0007] Based on the above, the erasing method of the memory device and the memory device described in the embodiment of the present invention use a threshold voltage close to the gate induced drain leakage (GIDL) erasing operation to perform a GIDL erasing operation on the memory block, so that the multiple memory cells in the multiple memory cell strings will randomly generate different threshold voltage distributions, thereby obtaining PUF data. Therefore, the embodiment of the present invention performs a memory erasing operation on the multiple memory cells in the multiple memory cell strings, so that the multiple memory cells in the multiple memory cell strings randomly generate different threshold voltage distributions, and then generate PUF data correspondingly according to these erased memory cell strings. Moreover, the threshold voltage distribution presented by each memory cell in the erased memory cell string will be the same, that is, the PUF data corresponding to each page in the memory device will be the same. Therefore, when the number of programming-erasing times of a specific page in the memory device exceeds the wear threshold, another page of the memory device can be used to replace the aforementioned specific page to increase the stability of the PUF data. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 FIG. 1 is a schematic diagram of the structure of a memory block 150 in a three-dimensional memory chip according to an embodiment of the present invention.

[0009] Figure 2 FIG. 4 is a schematic diagram illustrating a gate induced drain leakage (GIDL) erasing method according to an embodiment of the present invention.

[0010] Figure 3 It is a schematic diagram illustrating the influence of holes caused by gate induced drain leakage (GIDL) on the threshold voltage distribution in a memory cell according to an embodiment of the present invention.

[0011] Figure 4 FIG. 4 is a schematic diagram illustrating threshold voltage distribution and physical unclonable function (PUF) data in a memory cell according to an embodiment of the present invention.

[0012] Figure 5 1 is a flowchart of a method for erasing a memory device according to an embodiment of the present invention, and is also a flowchart of a method for generating data of a physical PUF according to an embodiment of the present invention.

[0013] Figure 6 FIG. 4 is a schematic diagram showing a portion of memory cell strings and pages in a memory cell block according to an embodiment of the present invention.

[0014] Description of Reference Numerals

[0015] 110: Memory controller

[0016] 150: Memory block

[0017] 152, 610, 620: Page

[0018] 154, 154-1: Storage cell string

[0019] 156.SSL: string selection line

[0020] 157: Storage unit

[0021] 158. GSL: Ground selection line

[0022] 159. CSL: Common Source Line

[0023] 310, 320, 330, 430: Arrow

[0024] 410, 420: convex dotted line

[0025] S510-S530: Steps of the method for erasing a memory device

[0026] dV1: Voltage difference between bit line and string select line

[0027] dV2: Voltage difference between ground select line and common source line

[0028] GIDL: Gate Induced Drain Leakage

[0029] Numb: Number of storage units

[0030] Vt: threshold voltage

[0031] Cond1, Cond2: Situation

[0032] dV1 / dV2: voltage difference

[0033] BL1, BL2, BL3, BLn, BLn+1: bit lines

[0034] WL0~WL95, WLn-1, WLn, WLn+1: word lines

[0035] SST: string select line transistor

[0036] GST: Ground Select Line Transistor

[0037] GIDLCur: Current value in the memory cell string subjected to the GIDL erase method

[0038] PL: Numerical value DETAILED DESCRIPTION

[0039] Figure 11 is a schematic diagram of the structure of a memory block 150 in a three-dimensional memory chip according to an embodiment of the present invention. A plurality of memory cells in the memory block 150 are arranged in three dimensions, for example, an XYZ coordinate system. Taking memory cell 157 as an example, memory cell 157 is coupled to a corresponding word line WL0 and a bit line BLn. Word lines (e.g., word lines WL0 to WL95) formed by a conductive layer or a word line layer and a plurality of memory cells coupled thereto form a plurality of pages 152. In other words, the memory cells in the memory block 150 are divided into a plurality of pages 152. Each page may be, for example, a layer of memory cells in an XY plane. Memory cells on the same layer (same page) may be coupled to the same word line (e.g., word line WL0 or WL95) and obtain a corresponding word line voltage. Memory cells on different layers (different pages) are coupled to different word lines (e.g., word lines WL0 and WL95) and obtain different word line voltages. In other words, a page in the memory block 150 is composed of memory cells connected to one of the corresponding word lines (e.g., one of the word lines WL0 to WL95) in the memory cell strings. Each page in the multiple pages 152 can be connected to a corresponding contact in the driving circuit, such as an X decoder (or scan driver), through one of the word lines WL0 to WL95 coupled to the page. Each line has a corresponding voltage driver, and these voltage drivers can be controlled by the memory controller 110 or corresponding hardware. The multiple memory cells in the memory cell string 154 belong to different pages.

[0040] Each string (e.g., string 154) includes a plurality of memory cells connected in series vertically along the Z direction. The memory cell string includes a plurality of memory cells (e.g., memory cell 157), a plurality of string selection transistors SST coupled to a string selection line SSL 156, and a plurality of ground selection transistors GST coupled to a ground selection line GSL 158. String 154 is connected to one or more drivers, such as a data driver. Memory cell 157 is connected to a common source line CSL 159 via a ground selection transistor GST. SSL 156 may be a conductive line or conductive layer formed on the top of each page 152 (or word line layer). The memory block 150 may include a plurality of SSLs 156 provided on a page located at the top of a plurality of pages 152. GSL 158 may be a conductive line or conductive layer formed on the bottom of each page 152 (or word line layer). CSL 159 may be a conductive layer or a plurality of conductive lines formed below the ground selection line GSL 158 and on the substrate of the three-dimensional storage chip. Several dummy lines or corresponding layers (not shown) may be further provided between the string selection line SSL 156 and the uppermost page 152 , or between the ground selection line GSL 158 and the lowermost page 152 .

[0041] The embodiment of the present invention is based on the variability of process variability and the variability of the erasing capability of gate induced drain leakage (GIDL). By adjusting the erase voltage of the GIDL erase operation to make the threshold voltage distribution in the memory block unstable, the memory cells can be distinguished into fast-erasing memory cells and slow-erasing memory cells, and thus correspondingly generate different bits in the physical uncopyable function (PUF) data (e.g., first type erase bit and second type erase bit). In addition, the aforementioned GIDL erase method will make all memory cells in each memory cell string have the same threshold voltage distribution, so the PUF data generated for each page is the same. When the number of programming-erasing times of a specific page exceeds the wear threshold, the embodiment of the present invention uses another page in the multiple pages as this specific page to generate the same PUF data, thereby reducing the impact of erase cycles on the PUF data. The following is a detailed description of each embodiment.

[0042] Figure 2 is a schematic diagram illustrating a gate induced drain leakage (GIDL) erasing method according to an embodiment of the present invention. Figure 2 Draw Figure 1 The following are some of the components to illustrate the GIDL erase method. Figure 2 As shown, the memory block 150 can use the GIDL erasing method to set all memory cells to logic "0". The GIDL erasing method uses the string selection transistor SST and / or the ground selection transistor GST formed by the doping technology to be due to the voltage difference between the bit line BL and the string selection line SSL (e.g., Figure 2 voltage difference dV1) and / or the voltage difference between the ground selection line GSL and the common source line CSL (eg, Figure 2 The voltage difference dV2) generates a corresponding electron flow or hole flow to adjust the threshold voltage of each memory cell in the memory cell string 154, thereby performing an erasing method on the memory cell.

[0043] The GIDL erasing method is implemented based on a string selection transistor SST and / or a ground selection transistor GST formed by a doping technique, and the doping conditions of the string selection transistor SST and / or the ground selection transistor GST may be slightly different due to the variability of the semiconductor process, thereby causing the aforementioned voltage difference dV1 or dV2 to affect the threshold voltage distribution in the storage cell.

[0044] Figure 3 FIG. 4 is a schematic diagram illustrating the effect of holes caused by GIDL on the threshold voltage distribution in a memory cell according to an embodiment of the present invention. Figure 3In the graph (A), the Y-axis labeled GIDLCur represents the current value of a specific memory cell string subjected to the GIDL erasing method, and the value PL on the Y-axis represents the standard sufficient for the GIDL erasing method. A current value of the GIDL erasing method lower than the value PL indicates that the memory cell fails in the GIDL erasing method; a current value of the GIDL erasing method higher than the value PL indicates that the memory cell succeeds in the GIDL erasing method. Figure 3 The X-axis labeled dV1 / dV2 in the center graph represents the voltage difference dV1 between the bit line BL and the string selection line SSL or the voltage difference dV2 between the ground selection line GSL and the common source line CSL. Figure 3 Graph (B) and Graph (C) are respectively the distribution of the number of memory cells Numb and the corresponding threshold voltage Vt when the voltage difference dV1 / dV2 is in the case of Cond1 or Cond2. The case of Cond1 can also be called a strong erase case, which has a larger voltage difference dV1 / dV2; the case of Cond2 can also be called a weak erase case, which has a smaller voltage difference dV1 / dV2. In addition, in this embodiment, the Figure 3 In the case Cond2 in the graph (C), the voltage difference dV1 / dV2 is slightly less than 5V, and thus it is also called a GIDL erase method lacking sufficient current.

[0045] from Figure 3 It is known that in a normal GIDL erasing method, a larger voltage difference dV1 / dV2 is provided (eg, case Cond1), so that the number of memory cells Numb in the memory cell and the corresponding threshold voltage Vt are distributed on a specific convex curve, such as Figure 3 As shown in the diagram (B), each erased memory cell has a similar threshold voltage, as shown by arrow 310. On the other hand, the embodiment of the present invention provides a smaller voltage difference dV1 / dV2 (such as the case Cond2) so that the number of memory cells Numb in the memory cell and the corresponding threshold voltage Vt distribution have two peaks, such as Figure 3 As shown in chart (C). Figure 3 The first peak of the graph (C) indicates the memory cell corresponding to the current value of the GIDL erasing method that is higher than the value PL (referred to as a strongly erased memory cell), as indicated by arrow 320 . Figure 3 The second peak of the graph (C) represents the memory cell corresponding to the current value of the GIDL erasing method that is lower than the value PL (referred to as a weakly erased memory cell), as indicated by arrow 330 .

[0046] In other words, the embodiment of the present invention uses the GIDL erasing method to set the voltage difference dV1 between the bit line BL and the string selection line SSL or the voltage difference dV2 between the ground selection line GSL and the common source line CSL according to Figure 3The case Cond2 in the diagram (C) provides the corresponding voltage difference, so that the memory cell presents Figure 3 The threshold voltage distribution in the diagram (C) is used to randomly divide the memory cells into strongly erased memory cells and weakly erased memory cells according to the threshold voltage distribution of the memory cells, and the strongly erased memory cells are set to the first type of erased bits (e.g., bit logic "1"), and the weakly erased memory cells are set to the second type of erased bits (e.g., bit logic "0"), thereby obtaining PUF data generated by the process variability. And all the memory cells in each memory cell string will present the same type of memory cells, for example, as long as one of the memory cells in a specific memory cell string is measured as a strongly erased memory cell, the other memory cells in this specific memory cell string will also be strongly erased memory cells; as long as one of the memory cells in a specific memory cell string is measured as a weakly erased memory cell, the other memory cells in this specific memory cell string will also be weakly erased memory cells.

[0047] Figure 4 FIG. 4 is a schematic diagram illustrating threshold voltage distribution and PUF data in a memory cell according to an embodiment of the present invention. Figure 4 The Y-axis of the chart (A) represents the cumulative number of memory cells, the X-axis represents the threshold voltage of the memory cell, the convex dotted line 410 represents the threshold voltage distribution of the weakly erased memory cell, the convex dotted line 420 represents the threshold voltage distribution of the strongly erased memory cell, and the arrow 430 and the corresponding box indicate the memory cell interval with unstable values. Figure 4 The right side (B) shows part of the memory block. For example, the page corresponding to the word line WLn in (B) can be used to store the other memory cell strings. Figure 4 The predetermined threshold voltage threshold PVt is used to distinguish whether the corresponding memory cell is a strongly erased memory cell (corresponding to logic "1") or a weakly erased memory cell (corresponding to logic "0"). If the threshold voltage of the memory cell of the memory cell string 154-1 is located at the box indicated by the arrow 430, it means that the threshold voltage value corresponding to this memory cell is an unstable memory cell interval. The embodiment of the present invention will filter out and ignore this memory cell, and will not use the memory cell of the memory cell string 154-1 to generate PUF data.

[0048] Figure 5 1 is a flowchart of a method for erasing a memory device according to an embodiment of the present invention, and is also a flowchart of a method for generating data of a physical PUF according to an embodiment of the present invention. Figure 5 The method is applicable to Figure 1 and Figure 2 The memory block structure may be implemented by a memory controller or corresponding hardware.

[0049] In step S510, a memory block (such as Figure 1Memory block 150). Memory block 150 includes a plurality of memory cell strings (e.g., memory cell string 154), the plurality of memory cells including a plurality of memory cells (e.g., memory cell 157) connected in series with each other, a plurality of string selection transistors (e.g., string selection transistor SST) and a plurality of ground selection transistors (e.g., ground selection transistor GST). One or more string selection transistors (e.g., string selection transistor SST) among the plurality of string selection transistors, a plurality of memory cells (e.g., memory cell 157) among the plurality of memory cells and one or more each ground selection transistor (e.g., ground selection transistor GST) among the plurality of ground selection transistors are connected in series with each other to form each memory cell string (e.g., memory cell string 154). Memory cell string 154 is coupled to a corresponding bit line BLn through a corresponding string selection transistor SST, and memory cell string 154 is coupled to a common source line CSL through a corresponding ground selection transistor. Each memory cell is connected to a corresponding plurality of word lines (e.g., word lines WL0 to WL95).

[0050] In step S515, Figure 5 Before step S510, the memory controller programs a plurality of memory cells in the memory block. This embodiment adopts page programming.

[0051] In step S520, the memory controller applies corresponding erase voltages to the word lines, common source lines, bit lines, string selection transistors, and ground selection transistors in the memory block 150, respectively. Specifically, in the present embodiment, a word line erase voltage (e.g., 0V) is applied to the corresponding word lines WL0 to WL95 of each of the memory cell strings. A common source line erase voltage (e.g., 20V) is applied to the common source line CSL. A bit line erase voltage (e.g., 20V) is applied to the corresponding bit line BLn of each of the plurality of memory cell strings (e.g., memory cell string 154). A string selection line erase voltage is applied to the string selection transistor SST of each memory cell string. A ground selection line erase voltage is applied to the ground selection transistor GST of each memory cell string. The voltage difference dV1 between the bit line erase voltage and the string selection line erase voltage needs to be less than or equal to a predetermined voltage difference (5V). In other words, the voltage difference dV1 between the bit line erase voltage and the string selection line erase voltage is between 0V and 5V. Similarly, the voltage difference dV2 between the common source line erase voltage and the ground selection line erase voltage also needs to be less than or equal to the predetermined voltage difference (5V). The voltage difference dV1 and the voltage difference dV2 of this embodiment can be different from each other. Based on the above, the string selection line erase voltage (i.e., the voltage on the string selection line SSL) and the ground selection line erase voltage (i.e., the voltage on the ground selection line GSL) can be approximately 15V in this embodiment.

[0052] After steps S510 and S520, the GIDL erasing operation is performed in the multiple memory cells of the multiple memory cell strings (e.g., memory cell string 154), and the aforementioned multiple erasing voltages cause the memory cells in the memory cell string 154 to perform the GIDL erasing operation. And after the GIDL erasing operation, all the multiple memory cells in the memory cell string 154 are randomly divided into the first type erasing bit or the second type erasing bit. And, all the multiple memory cells in a specific memory cell string are the aforementioned first type erasing bit, or, all the multiple memory cells in a specific memory cell string are the aforementioned second type erasing bit. In other words, the erasing bit type of each of the multiple memory cells in the memory cell string is the same, and each memory cell string can only generate one bit in the PUF data.

[0053] In step S530, the memory controller generates PUF data corresponding to the memory cell string randomly divided into the first type of erased bit or the second type of erased bit. The memory controller divides the memory cell into the first type of erased bit or the second type of erased bit according to the threshold voltage of the memory cell. In addition, when the threshold voltage of the memory cell cannot be used to distinguish the memory cell as the first type of erased bit or the second type of erased bit, that is, the threshold voltage of the memory cell is located at Figure 4 Arrow 430 and the corresponding box indicate an unstable memory cell region, and the indistinguishable memory cells are not used to generate PUF data.

[0054] In this embodiment, in the aforementioned step S515, Figure 1 The memory block 150 is programmed in units of pages (i.e., page programming), and is erased in units of the entire memory block 150 (i.e., block erasing). However, since the present embodiment uses GIDL erasing, multiple memory cells in a memory cell string will present the same type of erased bits, and each memory cell string can only generate one bit of PUF data. Furthermore, if the entire memory block is erased, each memory cell in the memory block will increase the cumulative number of programming and erasing cycles (P / E cycles) in the flash memory by one. Therefore, another example in the embodiment of the present invention illustrates a method of using page erasing instead of block erasing.

[0055] Figure 6 FIG. 1 is a schematic diagram showing a portion of memory cell strings and pages in a memory cell block according to an embodiment of the present invention. Figure 6 As shown, the embodiment of the present invention adopts page programming and page erasing. In other words, the erasing method or PUF data generation method of the present embodiment will program all the memory cells in a specific page (e.g., page 610) in the page before the memory cells are randomly divided into the first type of erased bits or the second type of erased bits.

[0056] Then, the memory controller determines whether the number of program-erase cycles of the specific page 610 exceeds the wear threshold. If the number of program-erase cycles does not exceed the wear threshold, it means that the PUF data generated using the specific page 610 is less likely to be unstable due to the limitation of the erase cycle in the flash memory. Therefore, this embodiment will continue to use the specific page 610. Figure 5 In step S520 and step S530, PUF data is generated. In contrast, if the number of program-erase cycles exceeds the wear threshold, it means that the PUF data generated using the specific page 610 has a higher probability of being unstable due to the limitation of the erase-write cycle in the flash memory. At this time, the memory controller of this embodiment uses another page of the multiple pages (e.g., page 620 corresponding to word line WLn+1) as the aforementioned specific page, and continues to Figure 5 Step S520 and step S530 generate PUF data. The reason for generating PUF data in a page is that all the multiple storage cells in each storage cell string will be erased by GIDL and distinguished as the same type of erased bits. That is, in this embodiment, each page is erased by GIDL. Figure 5 The PUF data generated corresponding to step S510 to step S530 are the same.

[0057] In summary, the erasing method of the memory device and the memory device according to the embodiment of the present invention use a threshold voltage close to the gate induced drain leakage (GIDL) erasing operation to perform a GIDL erasing operation on the memory block, so that the multiple memory cells in the multiple memory cell strings will randomly generate different threshold voltage distributions, thereby obtaining PUF data. Therefore, the embodiment of the present invention performs a memory erasing operation on the multiple memory cells in the multiple memory cell strings, so that the multiple memory cells in the multiple memory cell strings randomly generate different threshold voltage distributions, and then generate PUF data correspondingly according to these erased memory cell strings. Moreover, the threshold voltage distribution presented by each memory cell in the erased memory cell string will be the same, that is, the PUF data corresponding to each page in the memory device will be the same. Therefore, when the number of programming-erasing times of a specific page in the memory device exceeds the wear threshold, another page of the memory device can be used to replace the aforementioned specific page to increase the stability of the PUF data.

Claims

1. A memory erasing method of a memory device, comprising: Providing a memory block, wherein the memory block includes a plurality of memory cell strings, the memory cell strings include a plurality of memory cells, a plurality of string selection transistors, and a plurality of ground selection transistors, wherein each of the memory cell strings includes a string selection transistor, a plurality of memory cells among the plurality of memory cells, and a ground selection transistor connected in series with each other, the memory cell strings are coupled to corresponding bit lines through corresponding string selection transistors, and are coupled to a common source line through corresponding ground selection transistors, and the plurality of memory cells are each connected to a plurality of corresponding word lines; applying a word line erase voltage to the plurality of corresponding word lines of each of the memory cell strings; applying a common source line erase voltage to the common source line; applying a bit line erase voltage to a corresponding bit line of each of the memory cell strings; applying a string selection line erase voltage to the string selection transistor of each of the memory cell strings; as well as applying a ground selection line erase voltage to the ground selection transistor of each of the memory cell strings, Wherein the voltage difference between the bit line erase voltage and the string selection line erase voltage or the voltage difference between the common source line erase voltage and the ground selection line erase voltage is less than or equal to a predetermined voltage difference, and the memory cells in the memory cell string are randomly divided into first type erase bits or second type erase bits.

2. The memory erasing method according to claim 1, further comprising: Physically uncopyable functional data is correspondingly generated according to the memory cells in the memory cell string that are randomly divided into the first type erasure bits or the second type erasure bits. 3 . The memory erasing method according to claim 1 , wherein the memory cells in the memory cell string undergo a gate induced drain leakage current erasing operation.

4. The memory erasing method according to claim 3, wherein after the gate induced drain leakage current erasing operation, all of the multiple storage cells in a specific storage cell string are the first type erased bits, or, all of the multiple storage cells in a specific storage cell string are the second type erased bits.

5. The memory erasing method according to claim 1 , further comprising: The memory cell is classified as the first type erased bit or the second type erased bit according to a threshold voltage of the memory cell.

6. The memory erasing method according to claim 5, further comprising: In the case that the memory cells cannot be distinguished as the first type erased bits or the second type erased bits by using the threshold voltages of the memory cells, the plurality of memory cells that cannot be distinguished are not used. 7 . The memory erasing method according to claim 1 , wherein a voltage range of the predetermined voltage difference is 0V to 5V.

8. The memory erasing method according to claim 1, further comprising: The memory cells in the memory block are programmed before the memory cells in the memory cell string are randomly distinguished as the first type erased bits or the second type erased bits.

9. The memory erasing method according to claim 1, wherein a page in the memory block is composed of the plurality of memory cells connected to a corresponding one of the plurality of word lines in the memory cell string, and The memory erasing method further comprises: Before causing the plurality of memory cells in the memory cell string to be randomly distinguished into the first type erased bits or the second type erased bits, programming all memory cells in a specific page of the plurality of pages; Determining whether the number of program-erase times of the specific page exceeds a wear threshold; as well as When the number of program-erase times of the specific page exceeds a wear threshold, another page of the plurality of pages is used as the specific page.

10. The memory erasing method according to claim 1, wherein the word line erasing voltage is 0V, the common source line erasing voltage is 20V, and the bit line erasing voltage is 20V.

11. A memory device comprising: A memory block, wherein the memory block comprises a plurality of memory cell strings, the memory cell strings comprising a plurality of memory cells, a plurality of string selection transistors and a plurality of ground selection transistors, wherein each of the memory cell strings comprises a string selection transistor, a plurality of memory cells among the plurality of memory cells and a ground selection transistor connected in series with each other, the memory cell strings are coupled to corresponding bit lines through corresponding string selection transistors, and are coupled to a common source line through corresponding ground selection transistors, and the plurality of memory cells are respectively connected to a plurality of corresponding word lines; A memory controller, coupled to the memory block, controls a plurality of voltage drivers to: applying a word line erase voltage to the plurality of corresponding word lines of each of the memory cell strings, applying a common source line erase voltage to the common source line, applying a bit line erase voltage to a corresponding bit line of each of the memory cell strings, applying a string selection line erase voltage to the string selection transistor of each of the memory cell strings, and applying a ground selection line erase voltage to the ground selection transistor of each of the memory cell strings, Wherein the voltage difference between the bit line erase voltage and the string selection line erase voltage or the voltage difference between the common source line erase voltage and the ground selection line erase voltage is less than or equal to a predetermined voltage difference, and the memory cells in the memory cell string are randomly divided into first type erase bits or second type erase bits.

12. The memory device of claim 11 , wherein the memory controller further performs: Physically uncopyable functional data is correspondingly generated according to the memory cells in the memory cell string that are randomly divided into the first type erasure bits or the second type erasure bits. 13 . The memory device of claim 11 , wherein the memory cells in the memory cell string undergo a gate induced drain leakage current erase operation.

14. The memory device of claim 13, wherein after the GIDLC erase operation, all of the plurality of memory cells in a specific memory cell string are the first type erased bits, or all of the plurality of memory cells in a specific memory cell string are the second type erased bits.

15. The memory device of claim 11, wherein the memory controller further performs: The memory cell is classified as the first type erased bit or the second type erased bit according to a threshold voltage of the memory cell.

16. The memory device of claim 11, wherein the memory controller further performs: In the case that the memory cell cannot be distinguished as the first type erased bit or the second type erased bit by using the threshold voltage of the memory cell, the memory cell that cannot be distinguished is not used.

17. The memory device of claim 11, wherein the predetermined voltage difference has a voltage range of 0 volts to 5 volts.

18. The memory device of claim 11, wherein the memory controller further performs: The memory cells in the memory block are programmed before the memory cells in the memory cell string are randomly distinguished as the first type erased bits or the second type erased bits.

19. The memory device according to claim 11, wherein one page in the memory block is composed of the plurality of memory cell strings connected to a corresponding one of the plurality of word lines in the memory cell strings, and The memory controller further performs: programming all memory cells in a specific page of the plurality of pages before causing the memory cells in the memory cell string to be randomly distinguished as the first type erased bits or the second type erased bits; determining whether the number of program-erase times of the specific page exceeds a wear threshold; and When the number of program-erase times of the specific page exceeds a wear threshold, another page of the plurality of pages is used as the specific page.

20. The memory device of claim 11, wherein the word line erase voltage is 0 volts, the common source line erase voltage is 20V, and the bit line erase voltage is 20V.

Images