Improved fan-out type wafer level packaging process applied to high-performance W wave band

Abstract

The invention relates to the technical field of semiconductor packaging, in particular to an improved fan-out wafer level packaging process applied to a high-performance W wave band, which comprises the following steps of: forming a first surface supporting carrier plate, and laying a double-sided adhesive film on the first surface supporting carrier plate to provide support for subsequent chip fixation; forming a cavity between the chip area and the medium area, and forming an electroplating area at a required position to prevent the air bridge structure from collapsing; the chip is fixed on the supporting carrier plate through a flip chip; the chip is fixed by using a film pressing technology, so that the stability of the chip in a subsequent process is ensured; a cavity is formed between a chip area and a dielectric area, so that collapse of an air bridge structure is prevented, structural stability is improved, intrinsic performance deterioration of the transistor is prevented, dielectric is not attached to the surface of an active area, intrinsic performance deterioration of the transistor is prevented, and stable performance of a device is ensured. And electrical connection of the upper and lower parts of the package is realized through a glass perforation technology, so that the electric heating performance is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor packaging technology, and in particular to an improved fan-out wafer-level packaging process for high-performance W-band applications. Background Art

[0002] With the development of wireless communication technology, especially the increasing application of high-frequency bands (such as W-band), the demand for high-performance packaging technology is increasing. The application of W-band (75-110GHz) covers many fields such as high-speed wireless communication and millimeter-wave radar, which puts higher requirements on packaging technology. Traditional packaging technology faces many challenges in high-frequency band applications, especially under the flip-chip process, there are several major problems:

[0003] The air bridge structure is prone to collapse: In the flip chip process, the air bridge structure is prone to collapse during the processing, affecting the quality and performance of the package.

[0004] The dielectric cannot adhere to the surface of the active area: Since the dielectric cannot adhere to the surface of the active area, the intrinsic performance of the transistor may deteriorate, affecting the reliability and life of the device.

[0005] Poor device electrothermal performance: In high-frequency applications, poor device electrothermal performance and unsatisfactory heat dissipation may lead to excessive temperature rise, affecting the device's operating stability and reliability.

[0006] Difficulty in testing chip yield at the mass production level: During the mass production process, the chip yield testing method is not mature enough, resulting in low production efficiency and increased production costs.

[0007] Poor packaging consistency: The consistency of packaged chips is poor, which affects the quality of the final product and may lead to large performance differences between batches. Summary of the invention

[0008] 1. Technical issues to be solved

[0009] In view of the deficiencies in the prior art, the present invention provides an improved fan-out wafer-level packaging process for high-performance W-band applications.

[0010] (II) Technical solution

[0011] To achieve the above object, the present invention provides the following technical solution: An improved fan-out wafer-level packaging process for high-performance W-band applications of the present invention comprises the following steps:

[0012] Step 1: Form the first support carrier and lay a double-sided adhesive film on it to provide support for subsequent chip fixation;

[0013] Step 2: Formation of cavity and electroplating area: a cavity is formed between the chip area and the dielectric area to prevent the collapse of the air bridge structure, and an electroplating area is formed at the required position;

[0014] Step 3: Flip-chip mounting, fix the chip on the support substrate by flip-chip mounting;

[0015] Step 4: Fix the chip by lamination. Use lamination technology to fix the chip to ensure the stability of the chip in subsequent processes.

[0016] Step 5: Open the glass hole. Use glass perforation technology (TGV) to open a hole in the glass interposer area to achieve electrical connection between the positive and negative sides of the chip, and perform electrical heat treatment on the back of the chip.

[0017] Step 6: Thin-layer metal electroplating: Perform thin-layer metal electroplating at the location where electroplating is required to prepare for subsequent processes;

[0018] Step 7: Apply glue, apply an appropriate glue layer to prepare for the next step of photolithography;

[0019] Step 8: Photolithography, electroplating, stripping and etching seeds, completing the photolithography, electroplating, stripping and etching seed steps of the backside redistribution layer (RDL);

[0020] Step 9: Fix by lamination, use lamination technology again to ensure the stability of the chip during the process;

[0021] Step 10: Form a support carrier on the second side of the flip chip to prepare for subsequent processing;

[0022] Step 11: Unlock the first side of the chip, perform temporary bonding, and perform photolithography opening of the first side film;

[0023] Step 12: Electroplating RDL on the front side of the chip: Electroplating of the redistribution layer (RDL) on the front side of the chip;

[0024] Step 13: Passivation of the front surface of the chip: passivation of the front surface of the chip is performed to protect the chip and improve reliability;

[0025] Step 14: Re-form the support carrier on the first side of the chip, and complete the circuit design and electrical connection processing on the first side of the chip;

[0026] Step 15: Unlock the second side of the chip and make a laser opening at the ball planting location;

[0027] Step 16: Form pins at the ball implantation position and undo the first side of the chip to complete the chip implantation.

[0028] Preferably, it includes a packaged chip G, which includes a chip A, packaged dielectric layers B, C, D, E, and ball pins F, the dielectric layer B wraps the chip A, the dielectric layer C is packaged at the bottom of the chip A and the dielectric layer B, the dielectric layer D is packaged at the top of the chip A and the dielectric layer B, the dielectric layer E is packaged at the top of the dielectric layer D, a rewiring layer is electroplated between the packaged dielectric layers B, C, D, E, and the ball pins F are embedded in the dielectric layer C.

[0029] Further preferably, a cavity is provided between the dielectric layer D and the chip A.

[0030] Again preferably, the dielectric layer B is a glass intermediary layer, the dielectric layer C is a second-side supporting carrier, the dielectric layer D is a first supporting carrier, and the dielectric layer E is a double-sided adhesive film.

[0031] Preferably, the packaged chip G is a fan-shaped structure.

[0032] (III) Beneficial effects

[0033] Compared with the prior art, the present invention provides an improved fan-out wafer-level packaging process for high-performance W-band applications, which has the following beneficial effects:

[0034] Preventing the collapse of the air bridge structure: By forming a cavity between the chip area and the dielectric area, the collapse of the air bridge structure is prevented and the structural stability is improved.

[0035] Preventing the intrinsic performance of transistors from deteriorating: By not attaching dielectrics to the surface of the active area, the intrinsic performance of transistors can be prevented from deteriorating, ensuring stable device performance.

[0036] Improved electrical and thermal performance: Through-glass via (TGV) technology is used to achieve electrical connections between the upper and lower parts of the package, improving electrical and thermal performance.

[0037] Improve chip yield: Improve chip yield through precise process step control.

[0038] Improve the consistency of packaged chips: Ensure the consistency and reliability of packaged chips through standardized process flow. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 This is a structural diagram of the improved fan-out wafer-level package of the present invention;

[0040] Figure 2 It is a schematic diagram of the process steps 1 to 4 of the invention;

[0041] Figure 3 It is a schematic diagram of the fifth to eighth process steps of the invention;

[0042] Figure 4It is a schematic diagram of the ninth to tenth process steps of the invention;

[0043] Figure 5 It is a schematic diagram of the process steps 11 to 14 of the invention;

[0044] Figure 6 It is a schematic diagram of the fifteenth to sixteenth process steps of the invention. DETAILED DESCRIPTION

[0045] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0046] See also Figure 1-6 The improved fan-out wafer-level packaging process for high-performance W-band applications of the present invention realizes the packaging of high-performance chips through a series of steps, specifically including the following steps:

[0047] The first step is to form a first support carrier and lay a double-sided adhesive film thereon: a first support carrier is formed and a double-sided adhesive film is laid thereon to provide support for subsequent chip fixation.

[0048] The second step is the formation of cavity and electroplating area: a cavity is formed between the chip area and the dielectric area to prevent the collapse of the air bridge structure, and an electroplating area is formed at the required position.

[0049] The third step is flip-chip mounting: fix the chip on the supporting carrier by flip-chip mounting.

[0050] The fourth step is to fix the chip by lamination: Use lamination technology to fix the chip to ensure the stability of the chip in subsequent processes.

[0051] The fifth step is glass drilling: drilling holes in the glass interposer area through glass perforation technology (TGV) to achieve electrical connection between the positive and negative sides of the chip, and perform electrical heat treatment on the back of the chip.

[0052] Step 6: Thin layer metal electroplating: Perform thin layer metal electroplating at the location where electroplating is required to prepare for subsequent processes.

[0053] Step 7: Glue coating: Apply an appropriate glue layer to prepare for the next step of photolithography.

[0054] Step 8. Photolithography, electroplating, stripping and seed etching: Complete the photolithography, electroplating, stripping and seed etching steps of the backside redistribution layer (RDL).

[0055] Step 9: Fix by lamination: Use lamination technology again to ensure the stability of the chip during the process.

[0056] Step 10: Forming a support carrier on the second side of the flip chip: forming a support carrier on the second side of the flip chip to prepare for subsequent processing.

[0057] Step 11. Unlock the first side of the chip and perform temporary bonding and photolithography opening of the film on the first side: Unlock the first side of the chip and perform temporary bonding and photolithography opening of the film on the first side.

[0058] Step 12: Electroplating RDL on the front side of the chip: Electroplating of the redistribution layer (RDL) is performed on the front side of the chip.

[0059] Step 13: Surface passivation on the front side of the chip: Perform surface passivation on the front side of the chip to protect the chip and improve reliability.

[0060] Step 14: Re-formation of the support carrier on the first side of the chip: completing the circuit design and electrical connection processing on the first side of the chip.

[0061] Step 15. Unlock the second side of the chip and make a laser opening at the ball planting location: Unlock the second side of the chip and make a laser opening at the ball planting location.

[0062] Step 16: Planting balls to form pins and unlock the first side of the chip: Form pins at the ball planting position and unlock the first side of the chip to complete the chip planting work.

[0063] Working principles of each preferred technical solution

[0064] The structure of packaged chip G:

[0065] It includes chip A, packaging medium layers B, C, D, E, and ball implant pin F.

[0066] The dielectric layer B wraps the chip A.

[0067] The dielectric layer C is packaged on the bottom of the chip A and the dielectric layer B.

[0068] The dielectric layer D is packaged on top of the chip A and the dielectric layer B.

[0069] The dielectric layer E is encapsulated on top of the dielectric layer D.

[0070] The rewiring layer is electroplated between the package dielectric layers B, C, D, and E.

[0071] The ball implant pin F is embedded in the dielectric layer C.

[0072] Cavity Design:

[0073] A cavity is provided between the dielectric layer D and the chip A to prevent the air bridge structure from collapsing.

[0074] Specific materials of dielectric layer:

[0075] The dielectric layer B is a glass intermediate layer.

[0076] The dielectric layer C is the second surface supporting the carrier.

[0077] The dielectric layer D is the first supporting substrate.

[0078] The dielectric layer E is a double-sided adhesive film.

[0079] The shape of packaged chip G:

[0080] The packaged chip G has a fan-shaped structure, which is convenient for subsequent packaging and connection.

[0081] Comprehensive working principle

[0082] Through the above steps and technical solutions, the packaging process of the present invention can effectively solve several thorny problems faced in W-band multi-chip packaging:

[0083] Structural stability and reliability

[0084] Cavity design: By forming a cavity between the chip area and the dielectric area, the collapse of the air bridge structure is effectively prevented, thereby improving the stability and reliability of the packaging structure.

[0085] Glass perforation technology (TGV): The glass interposer area is opened with glass perforation technology to achieve electrical connection between the positive and negative sides of the chip, and the back of the chip is subjected to electrothermal treatment, which improves the reliability and electrothermal performance of the overall structure.

[0086] Electrical and thermal performance

[0087] Electrical connection: Through-glass via (TGV) technology is used to achieve electrical connection between the positive and negative sides of the chip, ensuring the electrical performance after packaging.

[0088] Heat dissipation performance: Through precise electrothermal treatment, the heat dissipation performance of the back of the chip is ensured, which improves the heat dissipation effect of the packaged chip and is suitable for high-frequency (DC~110G) applications.

[0089] Process accuracy and yield

[0090] Lamination fixation: Through two lamination fixation technologies, the stability of the chip in subsequent processes is ensured, reducing the defect rate caused by movement.

[0091] Precision plating: Through the steps of thin-layer metal plating, photolithography, electroplating, stripping and etching seeds, the precise formation of the redistribution layer (RDL) is ensured, improving the process accuracy.

[0092] Surface passivation: By performing surface passivation on the front side of the chip, the chip is protected and reliability is improved, reducing the risk of failure caused by environmental factors.

[0093] Functionality and compatibility

[0094] Redistribution layer (RDL): The redistribution layer is electroplated between the package dielectric layers to improve the electrical connection performance of the package and enhance the functionality of the packaged chip.

[0095] Ball implant pins: Ball implant pins are embedded in the dielectric layer C, providing a reliable pin structure for subsequent welding and connection, and enhancing the compatibility of the packaged chip.

[0096] Productivity and consistency

[0097] Standardized process: Through standardized process flow, the consistency and reliability of packaged chips are ensured, and production efficiency is improved.

[0098] Multi-layer support: The dielectric layers B, C, D, and E are the glass interposer, the second-side support substrate, the first support substrate, and the double-sided adhesive film, respectively. The multi-layer support structure ensures the stability and consistency of the chip during the packaging process.

[0099] Application

[0100] Applicable to a variety of chips: The improved FOWLP process is suitable for double-sided packaging of GaAs, GaN and silicon-based chips, expanding the scope of application.

[0101] Cost-effectiveness

[0102] Simplify the process: By optimizing the process steps, unnecessary complex processes are reduced, production costs are reduced, and economic benefits are improved.

[0103] Structural Optimization

[0104] Fan-shaped structure: The packaged chip G has a fan-shaped structure, which is convenient for subsequent packaging and connection, and improves the flexibility and practicality of the packaging.

[0105] Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. An improved fan-out wafer-level packaging process for high-performance W-band applications, characterized in that: The following steps are involved: Step 1: Form the first support carrier and lay a double-sided adhesive film on it to provide support for subsequent chip fixation; Step 2: Formation of cavity and electroplating area: a cavity is formed between the chip area and the dielectric area to prevent the collapse of the air bridge structure, and an electroplating area is formed at the required position; Step 3: Flip-chip mounting, fix the chip on the support substrate by flip-chip mounting; Step 4: Fix the chip by lamination. Use lamination technology to fix the chip to ensure the stability of the chip in subsequent processes. Step 5: Opening a hole in the glass interposer area through glass perforation technology (TGV) to achieve electrical connection between the positive and negative sides of the chip, and perform electrical heat treatment on the back of the chip; Step 6: Thin-layer metal electroplating: Perform thin-layer metal electroplating at the location where electroplating is required to prepare for subsequent processes; Step 7: Apply glue, apply an appropriate glue layer to prepare for the next step of photolithography; Step 8: Photolithography, electroplating, stripping and etching seeds, completing the photolithography, electroplating, stripping and etching seed steps of the backside redistribution layer (RDL); Step 9: Lamination fixation, use lamination technology again to fix the chip to ensure the stability of the chip during the process; Step 10: Form a support carrier on the second side of the flip chip to prepare for subsequent processing; Step 11: Unlock the first side of the chip, perform temporary bonding, and perform photolithography opening of the first side film; Step 12: Electroplating RDL on the front side of the chip: Electroplating of the redistribution layer (RDL) on the front side of the chip; Step 13: Passivation of the front surface of the chip: passivation of the front surface of the chip is performed to protect the chip and improve reliability; Step 14: Re-form the support carrier on the first side of the chip, and complete the circuit design and electrical connection processing on the first side of the chip; Step 15: Unlock the second side of the chip and make a laser opening at the ball planting location; Step 16: Form pins at the ball implantation position and untie the first side of the chip to complete the chip implantation.

2. The improved fan-out wafer-level packaging process for high-performance W-band applications according to claim 1, characterized in that: The invention comprises a packaged chip G, wherein the packaged chip G comprises a chip A, packaged dielectric layers B, C, D, E, and ball-planting pins F, wherein the dielectric layer B wraps the chip A, the dielectric layer C is packaged at the bottom of the chip A and the dielectric layer B, the dielectric layer D is packaged at the top of the chip A and the dielectric layer B, the dielectric layer E is packaged at the top of the dielectric layer D, a rewiring layer is electroplated between the packaged dielectric layers B, C, D, E, and the ball-planting pins F are embedded in the dielectric layer C.

3. The improved fan-out wafer-level packaging process for high-performance W-band applications according to claim 2, characterized in that: A cavity is provided between the dielectric layer D and the chip A.

4. The improved fan-out wafer-level packaging process for high-performance W-band applications according to claim 3, characterized in that: The dielectric layer B is a glass intermediary layer, the dielectric layer C is a second-side supporting carrier, the dielectric layer D is a first supporting carrier, and the dielectric layer E is a double-sided adhesive film.

5. The improved fan-out wafer-level packaging process for high-performance W-band applications according to claim 4, characterized in that: The packaged chip G is a fan-shaped structure.

Images