Error calibration method suitable for assembly line ADC

Abstract

The invention discloses an error calibration method applicable to an assembly line ADC (Analog to Digital Converter), which belongs to the technical field of digital simulation and comprises the following steps of: acquiring a last beat of pseudo-random noise sequence dPN [n-1]; wherein pseudo-random noise is added to the input of the sub-DAC of each pipeline level; on the basis of the pseudo-random noise sequence dPN [n-1] of the previous beat, an inter-stage gain error coefficient e [n] of the current beat is obtained through calculation; and realizing inter-stage gain error calibration based on the inter-stage gain error coefficient e [n] of the current beat and a digital output DB [n] obtained through pipeline stage conversion of a post-stage of the current beat. Obtaining a last beat of pseudo-random noise sequence dPN [n-2]; calculating a memory effect error coefficient CM [n] of the current beat based on the pseudo-random noise sequence dPN [n-2] of the previous beat; memory effect error calibration is achieved based on the current-beat memory effect error coefficient CM [n] and the digital output DB [n] obtained through current-beat post-stage pipeline stage conversion. According to the invention, better inter-stage gain calibration can be realized, and meanwhile, better memory effect calibration can be realized in a digital domain without too much change of the circuit.

Description

Technical Field

[0001] The present invention relates to the field of digital simulation technology, and more particularly to an error calibration method suitable for pipeline ADC. Background Art

[0002] Analog-to-digital converters (ADCs) are used to convert analog signals into digital signals and are widely used in wireless communications, high-end test equipment, image and speech processing, and other fields. With the development of advanced processes and design technologies, as well as the expansion of application scenarios, the demand for high-speed, high-precision ADCs is becoming increasingly significant. Pipeline ADCs can achieve a good compromise between speed and accuracy, so pipelines or pipeline-time interleaving architectures are generally used for ultra-high-speed and high-precision ADCs. Figure 1 The block diagram of the sub-Pipelined ADC in the channel is given. The basic principle is to distribute the pressure of high-resolution analog-to-digital conversion to each pipeline stage. Each pipeline stage successively analyzes a small number of bits, and multiple pipeline stages work continuously to achieve high-resolution analog-to-digital conversion, where the most significant bit is analyzed by the first stage in the pipeline, and the least significant bit is analyzed by the last stage in the pipeline.

[0003] Pipelined ADC processes the input analog signal serially through each pipeline stage, so it can achieve fast conversion with high throughput. However, the disadvantage of this architecture is that accurate analog signal processing must be performed at each pipeline stage to ensure that the signal is not distorted in the subsequent pipeline stages.

[0004] For high-speed and high-precision pipelined ADCs, interstage gain errors will seriously affect the linearity of the overall ADC. Therefore, it is very necessary to calibrate them accordingly. The interstage gain of pipelined ADCs is affected by both capacitor mismatch errors and the limited open-loop gain of the op amp. Since capacitor mismatch is caused by non-ideal factors such as process, it is a fixed error. For the change in interstage gain caused by capacitor mismatch, the corresponding error extraction and calibration can be achieved by using a foreground calibration similar to capacitor mismatch calibration. However, the limited open-loop gain of the op amp will be affected by temperature and voltage changes when the ADC is working, thereby affecting the interstage gain. Therefore, for the interstage gain error caused by the limited open-loop gain of the op amp, background calibration is required to extract and correct the error in real time. At the same time, with the continuous improvement of ADC speed and accuracy, the impact of memory effect on ADC is becoming more and more obvious, and the calibration of memory effect of pipelined ADC has also entered the researchers' sight.

[0005] Therefore, how to provide an error calibration method suitable for pipeline ADC, which can calibrate inter-stage gain error and memory effect error, is a problem that technical personnel in this field need to solve urgently. Summary of the invention

[0006] In view of this, an object of the present invention is to provide an error calibration method suitable for pipeline ADC.

[0007] In order to achieve the above object, the present invention adopts the following technical solution:

[0008] An error calibration method suitable for pipeline ADC includes the following steps:

[0009] Get the previous pseudo-random noise sequence d PN [n-1]; wherein pseudo-random noise is added to the input of the sub-DAC of each pipeline stage;

[0010] Based on the previous pseudo-random noise sequence d PN [n-1] calculates the inter-stage gain error coefficient e[n] of this beat;

[0011] Based on the inter-stage gain error coefficient e[n] of the current beat and the digital output D obtained by the pipeline conversion of the subsequent stage of the current beat B [n] Implement inter-stage gain error calibration.

[0012] Preferably, the error calibration method further comprises the following steps:

[0013] Get the pseudo-random noise sequence d of the previous beat PN [n-2];

[0014] Based on the previous pseudo-random noise sequence d PN [n-2] Calculate the memory effect error coefficient C of this shot M [n];

[0015] Based on the memory effect error coefficient C M [n] and the digital output D obtained by the pipeline conversion of the latter stage of the beat B [n] Implement memory effect error calibration.

[0016] Preferably, the calibrated post-stage pipeline digital output D of the previous beat is B_cal [n-1] and the previous pseudo-random noise sequence d PN [n-1] is input to the correlator for correlation operation to obtain the inter-stage gain error coefficient e[n] of this beat.

[0017] Preferably, the inter-stage gain error coefficient e[n] of the current beat is calculated using the following formula:

[0018] e[n]=e[n-1]+d PN [n-1]×D B_cal [n-1];

[0019] Where e[n-1] represents the inter-stage gain error coefficient of the previous beat; d PN [n-1] represents the previous pseudo-random noise sequence d PN [n-1]; D B_cal [n-1] represents the digital output of the next pipeline stage after the inter-stage gain error calibration of the previous beat.

[0020] Preferably, inter-stage gain calibration is achieved based on the following formula:

[0021] D B_cal [n] = D B [n]×(1-e[n] / G ideal )+D PN [n];

[0022] D PN [n] = d PN [n]*W PN ;

[0023] Among them, D B_cal [n] represents the digital output of the subsequent pipeline stage after the inter-stage gain error calibration of this beat; e[n] represents the inter-stage gain error coefficient of this beat; G ideal represents the ideal inter-stage gain coefficient; d PN [n] represents the pseudo-random noise sequence of this beat; W PN represents the pseudo-random noise sequence d PN The weight of [n].

[0024] Preferably, the digital output D of the last stage pipeline stage is R [n-1] and the previous pseudo-random noise sequence d PN [n-2] is input to the correlator for correlation operation to obtain the memory effect error coefficient C of the current shot M [n].

[0025] Preferably, the digital output D of the last stage pipeline stage R The calculation formula for [n-1] is:

[0026] D R [n-1] = D B [n-1]-d PN [n-1]*C M [n-1];

[0027] Among them, D B [n-1] represents the digital output obtained by the pipeline conversion of the last beat; d P N [n-1] represents the previous pseudo-random noise sequence; C M [n-1] represents the memory effect error coefficient of the previous beat.

[0028] Preferably, the memory effect error coefficient C of the current shot is calculated based on the following formula: M [n]:

[0029] C M [n] = C M [n-1]+d PN [n-2]*D R [n-1];

[0030] D R [n-1] = D B [n-1]-d PN [n-1]*C M [n-1];

[0031] Among them, C M [n-1] represents the memory effect error coefficient of the previous shot; d PN [n-2] represents the pseudo-random noise sequence of the previous beat; D R [n-1] indicates the digital output of the last stage pipeline; D B [n-1] represents the digital output obtained by the pipeline conversion of the previous beat; d PN [n-1] represents the previous pseudo-random noise sequence.

[0032] Preferably, the memory effect error calibration is implemented based on the following formula:

[0033] D B_cal [n] = D B [n]+D PN [n]+d PN [n]×C M [n]+α×C M [n]×d i [n-1];

[0034] D PN [n] = d PN [n]*W PN

[0035] Among them, D B [n] represents the digital output obtained by the pipeline conversion of the next stage of this beat; d PN [n] represents the pseudo-random noise sequence of this beat; W PN represents the pseudo-random noise sequence d PN The weight of [n]; C M [n] represents the memory effect error coefficient of this shot; α represents the equivalent coefficient of the memory effect error of the sampling capacitor; d i [n-1] represents the digital code obtained by the conversion of the pipeline stage in the previous beat.

[0036] An electronic device comprises a memory, a processor and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, the error calibration method applicable to a pipeline ADC is implemented.

[0037] It can be seen from the above technical solutions that, compared with the prior art, the present invention discloses an error calibration method suitable for pipeline ADC, which can achieve the following beneficial technical effects:

[0038] 1) The present invention can achieve better inter-stage gain calibration without making too many changes to the circuit itself, and can achieve better memory effect calibration in the digital domain.

[0039] 2) The present invention can effectively disperse the spectral spurious of the pipeline ADC and improve its overall spurious-free dynamic range.

[0040] 3) The present invention does not require continuous multiplication and has low hardware overhead. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.

[0042] Figure 1 The overall block diagram of the Pipelined ADC provided by the present invention;

[0043] Figure 2 A simulation circuit diagram for adding pseudo-random noise to the input of a sub-DAC of a certain pipeline stage provided by the present invention;

[0044] Figure 3 A logic block diagram of an error calibration method provided by an embodiment of the present invention;

[0045] Figure 4 A logic block diagram of an inter-stage gain error calibration method provided by a certain embodiment of the present invention;

[0046] Figure 5 A logic block diagram of a memory error calibration method provided by an embodiment of the present invention;

[0047] Figure 6 A simulated spectrum diagram before and after calibration provided by an embodiment of the present invention;

[0048] Figure 7 A schematic diagram of the structure of an electronic device provided in one embodiment of the present invention. DETAILED DESCRIPTION

[0049] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0050] like Figure 2 As shown, it shows an analog circuit diagram of adding pseudo-random noise to the input of a sub-DAC of a certain pipeline stage of the present invention. First, a pseudo-random noise sequence needs to be implemented in the analog circuit and then added to the input of the sub-DAC of the pipeline stage. The pseudo-random noise sequence passes through an inter-stage gain module containing an actual inter-stage gain coefficient and is quantized by a post-stage ADC. Finally, a digital code corresponding to the added pseudo-random noise sequence needs to be added to the output of the post-stage ADC in the digital domain.

[0051] It can be understood that: when performing inter-stage gain error calibration, ignoring the memory effect, the digital output of the subsequent ADC is:

[0052] D B =(Q N -d PN )×G+O N ;

[0053] Where D B is the digital output obtained by the subsequent pipeline conversion, d PN is a pseudo-random noise sequence, G is the actual inter-stage gain coefficient of the pipeline stage, Q N is the quantization noise of this pipeline stage, O N All other noise sources are included, such as thermal noise and quantization noise of the subsequent ADC. If the estimated interstage gain coefficient G es If it is not equal to the actual inter-stage gain coefficient G, the added pseudo-random noise sequence will not be completely eliminated in the digital domain, that is,

[0054] D B '=(Q N -d PN )×G+O N +d PN ×G es

[0055] =Q N ×G+d PN ×(G es -G)+O N ;

[0056] DB’ With the pseudo-random noise sequence d PN By performing relevant operations, the inter-stage gain error coefficient e can be obtained:

[0057]

[0058] in Related operation symbols. Ideally, d PN With Q N and O N are all uncorrelated. As the length of the pseudo-random noise sequence increases, their correlation operation results will approach zero, so the actual inter-stage gain coefficient G can be expressed as:

[0059] G=G ideal -e;

[0060] Therefore, the actual inter-stage gain can be extracted.

[0061] The embodiment of the present invention discloses an error calibration method applicable to a pipeline ADC, comprising the following steps:

[0062] like Figure 3-Figure 5 As shown:

[0063] 1) Get the previous pseudo-random noise sequence d PN [n-1]; wherein pseudo-random noise is added to the input of the sub-DAC of each pipeline stage;

[0064] 2) Based on the previous pseudo-random noise sequence d PN [n-1] calculates the inter-stage gain error coefficient e[n] of this beat;

[0065] In one embodiment, the calibrated post-stage pipeline digital output D of the previous beat is B_cal [n-1] and the previous pseudo-random noise sequence d PN [n-1] is input to the correlator for correlation operation to obtain the inter-stage gain error coefficient e[n] of this beat.

[0066] In one embodiment, the inter-stage gain error coefficient e[n] of the current beat is calculated using the following formula:

[0067] e[n]=e[n-1]+d PN [n-1]×D B_cal [n-1];

[0068] Where e[n-1] represents the inter-stage gain error coefficient of the previous beat; d PN [n-1] represents the previous pseudo-random noise sequence d PN [n-1]; D B_cal[n-1] represents the digital output of the next pipeline stage after the inter-stage gain error calibration of the previous beat.

[0069] It is understandable that the inter-stage gain error coefficient can be estimated by using correlation operation. However, correlation operation will also bring corresponding problems, including the problems of convergence speed and accuracy. Here, LMS algorithm is used to extract the inter-stage gain error coefficient.

[0070] 3) Based on the inter-stage gain error coefficient e[n] of the current beat and the digital output D obtained by the subsequent pipeline conversion of the current beat B [n] Implement inter-stage gain error calibration.

[0071] In one embodiment, inter-stage gain calibration is implemented based on the following formula:

[0072] D B_cal [n] = D B [n]×(1-e[n] / G ideal )+D PN [n];

[0073] D PN [n] = d PN [n]*W PN ;

[0074] Among them, D B_cal [n] represents the digital output of the subsequent pipeline stage after the inter-stage gain error calibration of this beat; e[n] represents the inter-stage gain error coefficient of this beat; G ideal represents the ideal inter-stage gain coefficient; d PN [n] represents the pseudo-random noise sequence of this beat; W PN represents the pseudo-random noise sequence d PN The weight of [n].

[0075] In one embodiment, the error calibration method further includes the following steps:

[0076] It should be noted that the pipeline ADC will also have memory effects due to factors such as incomplete resetting of the sampling capacitor. The main manifestation of the memory effect is that the value of the previous sampling conversion of a certain pipeline stage of the pipeline ADC will affect the current sampling conversion of the pipeline stage, thereby affecting its overall linearity. Combined with the multi-level random dither technology proposed in the present invention, the calibration of the memory effect can be achieved while calibrating the inter-stage gain error basis.

[0077] The specific steps are as follows:

[0078] 1) Get the pseudo-random noise sequence d of the previous beat PN [n-2];

[0079] 2) Based on the previous pseudo-random noise sequence d PN [n-2] Calculate the memory effect error coefficient C of this shot M [n];

[0080] In one embodiment, the digital output D of the last stage pipeline is R [n-1] and the previous pseudo-random noise sequence d PN [n-2] is input to the correlator for correlation operation to obtain the memory effect error coefficient C of the current shot M [n].

[0081] In one embodiment, the digital output D of the last stage pipeline stage is R The calculation formula for [n-1] is:

[0082] D R [n-1] = D B [n-1]-d PN [n-1]*C M [n-1];

[0083] Among them, D B [n-1] represents the digital output obtained by the pipeline conversion of the previous beat; d PN [n-1] represents the previous pseudo-random noise sequence; C M [n-1] represents the memory effect error coefficient of the previous beat.

[0084] In one embodiment, the memory effect error coefficient C of the current shot is calculated based on the following formula: M [n]:

[0085] C M [n] = C M [n-1]+d PN [n-2]*D R [n-1];

[0086] D R [n-1] = D B [n-1]-d PN [n-1]*C M [n-1];

[0087] Among them, C M [n-1] represents the memory effect error coefficient of the previous shot; d PN [n-2] represents the pseudo-random noise sequence of the previous beat; D R [n-1] indicates the digital output of the last stage pipeline; D B [n-1] represents the digital output obtained by the pipeline conversion of the previous beat; d PN[n-1] represents the previous pseudo-random noise sequence.

[0088] It is understandable that the memory effect error coefficient can be estimated by using correlation operation. However, correlation operation will also bring corresponding problems, including the convergence speed and accuracy. Here, LMS algorithm is used to extract the memory effect error coefficient.

[0089] Through the above steps, the memory effect error coefficient caused by the dither capacitance controlled by the PN code can be extracted.

[0090] 3) Based on the memory effect error coefficient C M [n] and the digital output D obtained by the pipeline conversion of the latter stage of the beat B [n] Implement memory effect error calibration.

[0091] In one embodiment, memory effect error calibration is implemented based on the following formula:

[0092] D B_cal [n] = D B [n]+D PN [n]+d PN [n]×C M [n]+α×C M [n]×d i [n-1];

[0093] D PN [n] = d PN [n]*W PN

[0094] Among them, D B [n] represents the digital output obtained by the pipeline conversion of the next stage of this beat; d PN [n] represents the pseudo-random noise sequence of this beat; W PN represents the pseudo-random noise sequence d PN The weight of [n]; C M [n] represents the memory effect error coefficient of this shot; α represents the sampling capacitor memory effect error equivalent coefficient (the degree of memory effect caused by incomplete capacitor reset is proportional to the size of the capacitor. By calculating the size relationship between the sampling capacitor and the dither capacitor, the sampling capacitor memory effect error equivalent coefficient α can be obtained); d i [n-1] represents the digital code obtained by the conversion of the pipeline stage in the previous beat.

[0095] Finally, the method of the present invention was modeled and simulated using Matlab. The spectrum diagrams before and after the inter-stage gain calibration obtained by simulation are shown in Figure 6 The performance comparison before and after calibration is shown in Table 1.

[0096] Table 1 Comparison of simulation performance before and after calibration

[0097] Performance Indicators Before calibration After calibration SNR(dBc) 54.69 79.32 SFDR(dBc) 63.29 88.88 THD(dBc) -66.65 -92.34 ENOB(Bit) 8.748 12.85

[0098] It can be seen from Table 1 that the method of the present invention can significantly improve the performance indicators such as SNR (dBc), SFDR (dBc), THD (dBc) and ENOB (Bit).

[0099] The embodiment of the present invention also discloses a physical structure diagram of an electronic device, such as Figure 7 As shown, the electronic device may include: a processor (processor) 701, a communication interface (Communications Interface) 702, a memory (memory) 703 and a communication bus 704, wherein the processor 701, the communication interface 702, and the memory 703 communicate with each other through the communication bus 704. The processor 701 may call the logic instructions in the memory 703 to execute the above-mentioned error calibration method applicable to the pipeline ADC.

[0100] In addition, the logic instructions in the above-mentioned memory 703 can be implemented in the form of a software functional unit and can be stored in a computer-readable storage medium when it is sold or used as an independent product. Based on such an understanding, the technical solution of the present invention can be essentially or partly embodied in the form of a software product that contributes to the prior art. The computer software product is stored in a storage medium, including several instructions to enable a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in the embodiment of the present invention. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0101] On the other hand, an embodiment of the present invention further provides a computer program product, which includes a computer program. The computer program can be stored on a non-transitory computer-readable storage medium. When the computer program is executed by a processor, the computer can execute the above-mentioned error calibration method applicable to the pipeline ADC.

[0102] In this specification, each embodiment is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part.

[0103] The above description of the disclosed embodiments enables one skilled in the art to implement or use the present invention. Various modifications to these embodiments will be apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An error calibration method suitable for pipeline ADC, characterized in that: The following steps are involved: Get the previous pseudo-random noise sequence d PN [n-1]; wherein pseudo-random noise is added to the input of the sub-DAC of each pipeline stage; Based on the previous pseudo-random noise sequence d PN [n-1] calculates the inter-stage gain error coefficient e[n] of this beat; Based on the inter-stage gain error coefficient e[n] of the current beat and the digital output D obtained by the pipeline conversion of the subsequent stage of the current beat B [n] Implement inter-stage gain error calibration.

2. The error calibration method for pipeline ADC according to claim 1, characterized in that: The following steps are also included: Get the pseudo-random noise sequence d of the previous beat PN [n-2]; Based on the previous pseudo-random noise sequence d PN [n-2] Calculate the memory effect error coefficient C of this shot M [n]; Based on the memory effect error coefficient C M [n] and the digital output D obtained by the pipeline conversion of the latter stage of the beat B [n] Implement memory effect error calibration.

3. The error calibration method for pipeline ADC according to claim 1, characterized in that: The calibrated post-stage digital output D of the previous beat B_cal [n-1] and the previous pseudo-random noise sequence d PN [n-1] is input to the correlator for correlation operation to obtain the inter-stage gain error coefficient e[n] of this beat.

4. The error calibration method for pipeline ADC according to claim 1, characterized in that: The inter-stage gain error coefficient e[n] of this beat is calculated using the following formula: e[n]=e[n-1]+d PN [n-1]×D B_cal [n-1]; Where e[n-1] represents the inter-stage gain error coefficient of the previous beat; d PN [n-1] represents the previous pseudo-random noise sequence d PN [n-1]; D B_cal [n-1] represents the digital output of the next pipeline stage after the inter-stage gain error calibration of the previous beat.

5. The error calibration method for pipeline ADC according to claim 3 or 4, characterized in that: The inter-stage gain calibration is implemented based on the following formula: D B_cal [n]=D B [n]×(1-e[n] / G ideal )+D PN [n]; D PN [n]=d PN [n]*W PN ; Among them, D B_cal [n] represents the digital output of the subsequent pipeline stage after the inter-stage gain error calibration of this beat; e[n] represents the inter-stage gain error coefficient of this beat; G ideal represents the ideal inter-stage gain coefficient; d PN [n] represents the pseudo-random noise sequence of this beat; W PN represents the pseudo-random noise sequence d PN The weight of [n].

6. The error calibration method for pipeline ADC according to claim 2, characterized in that: The digital output D of the last stage pipeline stage R [n-1] and the previous pseudo-random noise sequence d PN [n-2] is input to the correlator for correlation operation to obtain the memory effect error coefficient C of the current shot M [n].

7. The error calibration method for pipeline ADC according to claim 6, characterized in that: The digital output D of the last stage pipeline stage R The calculation formula for [n-1] is: D R [n-1]=D B [n-1]-d PN [n-1]*C M [n-1]; Among them, D B [n-1] represents the digital output obtained by the pipeline conversion of the previous beat; d PN [n-1] represents the previous pseudo-random noise sequence; C M [n-1] represents the memory effect error coefficient of the previous beat.

8. The error calibration method for pipeline ADC according to claim 2, characterized in that: The memory effect error coefficient C of the current shot is calculated based on the following formula M [n]: C M [n]=C M [n-1]+d PN [n-2]*D R [n-1]; D R [n-1]=D B [n-1]-d PN [n-1]*C M [n-1]; Among them, C M [n-1] represents the memory effect error coefficient of the previous shot; d PN [n-2] represents the pseudo-random noise sequence of the previous beat; D R [n-1] indicates the digital output of the last stage pipeline; D B [n-1] represents the digital output obtained by the pipeline conversion of the previous beat; d PN [n-1] represents the pseudo-random noise sequence of the previous beat.

9. An error calibration method suitable for pipeline ADC according to any one of claims 6-7, characterized in that: The memory effect error calibration is implemented based on the following formula: D B_cal [n]=D B [n]+D PN [n]+d PN [n]×C M [n]+α×C M [n]×d i [n-1]; D PN [n]=d PN [n]*W PN Among them, D B [n] represents the digital output obtained by the pipeline conversion of the next stage of this beat; d PN [n] represents the pseudo-random noise sequence of this beat; W PN represents the pseudo-random noise sequence d PN The weight of [n]; C M [n] represents the memory effect error coefficient of this shot; α represents the equivalent coefficient of the memory effect error of the sampling capacitor; d i [n-1] represents the digital code obtained by the conversion of the pipeline stage in the previous beat.

10. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: When the processor executes the computer program, the error calibration method applicable to the pipeline ADC as claimed in any one of claims 1 to 9 is implemented.

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