Partitioned dormancy type resolution-adjustable capacitor array analog-to-digital converter and method thereof

Abstract

The partition dormancy type resolution-adjustable capacitor array analog-to-digital converter comprises a normal-phase conversion capacitor array which comprises a normal-phase high-capacitor array and a normal-phase low-capacitor array; the anti-phase conversion capacitor array comprises an anti-phase high capacitor array and an anti-phase low capacitor array; the sampling module is used for carrying out initial sampling on the input signals from the top plates of all the capacitor units; the comparator is used for comparing an input signal or the states of the normal-phase conversion capacitor array and the reverse-phase conversion capacitor array and outputting bit data; the shift register is used for storing bit data; and the state switching module is used for being matched with the bridge switch to control circuit connection states of all the capacitor units, and the circuit connection states comprise a connection state and a voltage state. According to the invention, the energy consumption required by the capacitor unit is reduced through a partition dormancy mode, and the number of unit capacitors is reduced, so that the overall power consumption of the analog-to-digital converter is reduced.

Description

Technical Field

[0001] The invention relates to the field of analog-to-digital converters, in particular to a partitioned dormant capacitor array analog-to-digital converter with adjustable resolution and a method thereof. Background Art

[0002] An analog-to-digital converter is an electronic component that converts analog signals into digital signals. Analog-to-digital converters can generally be divided into two types: direct and indirect. Among direct analog-to-digital converters, the successive approximation analog-to-digital converter is a type with medium resolution, medium speed and simple structure.

[0003] The successive approximation analog-to-digital converter has the advantages of high degree of digitization and low power consumption. Specifically, the basic structure of the successive approximation analog-to-digital converter only includes a shift register, a comparator and a capacitor array, and does not require a gain circuit. Therefore, it can be used in low-power IoT fields such as sensors, portable devices and biological signal acquisition.

[0004] However, as the process size of electronic components in the prior art gradually decreases, the proportion of power consumption of digital circuits continues to decrease, while the power consumption of approximation analog-to-digital converters of pure analog circuits is difficult to reduce with the advancement of technology, which limits the scope of application of approximation analog-to-digital converters. Summary of the invention

[0005] In order to address the deficiencies in the prior art, the present invention provides a partitioned sleep-type adjustable-resolution capacitor array analog-to-digital converter and a method thereof, which reduces the energy consumption required for capacitor units and the number of unit capacitors through partitioned sleep, thereby reducing the overall power consumption of the analog-to-digital converter.

[0006] In order to achieve the above object, the specific scheme adopted by the present invention is: A partitioned dormant capacitor array analog-to-digital converter with adjustable resolution, comprising: A positive phase conversion capacitor array, including a positive phase high capacitance array and a positive phase low capacitance array; An inverting conversion capacitor array, including an inverting high capacitance array and an inverting low capacitance array; The positive phase high capacitance array, the positive phase low capacitance array, the negative phase high capacitance array and the negative phase low capacitance array all include a plurality of capacitance units arranged in sequence, and a bridge switch is provided between two adjacent capacitance units; Among the plurality of capacitor units arranged in sequence, the first capacitor unit includes two unit capacitors and one extended capacitor, and the two unit capacitors are connected in parallel and in series with the extended capacitor, and the capacitance of the extended capacitor is twice that of the unit capacitor, the second capacitor unit includes one unit capacitor, and starting from the third capacitor unit, the subsequent capacitor unit includes the entirety of the previous capacitor unit and a high-value capacitor whose capacitance is equal to the total capacitance of the previous capacitor unit; A sampling module, used for initially sampling input signals from the top plates of all capacitor units; A comparator, for comparing an input signal or the state of a positive-phase conversion capacitor array and a negative-phase conversion capacitor array and outputting bit data; Shift registers, used to store bit data; The state switching module is used to cooperate with the bridge switch to control the circuit connection state of all capacitor units, and the circuit connection state includes a connection state and a voltage state.

[0007] Preferably, the positive phase high capacitance array, the positive phase low capacitance array, the negative phase high capacitance array and the negative phase low capacitance array each include N-3 capacitance units arranged in sequence, wherein N is the number of bits of the analog-to-digital converter.

[0008] Preferably, the analog-to-digital converter further includes two power supply modules, the state switching module includes a plurality of state switching units, and the power supply modules are correspondingly connected to the capacitor units via the state switching units.

[0009] Preferably, the state switching unit includes a plurality of switching switches, and the switching switches are correspondingly connected to the capacitors in the capacitor unit.

[0010] Preferably, the power supply module includes a ground terminal gnd, a reference voltage terminal V ref and common mode voltage terminal V cm .

[0011] A partitioned dormant capacitor array analog-to-digital conversion method with adjustable resolution is based on the above-mentioned partitioned dormant capacitor array analog-to-digital converter with adjustable resolution, and the method comprises the following steps: Using the sampling module to perform initial sampling on the input signal; The circuit connection states of all the capacitor units are adjusted for the first time, so that the first capacitor unit is connected to the comparator, and the comparator performs a first comparison on the input signal and outputs the bit data D0; Based on D0, the circuit connection state of the capacitor unit is adjusted for the second time, the voltage state of the first capacitor unit is changed, and after the adjustment, the comparator performs a second comparison and outputs the bit data D1; Based on D1, the voltage states of the capacitor units in the positive phase low capacitance array and the negative phase low capacitance array are adjusted for the third time, and after the adjustment, the comparator performs a third comparison and outputs the bit data D2; The circuit connection states of all the capacitor units are adjusted for the fourth time based on D0, D1 and D2, and after the adjustment, the comparator performs the fourth comparison and outputs the bit data D3; The circuit connection states of all the capacitor units are adjusted for the fifth time based on D2 and D3, and after the adjustment, the comparator performs the fifth comparison and outputs the bit data D4; Based on D2 and D n-2 The circuit connection state of all capacitor units is adjusted for the nth time, and after the adjustment, the comparator performs the nth comparison and outputs the bit data D n-1 , until the bit data D is obtained N-1 , where N is the number of bits of the analog-to-digital converter.

[0012] Preferably, when the sampling module is used to perform initial sampling on the input signal, the voltage states of all the capacitor units in the positive phase high capacitor array and the negative phase high capacitor array are adjusted to V ref , the voltage states of all capacitor units in the positive phase low capacitance array and the negative phase low capacitance array are adjusted to gnd.

[0013] Preferably, the method for first adjusting the circuit connection status of all the capacitor units includes: Among the plurality of capacitor units, the state switching module is used to switch the connection states of all capacitor units except the first capacitor unit to disconnected.

[0014] Preferably, the specific method for performing a second adjustment on the circuit connection state of the capacitor unit based on D0 includes: If D0=1, the state switching module is used to switch the connection state of the first capacitor unit in the positive phase low capacitor array and the negative phase high capacitor array to disconnection; if D0=0, the connection state of the first capacitor unit in the positive phase high capacitor array and the negative phase low capacitor array is switched to disconnection; The connection state is maintained as the voltage state of the first capacitor unit connected is adjusted to V cm .

[0015] Preferably, each time a bit of data is generated, the bit of data is sequentially stored in the shift register.

[0016] The present invention adopts the technology of capacitor array partition dormancy, so that the analog-to-digital converter only needs to use half the power supply voltage to process the same input signal swing, thereby greatly reducing the required energy consumption, reducing the number of unit capacitors, optimizing the switch switching scheme of the capacitor array, and reducing the overall power consumption of the analog-to-digital converter; The present invention can freely adjust the required output resolution for an analog-to-digital converter with an N-bit resolution, that is, it can be adjusted within the range of 5-N bits, has higher flexibility and a wider range of applications. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0018] Figure 1 It is a structural schematic diagram of the analog-to-digital converter of the present invention; Figure 2 is a schematic diagram of a voltage state switching method in the first stage of the analog-to-digital conversion method of the present invention when the number of data bits is 6; Figure 3 is a schematic diagram of a voltage state switching method in the second stage of the analog-to-digital conversion method of the present invention when the number of data bits is 6; Figure 4 is a schematic diagram of a voltage state switching method in the third stage of the analog-to-digital conversion method of the present invention when the number of data bits is 6; Figure 5 is a schematic diagram of a voltage state switching method in the fourth stage of the analog-to-digital conversion method of the present invention when the number of data bits is 6; Figure 6 It is a schematic diagram of the first part of the voltage state switching method in the fifth stage of the analog-to-digital conversion method of the present invention when the number of data bits is 6; Figure 7 It is a schematic diagram of the second part of the voltage state switching method in the fifth stage of the analog-to-digital conversion method of the present invention when the number of data bits is 6; Figure 8 It is a schematic diagram of the first part of the voltage state switching method in the sixth stage of the analog-to-digital conversion method of the present invention when the number of data bits is 6; Fig. 9 It is a schematic diagram of the second part of the voltage state switching method in the sixth stage of the analog-to-digital conversion method of the present invention when the number of data bits is 6; Fig.10 It is a schematic diagram of the third part of the voltage state switching method in the sixth stage of the analog-to-digital conversion method of the present invention when the number of data bits is 6; Fig.11 It is a schematic diagram of the fourth part of the voltage state switching method in the sixth stage of the analog-to-digital conversion method of the present invention when the number of data bits is 6. DETAILED DESCRIPTION

[0019] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0020] like Figure 1 As shown, a partitioned dormant capacitor array analog-to-digital converter with adjustable resolution includes a total capacitor array, a sampling module, a comparator, a shift register, a state switching module and two power supply modules, wherein the total capacitor array includes a positive phase conversion capacitor array and a negative phase conversion capacitor array.

[0021] The positive phase conversion capacitor array includes a positive phase high capacitor array and a positive phase low capacitor array, and the negative phase conversion capacitor array includes a negative phase high capacitor array and a negative phase low capacitor array. The positive phase high capacitor array, the positive phase low capacitor array, the negative phase high capacitor array and the negative phase low capacitor array all include a plurality of capacitor units arranged in sequence, and a bridge switch is provided between two adjacent capacitor units. Among the plurality of capacitor units arranged in sequence, the first capacitor unit includes two unit capacitors and an extended capacitor, and the two unit capacitors are connected in parallel and in series with the extended capacitor, and the capacitance of the extended capacitor is twice that of the unit capacitor, the second capacitor unit includes a unit capacitor, and starting from the third capacitor unit, the next capacitor unit includes all of the previous capacitor unit and a high-value capacitor with a capacitance equal to the total capacitance of the previous capacitor unit.

[0022] More specifically, the positive phase high capacitance array, the positive phase low capacitance array, the negative phase high capacitance array and the negative phase low capacitance array all include N-3 capacitance units arranged in sequence, where N is the number of bits of the analog-to-digital converter. The capacitance of the unit capacitance is recorded as C, then the first capacitance unit includes a middle extension capacitance with a capacitance of 2C; the second capacitance unit includes a unit capacitance; the third capacitance unit includes two unit capacitances; the fourth capacitance unit includes two unit capacitances and a high capacitance with a capacitance of 2C; the fifth capacitance unit includes two unit capacitances, a high capacitance with a capacitance of 2C and a high capacitance with a capacitance of 4C, and so on. The capacitance composition of the N-3 capacitance unit can be expressed as C, C, 2C, ... 2 N-6 C. For easy distinction, Figure 1 In the example, the capacitance units are marked as partitions, the high capacitance array is marked as the high array, and the low capacitance array is marked as the low array.

[0023] The sampling module is used to initially sample the input signal from the top plates of all capacitor units.

[0024] The comparator is used to compare the input signal or the state of the positive phase conversion capacitor array and the negative phase conversion capacitor array and output bit data.

[0025] Shift register, used to store bit data.

[0026] Both power modules include a ground terminal gnd, a reference voltage terminal V ref and common mode voltage terminal V cmThe state switching module is used to cooperate with the bridge switch to control the circuit connection state of all capacitor units, and the circuit connection state includes a connection state and a voltage state. The state switching module includes a plurality of state switching units, and the power supply module is connected to the capacitor unit via the state switching unit. The state switching unit includes a plurality of switching switches, and the switching switches are connected to the capacitors in the capacitor unit. By changing the state of the switching switches, the connection state of the capacitor and the power supply module can be changed, that is, by changing the state of the switching switches, the capacitor can be connected to the ground terminal gnd and the reference voltage terminal V ref Or the common mode voltage terminal V cm Connection. The connection status is connected or disconnected, and the voltage status is gnd, V ref or V cm .

[0027] It should be noted that, in the present invention, the specific structures and working principles of the sampling module, the comparator and the shift register belong to conventional technical means in the art and will not be described in detail here.

[0028] The present invention further provides a partitioned dormant capacitor array analog-to-digital conversion method with adjustable resolution. Based on the above-mentioned partitioned dormant capacitor array analog-to-digital converter with adjustable resolution, the method includes six stages, which are specifically as follows.

[0029] In the first stage, the sampling module is used to perform initial sampling of the input signal. When the sampling module is used to perform initial sampling of the input signal, all bridge switches and switching switches are closed, and the sampling module samples the input signal on the top plate of all capacitors. In addition, the voltage state of all capacitor units in the positive phase high capacitance array and the negative phase high capacitance array is adjusted to V ref , the voltage states of all capacitor units in the positive phase low capacitance array and the negative phase low capacitance array are adjusted to gnd.

[0030] After the sampling is completed, the circuit connection state of all capacitor units is adjusted for the first time, so that the first capacitor unit is connected to the comparator, and the comparator performs the first comparison on the input signal and then outputs the bit data D0. The method for adjusting the circuit connection state of all capacitor units for the first time includes: among the multiple capacitor units, using the state switching module to switch the connection state of all capacitor units except the first capacitor unit to disconnection, at which time the disconnected capacitor unit enters the dormant state, and only the first capacitor unit in each capacitor array is kept in the connected state, so that the comparator performs the first comparison without consuming switching energy and outputs the highest bit data D0.

[0031] In the second stage, the circuit connection state of the capacitor unit is adjusted for the second time based on D0, the voltage state of the first capacitor unit is changed, and after the adjustment, the comparator performs a second comparison and outputs the bit data D1. The specific method of adjusting the circuit connection state of the capacitor unit for the second time based on D0 includes: if D0=1, using the state switching module to switch the connection state of the first capacitor unit in the positive phase low capacitance array and the negative phase high capacitance array to disconnected; if D0=0, switching the connection state of the first capacitor unit in the positive phase high capacitance array and the negative phase low capacitance array to disconnected; adjusting the voltage state of the first capacitor unit whose connection state is maintained to V cm After the voltage state adjustment is completed, the voltage of the first capacitor unit in the two high-capacitance arrays drops by V ref / 2, the voltage of the first capacitor unit in the two low capacitance arrays increases by V ref / 2, so the second comparison does not consume switching energy. Then the comparator performs the second comparison and outputs the second most significant bit data D1.

[0032] In the third stage, the voltage states of the capacitors in the positive phase low capacitance array and the negative phase low capacitance array are adjusted for the third time based on D1, and after the adjustment, the comparator performs a third comparison and outputs the bit data D2. More specifically, in the third stage, according to the result of the last comparison, the reference voltages connected to the two low capacitance arrays are increased from V cm To V ref Switching, so that the voltage of the two high capacitance arrays increases V ref / 2, so the third comparison does not consume switching energy. In addition, in the subsequent comparison stage, the capacitor arrays that have been changed this time will remain unchanged, and only the voltage states of the remaining capacitor arrays will be adjusted to achieve the effect of successive approximation. The comparator then performs the third comparison and outputs the valid bit data D2.

[0033] In the fourth stage, the circuit connection state of all capacitor units is adjusted for the fourth time based on D0, D1 and D2, and after the adjustment, the comparator performs the fourth comparison and outputs the bit data D3. More specifically, in the fourth stage, if D0D1=11, the following comparison stage is completed by the positive phase high capacitor array of the positive phase conversion capacitor array switching the voltage state to complete the successive approximation; if D0D1=10, it is completed by the negative phase low capacitor array of the negative phase conversion capacitor array; if D0D1=01, it is completed by the negative phase high capacitor array of the negative phase conversion capacitor array; if D0D1=00, it is completed by the positive phase low capacitor array of the positive phase conversion capacitor array. If D2=1, the voltage state of the capacitor of the first capacitor unit in the positive phase conversion capacitor array is changed by V cm Switching to gnd, or inverting the voltage state of the capacitor of the first capacitor unit in the capacitor array, changes from V cm Switch to V ref; If D2=0, the operation is reversed, that is, the voltage state of the capacitor of the first capacitor unit in the inverse conversion capacitor array is changed from V cm Switch to V ref , or the voltage state of the capacitor of the first capacitor unit in the inverse conversion capacitor array is changed from V cm Switch to gnd. Then perform the fourth comparison and output the valid bit data D3.

[0034] In the fourth stage, the switching energy consumption of the total capacitor array is: .

[0035] In the fifth stage, the circuit connection state of all capacitor units is adjusted for the fifth time based on D2 and D3, and after the adjustment, the comparator performs the fifth comparison and outputs the bit data D4. More specifically, in the fifth stage, when the data D2D3 output by the first two comparisons are the same and 11, if a positive phase conversion capacitor array is used, the voltage unit of the capacitor of the second capacitor unit is switched to gnd, and if a negative phase conversion capacitor array is used, the voltage unit of the capacitor of the second capacitor unit is switched to V ref ; When D2D3=00, if a positive-phase conversion capacitor array is used, the voltage unit of the capacitor of the second capacitor unit is switched to Vref, and if a negative-phase conversion capacitor array is used, the voltage unit of the capacitor of the second capacitor unit is switched to gnd. If D2D3 is different, the voltage state of the capacitor of all second capacitor units is switched to V cm This voltage switching will also affect the switching selection of the reference voltage connected to one of the unit capacitors C of the third capacitor unit. After the voltage state switching is completed, the bridge switch of the second capacitor unit is closed to connect the second capacitor unit back to the circuit, so that the voltage state changes, and then the fifth comparison is performed and the valid bit data D4 is output.

[0036] In the fifth stage, the switching energy consumption of the total capacitor array is: .

[0037] The sixth stage is based on D2 and D n-2 The circuit connection state of all capacitor units is adjusted for the nth time, and after the adjustment, the comparator performs the nth comparison and outputs the bit data D n-1 , until the bit data D is obtained N-1 , where N is the number of bits of the analog-to-digital converter. After the fifth comparison, the subsequent comparison conditions are similar to the fifth comparison. If the comparison output data D2D N-2 When the same and 11, if a positive phase conversion capacitor array is used, the voltage state of the minimum capacitor of the N-3th capacitor unit is switched to gnd, and if a negative phase conversion capacitor array is used, the voltage state is switched to Vref ;D2D N-2 = 00, if a positive-phase switching capacitor array is used, the voltage state switches to V ref If an inverting switching capacitor array is used, the voltage state switches to gnd. N-2 different, the voltage state of the minimum capacitor of the N-3th capacitor unit switches to V cm The remaining capacitors correspond to the results of the previous comparison and switch to the same voltage state. After the voltage state is switched, the bridge switch of the partition is closed to connect the capacitor unit back to the circuit to change the voltage state. Then the Nth comparison is performed and the valid bit data D is output. N-1 .

[0038] Furthermore, in each stage, the switching process of the capacitor voltage state is shown in Table 1.

[0039] Table 1 Summary of voltage state switching methods

[0040] The sixth stage needs to be carried out until the selected resolution (5-N bits) is completed, that is, the 5-Nth comparison is completed. During the whole process, each bit of data is generated and stored in the shift register in sequence. The average switching energy consumption corresponding to each bit of resolution of the total capacitor array is: .

[0041] In a specific implementation of the present invention, the data bit number of the analog-to-digital converter is set to 6. Then, in the sixth comparison, the switching energy consumption of the total capacitor array is: .

[0042] In this embodiment, the average switching energy consumption of the total capacitor array is: 。

[0043] In this embodiment, the switching method of the voltage state in each stage is as follows: Figure 2-11 shown.

[0044] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0045] The above description of the disclosed embodiments enables one skilled in the art to implement or use the present invention. Various modifications to these embodiments will be apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A partitioned dormant capacitor array analog-to-digital converter with adjustable resolution, characterized in that: include: A positive phase conversion capacitor array, including a positive phase high capacitance array and a positive phase low capacitance array; An inverting conversion capacitor array, including an inverting high capacitance array and an inverting low capacitance array; The positive phase high capacitance array, the positive phase low capacitance array, the negative phase high capacitance array and the negative phase low capacitance array all include a plurality of capacitance units arranged in sequence, and a bridge switch is provided between two adjacent capacitance units; Among the plurality of capacitor units arranged in sequence, the first capacitor unit includes two unit capacitors and one extended capacitor, and the two unit capacitors are connected in parallel and in series with the extended capacitor, and the capacitance of the extended capacitor is twice that of the unit capacitor, the second capacitor unit includes one unit capacitor, and starting from the third capacitor unit, the subsequent capacitor unit includes the entirety of the previous capacitor unit and a high-value capacitor whose capacitance is equal to the total capacitance of the previous capacitor unit; A sampling module, used for initially sampling input signals from the top plates of all capacitor units; A comparator, for comparing an input signal or the state of a positive-phase conversion capacitor array and a negative-phase conversion capacitor array and outputting bit data; Shift registers, used to store bit data; The state switching module is used to cooperate with the bridge switch to control the circuit connection state of all capacitor units, and the circuit connection state includes a connection state and a voltage state.

2. The partitioned dormant capacitor array analog-to-digital converter with adjustable resolution as claimed in claim 1, characterized in that: The positive phase high capacitance array, the positive phase low capacitance array, the negative phase high capacitance array and the negative phase low capacitance array each include N-3 capacitance units arranged in sequence, wherein N is the number of bits of the analog-to-digital converter.

3. The partitioned dormant capacitor array analog-to-digital converter with adjustable resolution as claimed in claim 1, characterized in that: The analog-to-digital converter further includes two power supply modules, the state switching module includes a plurality of state switching units, and the power supply modules are correspondingly connected to the capacitor units via the state switching units.

4. The partitioned dormant capacitor array analog-to-digital converter with adjustable resolution as claimed in claim 3, characterized in that: The state switching unit includes a plurality of switching switches, and the switching switches are correspondingly connected to the capacitors in the capacitor unit.

5. The partitioned dormant capacitor array analog-to-digital converter with adjustable resolution as claimed in claim 3, characterized in that: The power supply module includes a ground terminal gnd, a reference voltage terminal V ref and common mode voltage terminal V cm .

6. A partitioned dormant capacitor array analog-to-digital conversion method with adjustable resolution, based on the partitioned dormant capacitor array analog-to-digital converter with adjustable resolution as claimed in any one of claims 1 to 5, characterized in that: The method comprises the following steps: Using the sampling module to perform initial sampling on the input signal; The circuit connection states of all the capacitor units are adjusted for the first time, so that the first capacitor unit is connected to the comparator, and the comparator performs a first comparison on the input signal and outputs the bit data D0; Based on D0, the circuit connection state of the capacitor unit is adjusted for the second time, the voltage state of the first capacitor unit is changed, and after the adjustment, the comparator performs a second comparison and outputs the bit data D1; Based on D1, the voltage states of the capacitor units in the positive phase low capacitance array and the negative phase low capacitance array are adjusted for the third time, and after the adjustment, the comparator performs a third comparison and outputs the bit data D2; The circuit connection states of all the capacitor units are adjusted for the fourth time based on D0, D1 and D2, and after the adjustment, the comparator performs the fourth comparison and outputs the bit data D3; The circuit connection states of all the capacitor units are adjusted for the fifth time based on D2 and D3, and after the adjustment, the comparator performs the fifth comparison and outputs the bit data D4; Based on D2 and D n-2 The circuit connection state of all capacitor units is adjusted for the nth time, and after the adjustment, the comparator performs the nth comparison and outputs the bit data D n-1 , until the bit data D is obtained N-1 , where N is the number of bits of the analog-to-digital converter.

7. The partitioned dormant capacitor array analog-to-digital conversion method with adjustable resolution as claimed in claim 6, characterized in that: When the sampling module is used to perform initial sampling on the input signal, the voltage state of all the capacitor units in the positive phase high capacitor array and the negative phase high capacitor array is adjusted to Vref, and the voltage state of all the capacitor units in the positive phase low capacitor array and the negative phase low capacitor array is adjusted to gnd.

8. The partitioned dormant capacitor array analog-to-digital conversion method with adjustable resolution as claimed in claim 6, characterized in that: The method for first adjusting the circuit connection status of all the capacitor units includes: Among the plurality of capacitor units, the state switching module is used to switch the connection states of all capacitor units except the first capacitor unit to disconnected.

9. The partitioned dormant capacitor array analog-to-digital conversion method with adjustable resolution as claimed in claim 8, characterized in that: The specific method of performing a second adjustment on the circuit connection state of the capacitor unit based on D0 includes: If D0=1, the state switching module is used to switch the connection state of the first capacitor unit in the positive phase low capacitor array and the negative phase high capacitor array to disconnection; if D0=0, the connection state of the first capacitor unit in the positive phase high capacitor array and the negative phase low capacitor array is switched to disconnection; The connection state is maintained as the voltage state of the first capacitor unit connected is adjusted to V cm 9.

10. The partitioned dormant capacitor array analog-to-digital conversion method with adjustable resolution as claimed in claim 6, characterized in that: Each time a bit of data is generated, the bit of data is sequentially stored in the shift register.

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