Semiconductor package

Abstract

A semiconductor package according to an embodiment includes: an insulating layer; a protective layer disposed on the insulating layer; a through electrode passing through the insulating layer; and a bump feature disposed on the through electrode and passing through the protective layer, in which: the bump feature includes a first portion connected to the through electrode and a second portion disposed on the first portion and protruding over the protective layer; and a width of the first portion in the horizontal direction is the same as a width of the second portion in the horizontal direction.

Description

Technical Field

[0001] Embodiments relate to a circuit board and a semiconductor package including the circuit board. Background Art

[0002] A semiconductor package has a structure in which a semiconductor chip is attached to a circuit board. A semiconductor package can be provided by integrating a plurality of packages having different devices attached into one. Since a plurality of components are implemented in one package, such a semiconductor package has the advantage of being able to transmit high-speed signals through a short path. Therefore, semiconductor packages are widely used in mobile devices and the like.

[0003] Meanwhile, when an electronic device such as a semiconductor chip is attached to a circuit board, semiconductor packaging is performed by applying a wire. A semiconductor package having a wire structure has a problem of increasing volume. Therefore, semiconductor packaging is recently performed by flip chip packaging. Flip chip packaging is a method of bonding and packaging a semiconductor chip and a circuit board by fusing solder bumps to a connection pattern of a semiconductor chip or a circuit board without using an additional connection material such as a wire when an electronic component such as a semiconductor chip is attached to a circuit board.

[0004] Recently, due to the demand for high-speed, large-capacity data processing and the miniaturization of electronic products, the bump pitch of electronic devices has become smaller and smaller. In line with this trend, the reliability of the bump connection between the circuit board and the semiconductor chip in the flip chip package is decreasing. In order to prevent the reliability from being reduced, Korean Patent Publication No. 10-2013-0027870 proposes a structure including a bump component with improved reliability. Summary of the invention

[0005] Technical issues

[0006] The embodiment provides a circuit board having a novel structure and a semiconductor package including the same.

[0007] In addition, the embodiment provides a circuit board capable of reducing a pitch between a plurality of bump parts and a semiconductor package including the same.

[0008] In addition, the embodiment provides a circuit board capable of improving circuit integration and a semiconductor package including the same.

[0009] In addition, the embodiment provides a circuit board having improved connection reliability between a bump portion and a pad portion of a bump part and a semiconductor package including the same.

[0010] In addition, the embodiment provides a circuit board capable of minimizing the extent of a recessed portion formed at a side surface of a lower region of a bump part and a semiconductor package including the same.

[0011] In addition, the embodiment provides a circuit board capable of minimizing thickness deviations of a plurality of bump parts and a semiconductor package including the same.

[0012] The technical problems to be solved by the proposed embodiments are not limited to the technical problems mentioned above, and other technical problems not mentioned can be clearly understood by those skilled in the art to which the proposed embodiments belong from the following description.

[0013] Technical Solution

[0014] According to an embodiment, a semiconductor package includes an insulating layer; a protective layer disposed on the insulating layer; a through-electrode passing through the insulating layer; and a bump component disposed on the through-electrode and passing through the protective layer, wherein the bump component includes a first portion connected to the through-electrode; and a second portion disposed on the first portion and protruding onto the protective layer, wherein a width of the first portion in a horizontal direction is the same as a width of the second portion in the horizontal direction.

[0015] In addition, the width of the first portion in the horizontal direction is greater than the width of the upper surface of the through electrode.

[0016] In addition, the first portion and the second portion of the projection member are integrally formed.

[0017] In addition, the first portion and the second portion of the bump member are formed integrally with the through electrode.

[0018] In addition, the bump part includes a plurality of metal layers, and a width of at least one of the plurality of metal layers is different from a width of at least one of the plurality of metal layers.

[0019] In addition, the plurality of metal layers include: a first metal layer disposed on the insulating layer; a second metal layer disposed on the first metal layer; and a third metal layer disposed on the second metal layer, wherein a width of the first metal layer is smaller than a width of the third metal layer.

[0020] In addition, the width of the second metal layer is greater than the width of the first metal layer.

[0021] In addition, the width of the third metal layer is greater than the width of the second metal layer.

[0022] In addition, the first metal layer is a chemical copper plating layer, the second metal layer is a first electrolytic plating layer, and the third metal layer is a second electrolytic plating layer.

[0023] In addition, the bump part further includes a fourth metal layer provided between the insulating layer and the first metal layer, and a width of the third metal layer is greater than a width of the fourth metal layer.

[0024] In addition, the fourth metal layer is a copper layer.

[0025] In addition, the first metal layer has a first thickness in the range of 0.5μm to 1.5μm, the second metal layer has a second thickness in the range of 3μm to 5μm, the third metal layer has a third thickness in the range of 100μm to 220μm, and the fourth metal layer has a fourth thickness in the range of 0.8μm to 2μm.

[0026] In addition, the semiconductor package further includes a pad part which is positioned on the insulating layer and is spaced apart from the bump part in the horizontal direction, and the pad part overlaps the first portion of the bump part in the horizontal direction.

[0027] In addition, the pad part includes first to third metal layers corresponding to the first to third metal layers of the bump part.

[0028] In addition, the thickness of the third metal layer of the pad part is smaller than the thickness of the third metal layer of the bump part.

[0029] In addition, the semiconductor package further includes a trace disposed on the insulating layer and spaced apart from the bump part in a horizontal direction, and the trace overlaps the first portion of the bump part in the horizontal direction.

[0030] In addition, the trace includes first to third metal layers corresponding to the first to third metal layers of the bump feature.

[0031] Additionally, a thickness of the third metal layer of the trace is less than a thickness of the third metal layer of the bump feature.

[0032] Beneficial Effects

[0033] The circuit board of the embodiment includes an insulating layer, a through electrode passing through the insulating layer, and a first circuit layer disposed on the insulating layer. In this case, the first circuit layer includes a bump component. The bump component is provided to pass through a protective layer disposed on the insulating layer and protrude on the protective layer.

[0034] The bump component includes a first portion disposed on the insulating layer and the through electrode, and a second portion on the first portion. There is no interface between the first portion and the second portion of the bump component. In other words, the first portion and the second portion are formed integrally with each other. In addition, the through electrode is formed integrally with the first portion and the second portion of the bump component. In other words, there is no interface between the through electrode and the bump component.

[0035] Therefore, the bump component of the embodiment does not have an additional layer disposed between the first portion and the second portion. Specifically, the bump component does not have a seed layer between the first portion and the second portion. Thus, the embodiment can improve the physical connectivity and electrical connectivity between the first portion and the second portion of the bump component. In addition, the bump component of the embodiment is formed integrally with the through electrode, and thus the electrical and physical reliability can be further improved.

[0036] At this time, in the comparative example, the pad part and the bump part are formed by separate plating processes separated from each other. Therefore, the comparative example has the problem that the electrical and physical connectivity between them is reduced and the signal transmission loss is increased. In addition, the comparative example has a structure in which a seed layer is additionally provided between the pad part and the bump part, and therefore the overall reliability of the bump part is reduced due to the physical reliability problem of the seed layer.

[0037] In contrast, the embodiment has a structure in which the through electrode, the first portion of the bump component and the second portion of the bump component are formed integrally with each other. Therefore, the embodiment can improve the electrical and physical connectivity between the through electrode and the bump component. Therefore, the embodiment can improve the physical reliability and electrical reliability of the circuit board.

[0038] In addition, the bump component of the embodiment includes a first metal layer, a second metal layer and a third metal layer. In addition, the second metal layer is a first electroplated layer in which the first metal layer is electroplated as a seed layer, and the third metal layer is a second electroplated layer in which the first metal layer and the second metal layer are electroplated as a seed layer.

[0039] Therefore, the embodiment can minimize the depth of the recessed portion generated in the etching process of the seed layer performed after the circuit layer is formed. That is, the second metal layer can have a higher strength than the first metal layer as an electroplating layer. Therefore, the second metal layer can be used as a barrier layer, which minimizes the depth of the recessed portion generated at the side surface of the first metal layer in the etching process. In addition, the second metal layer can play a role in preventing the third metal layer from deforming in the etching process. Therefore, by further including the second metal layer in the bump component, the embodiment can minimize the depth of the recessed portion formed at the lower side surface of the bump component. Therefore, the embodiment can improve the physical reliability and electrical reliability of the bump component.

[0040] In addition, the third metal layer of the bump part is plated not only on the first metal layer but also on the second metal layer as a seed layer. Therefore, the embodiment can minimize the thickness deviation between the plurality of bump parts included in the circuit board.

[0041] Specifically, in the circuit board of the comparative example, only the chemical copper plating layer is used as the seed layer to perform the plating of the bump component. At this time, the bump component has a thickness of 100 μm or more. Therefore, when the plating has a metal layer with a thickness of 100 μm or more, it is difficult to perform a plating process with uniform thickness over the entire area using only the chemical copper plating layer. Therefore, in the circuit board of the comparative example, the thickness deviation of each bump component exceeds 30% compared with the average value of the thickness of the plurality of bump components. For example, when the average value is 100 μm, the thickness of at least one bump component among the plurality of bump components is less than 70 μm or exceeds 130 μm. Therefore, in the circuit board of the comparative example, the plating process is performed so that the thickness of each bump component is greater than the target thickness, so as to match the thickness of each bump component. Therefore, the comparative example has the following problem: while the thickness of the bump component is finally adjusted to the target thickness, a polishing process must be included to make the thickness uniform, and the polishing process time increases.

[0042] In contrast, the embodiment not only uses the first metal layer of the bump component, but also uses the second metal layer as a seed layer to perform electrolytic plating on the third metal layer of the bump component. Therefore, the embodiment can minimize the thickness deviation between the plurality of bump components. Therefore, the embodiment can perform the plating process under the condition that the bump component has a thickness corresponding to the target thickness. Therefore, the embodiment can omit the polishing process or greatly shorten the polishing process time. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1 is a cross-sectional view showing a circuit board according to a comparative example.

[0044] Figure 2 is a cross-sectional view showing a circuit board according to an embodiment.

[0045] Figure 3 is a cross-sectional view showing the layer structure of the bump member of the first circuit layer of the first embodiment.

[0046] Figure 4 is a cross-sectional view showing the layer structure of the pad of the first circuit layer of the first embodiment.

[0047] Figure 5 is a cross-sectional view showing the layer structure of traces of the first circuit layer of the first embodiment.

[0048] Figure 6 is a cross-sectional view showing the layer structure of the second circuit layer of the embodiment.

[0049] Figure 7 is a cross-sectional view showing the layer structure of the bump component of the first circuit layer of the second embodiment.

[0050] Figure 8is a diagram showing the first embodiment of the present invention. Figure 7 An enlarged view of an enlarged view of area A.

[0051] Fig. 9 is a diagram showing a method according to the second embodiment Figure 7 An enlarged view of an enlarged view of area A.

[0052] Fig.10 is a diagram showing a semiconductor package according to an embodiment.

[0053] Figures 11 to 22 It is shown in the order of process Figure 2 A cross-sectional view of a method for manufacturing a circuit board is shown in FIG. DETAILED DESCRIPTION

[0054] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the spirit and scope of the present invention are not limited to the described partial embodiments and can be implemented in various other forms, and one or more elements in the embodiments can be selectively combined and rearranged within the spirit and scope of the present invention.

[0055] In addition, unless otherwise explicitly defined and described, the terms (including technical and scientific terms) used in the embodiments of the present invention may be understood to have the same meaning as commonly understood by ordinary technicians in the field to which the present invention belongs, and terms such as those defined in commonly used dictionaries may be interpreted as having a meaning consistent with the meaning in the context of the relevant field.

[0056] In addition, the terms used in the embodiments of the present invention are used to describe the embodiments and are not intended to limit the present invention. In this specification, unless explicitly stated in a phrase, a singular form may also include a plural form, and may include at least one of all possible combinations of A, B, and C when described in "at least one (or more) of A (and), B, and C".

[0057] In addition, when describing the elements of the embodiments of the present invention, terms such as first, second, A, B, (a), and (b) may be used. These terms are only used to distinguish elements from other elements and are not limited to the nature, order, or sequence of the elements.

[0058] In addition, when an element is described as being “connected,” “coupled” or “in contact with” another element, it may include not only when the element is directly “connected,” “coupled” or “in contact with” the other element, but also when the element is “connected,” “coupled” or “in contact with” through another element between the element and the other element.

[0059] In addition, when described as being formed or disposed “on (above)” or “under (below)” each element, the “on (above)” or “under (below)” may include not only when the two elements are directly connected but also when one or more other elements are formed or disposed between the two elements.

[0060] In addition, when expressed as “upper” or “lower”, it can include not only an upper direction but also a lower direction based on one element.

[0061] (Comparison example)

[0062] Figure 1 is a cross-sectional view showing a circuit board according to a comparative example.

[0063] refer to Figure 1 , the circuit board includes an insulating layer 10.

[0064] In addition, the first circuit pattern 20 is disposed on the upper surface of the insulating layer 10, and the second circuit pattern 30 is disposed on the lower surface of the insulating layer 10. The first circuit pattern 20 includes a pad.

[0065] In addition, the circuit board of the comparative example includes a through electrode penetrating the insulating layer 10 .

[0066] The protection layer 50 is disposed on the upper surface of the insulating layer 10 , and has an opening vertically overlapping the upper surface of the pad of the first circuit pattern 20 .

[0067] In addition, the bumps 70 are provided on the pads of the first circuit pattern 20 .

[0068] The bump 70 has a certain height or thickness, and protrudes on the pad of the first circuit pattern 20. Therefore, it is difficult to form the bump 70 by electroless plating.

[0069] Therefore, the seed layer 60 is disposed between the bump 70 and the pad of the first circuit pattern 20. The seed layer 60 is a chemical copper plating layer.

[0070] The seed layer 60 is disposed on the upper surface of the pad of the first circuit pattern 20 and the inner wall of the protection layer 50 , respectively.

[0071] That is, the comparative example has a structure in which the seed layer 60 is disposed between the bump 70 and the pad of the first circuit pattern 20. Therefore, the comparative example has a problem that a process of forming the seed layer 60 must be additionally performed, and the manufacturing process becomes complicated or the manufacturing time increases accordingly.

[0072] In addition, the circuit board of the comparative example undergoes a whitening phenomenon of the protective layer 50 due to the solution used in the decontamination process of the seed layer 60 formed by chemical plating. In addition, the circuit board of the comparative example has a structure in which the seed layer 60 is disposed between the pad and the bump 70, and thus the bump layer has a porous microstructure. At this time, the porous structure has a low metal density, and therefore, there is a problem of cracks being generated in the porous seed layer 60 due to external impact or other physical forces. In addition, there is a problem that the bump 70 is damaged due to the generation of cracks, and thus the reliability or durability of the product is greatly reduced.

[0073] In addition, the comparative example has a problem that the connection reliability between the pad and the bump 70 is reduced due to the structure in which the seed layer 60 is provided.

[0074] In addition, the comparative example has a problem that the seed layer 60 is etched in a pre-treatment process for the surface treatment of the bump 70 and thus the bump 70 cannot perform its normal function.

[0075] In addition, the bump 70 of the comparative example is arranged on the pad with a width smaller than the width of the pad. Therefore, the pitch between the plurality of bumps corresponds to the pitch between the plurality of pads connected to the plurality of bumps. In addition, the pitch between the plurality of pads corresponds to the pitch between the plurality of through electrodes connected thereto.

[0076] At this time, the comparative example determines the pitch between the through electrodes, the pitch between the pads, and the pitch between the bumps by considering all of the tolerance in the process of forming the bumps 70, the tolerance in the process of forming the pads of the first circuit pattern 20, and the tolerance in the process of forming the through holes of the through electrodes 40. Therefore, the comparative example has a limitation in reducing the pitch between the plurality of bumps.

[0077] In addition, the comparative example performs plating on the bump 70 through the seed layer 60 separately provided on the pad of the first circuit pattern 20. Therefore, the comparative example has a problem of large thickness deviation among the plurality of bumps 70. Therefore, the comparative example has a problem that a polishing process must be performed to match the thickness of the plurality of bumps.

[0078] The embodiments provide a circuit board and a semiconductor package including the same, which can improve circuit integration by reducing a pitch between a plurality of bump components (pillars), improve connection reliability between a bump portion and a pad portion of a bump component, minimize a recessed degree of a recessed portion formed at a side surface of a lower region, and minimize thickness deviation of a plurality of bump components.

[0079] -Electronic Devices-

[0080] Before describing the embodiment, an electronic device including a semiconductor package of the embodiment will be briefly described. The electronic device includes a mainboard (not shown). The mainboard can be physically and / or electrically connected to various components. For example, the mainboard can be electrically connected to the semiconductor package of the embodiment. Various devices can be mounted on the semiconductor package. The semiconductor package can include various devices or chips. The device or chip can include memory chips such as volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), and flash memory, application processor chips such as central processing units (e.g., CPUs), graphics processors (e.g., GPUs), antenna chips, digital signal processors, cryptographic processors, microprocessors, and microcontrollers, and logic chips such as analog-to-digital converters and ASICs (application specific ICs).

[0081] Additionally, a device or chip may include passive devices and active devices.

[0082] An active device refers to a component that actively utilizes the nonlinear part of the signal characteristics. In addition, a passive device refers to a component that does not utilize the nonlinear signal characteristics even if both linear and nonlinear signal characteristics exist. For example, active devices may include transistors, IC semiconductor devices, and passive devices may include capacitors, resistors, inductors, etc. Passive devices may increase the signal processing speed of a semiconductor chip as an active device, or perform a filtering function. In addition, the chip may be a wireless communication chip that can be used for Wi-Fi or 5G communications.

[0083] Meanwhile, the product group of the semiconductor package to which the embodiment is applied may be any one of CSP (chip scale package), FC-CSP (flip chip - chip scale package), FC-BGA (flip chip ball grid array), POP (package stack-up) and SIP (system in package), but is not limited thereto.

[0084] In this case, the electronic device may be a smartphone, a personal digital assistant, a digital video camera, a digital still camera, a vehicle, a high-performance server, a network system, a computer, a display, a tablet computer, a laptop computer, a netbook, a television, a video game console, a smart watch, an automobile, etc. However, the embodiment is not limited thereto, and may be any other electronic device that processes data in addition to these.

[0085] Figure 2 is a cross-sectional view showing a circuit board according to an embodiment.

[0086] In the following, reference will be made to Figure 2 The overall structure of a circuit board according to an embodiment is described.

[0087] refer to Figure 2, the circuit board 100 enables at least one chip to be attached. In addition, the circuit board 100 of the embodiment enables attachment to a main board of an electronic device. The main board may mean a main board of an electronic device.

[0088] In addition, the number of chips mounted on the circuit board 100 may be one, or alternatively, two or more. For example, one processor chip may be mounted on the circuit board 100. For example, at least two processor chips with different functions may be mounted on the circuit board 100, for example, one memory chip and one processor chip may be mounted on the circuit board 100, for example, at least two processor chips with different functions and at least one memory chip may be mounted on the circuit board 100.

[0089] The circuit board 100 includes an insulating layer 110 .

[0090] At this time, the circuit board 100 of the embodiment may be a core board. For example, the circuit board 100 may include a second insulating layer 112 of a core layer.

[0091] For example, the circuit board 100 may have a structure in which a plurality of insulating layers having mutually symmetrical structures are laminated on the upper and lower parts thereof with the second insulating layer 112 as the center. However, the embodiment is not limited thereto. For example, a plurality of insulating layers having mutually asymmetrical structures may be arranged on the upper and lower parts thereof with the second insulating layer 112 as the center.

[0092] Hereinafter, the circuit board 100 of the embodiment is described as a core board, and therefore, the second insulating layer 112 is a core layer. However, the embodiment is not limited thereto. For example, the circuit board 100 of the embodiment may be a coreless board that does not include a core layer. The structural feature of the circuit board 100 of the embodiment is the outermost circuit layer of the circuit board 100. Hereinafter, the structure of the outermost circuit layer of the circuit board 100 of the embodiment will be described.

[0093] Therefore, the structure of the outermost circuit layer 120 of the circuit board 100 described below can be applied to a core board, and differently, can be applied to a coreless board. In addition, the structure of the outermost circuit layer 120 can be applied not only to the laminated structure of a general circuit board, but also to a circuit board of an ETS (embedded trace substrate) structure.

[0094] The circuit board 100 of the embodiment includes an insulating layer 110 .

[0095] The insulating layer 110 may include a first insulating layer 111 , a second insulating layer 112 , and a third insulating layer 113 from an upper side.

[0096] The second insulating layer 112 may refer to an inner insulating layer disposed on an inner layer among a plurality of insulating layers of the circuit board 100. The second insulating layer 112 may include prepreg.

[0097] At this time, although the first insulating layer 111 is illustrated in the figure as having a single-layer structure, the embodiment is not limited thereto. For example, the first insulating layer 111 may have a multi-layer structure. For example, the circuit board 100 may have a layer structure of four or more layers. In addition, the first insulating layer 111 corresponding to the inner insulating layer of the circuit board 100 may have a multi-layer structure based on the total number of layers of the circuit board 100.

[0098] The first insulating layer 111 may be disposed on the second insulating layer 112. For example, the first insulating layer 111 may be disposed on an upper surface of the second insulating layer 112.

[0099] The first insulating layer 111 may refer to a first outermost insulating layer among the insulating layers 110 of the circuit board 100. For example, the first insulating layer 111 may refer to an insulating layer disposed at the uppermost side among the insulating layers 110 of the circuit board 100. The first insulating layer 111 may provide a mounting area where a chip is mounted, or a bonding area where an external substrate such as a main board of an electronic device is bonded.

[0100] The third insulating layer 113 may be disposed on a lower surface of the second insulating layer 112. The third insulating layer 113 may refer to a second outermost insulating layer among the insulating layers 110 of the circuit board 100. For example, the third insulating layer 113 may refer to an insulating layer disposed at a lowermost side among the insulating layers 110 of the circuit board 100.

[0101] The first insulating layer 111 and the third insulating layer 113 may be rigid or flexible. For example, the first insulating layer 111 and the third insulating layer 113 may include glass or plastic. In detail, the first insulating layer 111 and the third insulating layer 113 may include chemically strengthened / semi-strengthened glass, such as soda-lime glass or aluminosilicate glass. Alternatively, the first insulating layer 111 and the third insulating layer 113 may include strengthened or flexible plastic, such as polyimide (PI), polyethylene terephthalate (PET), propylene glycol (PPG), or polycarbonate (PC). Alternatively, the first insulating layer 111 and the third insulating layer 113 may include sapphire.

[0102] In addition, the first insulating layer 111 and the third insulating layer 113 may include an optically isotropic film. For example, the first insulating layer 111 and the third insulating layer 113 may include COC (cyclic olefin copolymer), COP (cyclic olefin polymer), optically isotropic polycarbonate (PC), or optically isotropic polymethyl methacrylate (PMMA).

[0103] In addition, the first insulating layer 111 and the third insulating layer 113 may be formed of a material including an inorganic filler and an insulating resin. For example, the first insulating layer 111 and the third insulating layer 113 may include a structure in which an inorganic filler such as silicon dioxide or aluminum oxide is dispersed in a thermosetting resin such as epoxy resin or a thermoplastic resin such as polyimide. For example, the first insulating layer 111 and the third insulating layer 113 may include ABF (Ajinomoto deposited film), FR-4, BT (bismaleimide triazine), PID (photoimageable dielectric resin), BT, etc.

[0104] In addition, the first insulating layer 111 and the third insulating layer 113 can be bent while having a partially curved surface. That is, the first insulating layer 111 and the third insulating layer 113 can be bent while having a partially flat surface and a partially curved surface. In detail, the first insulating layer 111 and the third insulating layer 113 can be bent while having a curved surface at the end, or can be bent or bent while having a surface including an arbitrary curvature.

[0105] In addition, the first insulating layer 111 and the third insulating layer 113 may be flexible substrates having flexible characteristics. In addition, the first insulating layer 111 and the third insulating layer 113 may be substrates that are bent or folded.

[0106] Each of the first insulating layer 111 and the third insulating layer 113 may have a thickness in the range of 10 μm to 60 μm. Preferably, each of the first insulating layer 111 and the third insulating layer 113 may have a thickness in the range of 12 μm to 50 μm. More preferably, each of the first insulating layer 111 and the third insulating layer 113 may have a thickness in the range of 15 μm to 40 μm.

[0107] If the thickness of the first insulating layer 111 or the third insulating layer 113 is less than 10 μm, the circuit layer included in the circuit board 100 may not be stably protected.

[0108] In addition, if the thickness of the first insulating layer 111 or the third insulating layer 113 exceeds 60 μm, the thickness of the circuit board 100 may increase, thereby increasing the thickness of the semiconductor package. In addition, if the thickness of the first insulating layer 111 or the third insulating layer 113 exceeds 60 μm, the thickness of the circuit layer and the thickness of the through electrode will also increase accordingly. In addition, if the thickness of the circuit layer and the thickness of the through electrode increase, it is difficult to achieve miniaturization, so the circuit integration may decrease, and the signal transmission distance may increase, so that the signal transmission loss may increase.

[0109] The circuit board 100 of the embodiment includes a circuit layer disposed on an insulating layer 110 .

[0110] For example, the circuit board 100 may include a first circuit layer 120 disposed on an upper surface of the first insulating layer 111 .

[0111] For example, the circuit board 100 may include a second circuit layer 130 disposed between a lower surface of the first insulating layer 111 and an upper surface of the second insulating layer 112 .

[0112] For example, the circuit board 100 may include a third circuit layer 140 disposed between a lower surface of the second insulating layer 112 and an upper surface of the third insulating layer 113 .

[0113] For example, the circuit board 100 may include a fourth circuit layer 150 disposed on a lower surface of the third insulating layer 113 .

[0114] The first circuit layer 120 , the second circuit layer 130 , the third circuit layer 140 , and the fourth circuit layer 150 may be manufactured using conventional printed circuit board manufacturing processes such as an additive process, a subtractive process, a modified semi-additive process (MSAP), and a semi-additive process (SAP), and a detailed description thereof is omitted herein.

[0115] The first circuit layer 120 may refer to a circuit layer disposed on a first outermost layer of the circuit board 100. In addition, the fourth circuit layer 140 may refer to a circuit layer disposed on a second outermost layer of the circuit board 100.

[0116] The first circuit layer 120 may have a structure protruding above the upper surface of the first insulating layer 111. In addition, the fourth circuit layer 140 may have a structure protruding below the lower surface of the third insulating layer 113, but the embodiment is not limited thereto. For example, if the circuit board 100 of the embodiment has an ETS structure, one of the first circuit layer 120 and the fourth circuit layer 140 (preferably, the fourth circuit layer) may have a structure embedded in the surface of the insulating layer.

[0117] The first circuit layer 120 may be divided into a plurality of circuit patterns according to functions.

[0118] For example, the first circuit layer 120 may include a first circuit pattern 121 , a second circuit pattern 122 , and a third circuit pattern 123 .

[0119] The first circuit pattern 121 is used as a metal bump component for bonding an external substrate (e.g., a main board of an electronic device) to the circuit board 100. Therefore, the first circuit pattern 121 may also be referred to as a "bump component." Hereinafter, the first circuit pattern 121 is described as a "bump component."

[0120] The second circuit pattern 122 is used as a mounting pad for mounting a chip on the circuit board 100. Therefore, the second circuit pattern 122 may also be referred to as a “pad.” Hereinafter, the second circuit pattern 122 is described as a “pad.”

[0121] The third circuit pattern 123 serves as a trace connected to at least one of the first circuit pattern 121 and the second circuit pattern 122 and performs a wiring function. Therefore, the third circuit pattern 123 may also be referred to as a "trace." Hereinafter, the third circuit pattern 123 is described as a "trace."

[0122] Bump component 121 may have a different thickness from pad 122 and trace 123. Preferably, the thickness of bump component 121 may be greater than the thickness of pad 122 and trace 123. In addition, pad 122 and trace 123 may have the same thickness. Here, the same thickness may mean that the difference in thickness between pad 122 and trace 123 is 5 μm or less, 4 μm or less, 3 μm or less, 2 μm or less, or 1 μm or less.

[0123] The thickness of the bump component 121 may be 3 times or more than the thickness of the pad 122 or the trace 123. For example, the thickness of the bump component 121 may be 5 times or more than the thickness of the pad 122 or the trace 123. For example, the thickness of the bump component 121 may be 7 times or more than the thickness of the pad 122 or the trace 123. For example, the thickness of the bump component 121 may be 10 times or more than the thickness of the pad 122 or the trace 123.

[0124] At this time, the fact that the thickness of the bump component 121 is greater than the thickness of the pad 122 or the thickness of the trace 123 does not mean that the number of layers of the metal layer constituting the bump component 121 is greater than the number of layers of the metal layer constituting the pad 122 or the trace 123. In other words, the number of layers of the metal layer constituting the bump component 121 is the same as the number of layers of the metal layer constituting the pad 122 or the trace 123. In other words, the layer structure of the bump component 121 is the same as the layer structure of the pad 122 or the trace 123. However, the thickness of any one of the metal layers constituting the bump component 121 is greater than the thickness of the corresponding metal layer of the pad 122 or the trace 123.

[0125] Therefore, the thickness 121 of the bump feature 121 is greater than the thickness of the pad 122 or the trace 123 .

[0126] The bump component 121 can be divided into a plurality of parts. The bump component 121 can be divided into a first part 121P and a second part 121B based on the thickness direction. At this time, the division of the first part 121P and the second part 121B does not mean layer division. Specifically, the first part 121P and the second part 121B are a single configuration formed integrally with each other, and can be divided only based on the pad 122 or the trace 123.

[0127] The first portion 121P of the bump component 121 may mean a pad portion of the bump component 121. The first portion 121P of the bump component 121 may have a thickness corresponding to a thickness of the pad 122 or the trace 123.

[0128] The second portion 121B of the bump member 121 is disposed on the first portion 121P of the bump member 121. The second portion 121B of the bump member 121 may be referred to as a bump portion of the bump member 121.

[0129] Therefore, the bump part 121 may be larger than the thickness of the pad 122 or the trace 123 by the thickness of the second portion 121B.

[0130] To this end, the bump component 121 may be formed by a plating process separate from the pad 122 or the trace 123. However, the embodiment is not limited thereto. The first portion 121P of the bump component 121 may be formed in a plating process of the pad 122 or the trace 123, and the second portion 121B of the bump component 121 may be formed as one body with the first portion 121P by performing an additional plating process.

[0131] By this, the bump component 121 of the embodiment does not have an additional layer disposed between the first portion 121P and the second portion 121B. Specifically, the bump component 121 does not have a seed layer between the first portion 121P and the second portion 121B. By doing so, the embodiment can improve the physical connectivity and electrical connectivity between the first portion 121P and the second portion 121B of the bump component 121. In addition, the widths of the first portion 121P and the second portion 121B of the bump component 121 can correspond to each other. Here, the width of the first portion 121P may refer to the concave portion ( Fig. 22 Therefore, the embodiment can determine the pitch between the plurality of bump parts 121 a and 121 b based on the pitch of the second portion 121B of the bump part 121 .

[0132] The detailed structures of the bump parts 121 , the pads 122 , and the traces 123 of the first circuit layer 120 will be described in more detail below.

[0133] The second circuit layer 130, the third circuit layer 140, and the fourth circuit layer 150 may have a layer structure different from that of the first circuit layer 120. For example, the number of metal layers of the second circuit layer 130, the third circuit layer 140, and the fourth circuit layer 150 may be different from that of the first circuit layer 120. For example, the number of metal layers of the second circuit layer 130, the third circuit layer 140, and the fourth circuit layer 150 may be less than that of the first circuit layer 120.

[0134] Specifically, the first circuit layer 120, the second circuit layer 130, the third circuit layer 140, and the fourth circuit layer 150 each include a metal layer corresponding to the seed layer. In addition, the number of seed layers of the second circuit layer 130, the third circuit layer 140, and the fourth circuit layer 150 may be less than the number of seed layers of the first circuit layer 120.

[0135] However, the fourth circuit layer 150 is the second outermost circuit layer of the circuit board and may be formed together with the first circuit layer 120. Therefore, the embodiment may allow the fourth circuit layer 150 to have a layer structure corresponding to the first circuit layer 120 in order to improve processability.

[0136] The first circuit layer 120, the second circuit layer 130, the third circuit layer 140 and the fourth circuit layer 150 may be formed of at least one metal material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu) and zinc (Zn). In addition, the first circuit layer 120, the second circuit layer 130, the third circuit layer 140 and the fourth circuit layer 150 may be formed of a paste or solder paste including at least one metal material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu) and zinc (Zn) having excellent bonding strength. Preferably, the first circuit layer 120, the second circuit layer 130, the third circuit layer 140 and the fourth circuit layer 150 may be formed of relatively inexpensive copper (Cu).

[0137] The second circuit layer 130, the third circuit layer 140 and the fourth circuit layer 150 may have a thickness in the range of 5 μm to 20 μm. For example, the second circuit layer 130, the third circuit layer 140 and the fourth circuit layer 150 may have a thickness in the range of 6 μm to 17 μm. The second circuit layer 130, the third circuit layer 140 and the fourth circuit layer 150 may have a thickness in the range of 7 μm to 13 μm. When the thickness of the second circuit layer 130, the third circuit layer 140 and the fourth circuit layer 150 is less than 5 μm, the resistance may increase. When the thickness of the second circuit layer 130, the third circuit layer 140 and the fourth circuit layer 150 exceeds 20 μm, circuit miniaturization may be difficult, and thus the circuit integration may be reduced.

[0138] Meanwhile, the pad 122 and the trace 123 of the first circuit layer 120 may have a thickness corresponding to the thickness of the second circuit layer 130 , the third circuit layer 140 , and the fourth circuit layer 150 .

[0139] In addition, the thickness of the bump part 121 of the first circuit layer 120 may be greater than the thickness of the pad 122 , the trace 123 , the second circuit layer 130 , the third circuit layer 140 , and the fourth circuit layer 150 .

[0140] The thickness of the bump part 121 of the first circuit layer 120 may exceed 100 μm. The thickness of the bump part 121 of the first circuit layer 120 may exceed 120 μm. The thickness of the bump part 121 of the first circuit layer 120 may exceed 140 μm. The thickness of the bump part 121 of the first circuit layer 120 may exceed 160 μm. The thickness of the bump part 121 of the first circuit layer 120 may exceed 200 μm.

[0141] The thickness of the bump part 121 of the first circuit layer 120 may satisfy the range of 100 μm to 220 μm. Preferably, the thickness of the bump part 121 of the first circuit layer 120 may satisfy the range of 110 μm to 215 μm. More preferably, the thickness of the bump part 121 of the first circuit layer 120 may satisfy the range of 115 μm to 210 μm.

[0142] If the thickness of the bump component 121 of the first circuit layer 120 is less than 100 μm, the external substrate (e.g., the main board of the electronic device) may not be stably bonded to the first bump component 121. For example, if the thickness of the bump component 121 of the first circuit layer 120 exceeds 220 μm, the rigidity of the bump component 121 may be reduced, and therefore, reliability problems such as collapse may occur when bonding the external substrate. In addition, if the thickness of the bump component 121 of the first circuit layer 120 exceeds 220 μm, the thickness deviation between the plurality of bump components may increase, and therefore, the time of the polishing process may increase. In addition, if the thickness of the bump component 121 of the first circuit layer 120 exceeds 220 μm, the thickness of the circuit board 100 and the thickness of the semiconductor package may increase.

[0143] The circuit board of the embodiment may include through electrodes.

[0144] Specifically, the through electrode may pass through the insulating layer 110. Preferably, the through electrode includes a first through electrode 160 passing through the first insulating layer 111. In addition, the through electrode includes a second through electrode 170 passing through the second insulating layer 112. Furthermore, the through electrode includes a third through electrode 180 passing through the third insulating layer 113.

[0145] The first through electrode 160 , the second through electrode 170 , and the third through electrode 180 may be disposed in a through hole passing through each insulating layer. For example, the first through electrode 160 , the second through electrode 170 , and the third through electrode 180 may be formed by filling the through hole with a conductive material.

[0146] The through hole can be formed by any one of mechanical, laser, and chemical processing methods. The through hole can be formed by mechanical processing methods such as milling, drilling, and routing. In addition, the through hole can use UV or CO2 laser methods. In addition, the first through hole can use a chemical processing method using a chemical agent including silane, ketone, etc.

[0147] When forming the through hole, any one metal material selected from copper (Cu), silver (Ag), tin (Sn), gold (Au), nickel (Ni), and palladium (Pd) may be used to fill the through hole to form the first through electrode 160, the second through electrode 170, and the third through electrode 180. At this time, the filling of the conductive material can be performed by any one or a combination of electroless plating, electrolytic plating, screen printing, sputtering, evaporation, inkjet, and dispensing.

[0148] Meanwhile, the first through electrode 160 may be formed in plurality while being horizontally spaced apart within the first insulating layer 111 .

[0149] At this time, the first through electrode 160 may overlap the first circuit layer 120 in the vertical direction. In addition, the first through electrode 160 may include a first-first through electrode 160a overlapping the bump part 121 of the first circuit layer 120 in the vertical direction. In addition, the first through electrode 160 may include a first-second through electrode 160b overlapping the pad 122 of the first circuit layer 120 in the vertical direction.

[0150] At this time, the first through electrode 160 is formed integrally with the first circuit layer 120. This is because the filling of the inside of the through hole penetrating the first insulating layer 111 and the plating process for forming the circuit layer on the first insulating layer 111 are performed simultaneously.

[0151] Therefore, the pad 122 may be integrally formed with the first-second through-electrode 160b. Here, integrally formed may mean that at least one metal layer constituting the pad 122 and at least one metal layer constituting the first-second through-electrode are plated layers formed by a single plating process.

[0152] In addition, the bump component 121 may be formed integrally with the first-first through electrode 160a. For example, the second portion 121B corresponding to the bump portion of the bump component 121 and the first portion 121P corresponding to the pad portion of the bump component 121 are formed integrally. In addition, the first portion 121P of the bump component 121 is formed integrally with the first-first through electrode 160a. Therefore, the second portion 121B of the bump component 121 is formed integrally with the first-first through electrode 160a.

[0153] At this time, in the comparative example, although the through electrode and the pad of the bump part are formed integrally with each other, the through electrode and the bump of the bump part are independent metal layers formed by independent processes. Therefore, the comparative example has problems that the electrical and physical connectivity between them is deteriorated and the signal transmission loss is increased.

[0154] In contrast, the embodiment has a structure in which the first-first through electrode 160a, the first portion 121P of the bump part 121, and the second portion 121B of the bump part 121 are formed integrally with each other. Therefore, the embodiment can improve the electrical and physical connectivity between the first-first through electrode 160a and the bump part 121. Therefore, the embodiment can improve the physical reliability and electrical reliability of the circuit board.

[0155] The circuit board 100 of the embodiment includes a protection layer.

[0156] Specifically, the first protective layer 195 is disposed on the upper surface of the first insulating layer 111. The first protective layer 195 includes at least one opening. Specifically, the first protective layer 195 includes an opening vertically overlapping with the bump part 121 of the first circuit layer 120. At this time, the width of the opening of the first protective layer 195 may be the same as the width of the bump part 121.

[0157] Here, in the comparative example, the width of the opening of the first protective layer is greater than or less than the width of the bump component. This is because due to the tolerance in the exposure and development process of the first protective layer, it is difficult to form the width of the opening of the first protective layer and the width of the bump component to be substantially the same. Therefore, in the comparative example, considering the tolerance, the width of the opening of the first protective layer is increased or the width of the bump component is increased. Therefore, in the comparative example, there is a limitation on reducing the pitch between the plurality of bump components.

[0158] In contrast, in the embodiment, after the bump component 121 is formed to a certain thickness, the first protective layer 195 is formed. Therefore, the embodiment can make the width of the bump component 121 substantially the same as the width of the opening of the first protective layer 195. Thus, the embodiment can further reduce the pitch between the plurality of bump components. Therefore, the embodiment can improve the circuit integration of the circuit board.

[0159] Meanwhile, the circuit board 100 can further include a second protection layer 195 disposed on the lower surface of the third insulating layer 113 .

[0160] The first protective layer 195 and the second protective layer 195 can include an insulating material. The first protective layer 195 and the second protective layer 195 can include various materials, which can be applied and cured by heating to protect the surfaces of the insulating layer and the circuit layer.

[0161] The first protective layer 195 and the second protective layer 195 can be solder resists including organic polymer materials. For example, the first protective layer 195 and the second protective layer 195 can include epoxy acrylate series resins. In detail, the first protective layer 195 and the second protective layer 195 can include resins, curing agents, photoinitiators, pigments, solvents, fillers, additives, acrylic acid series monomers, etc. However, the embodiment is not limited thereto, and the first protective layer 195 and the second protective layer 195 can be any one of a photo solder resist, a cover layer, and a polymer material.

[0162] The thickness of the first protective layer 195 and the second protective layer 195 may be 1 μm to 20 μm. The thickness of the first protective layer 195 and the second protective layer 195 may be 1 μm to 15 μm. For example, the thickness of the first protective layer 195 and the second protective layer 195 may be 5 μm to 20 μm. When the thickness of the first protective layer 195 and the second protective layer 195 exceeds 20 μm, the overall thickness of the circuit board and the semiconductor package may increase.

[0163] Meanwhile, although the circuit board illustrated in the drawing includes the first protection layer 195 and the second protection layer 195 , it is not limited thereto.

[0164] For example, at least one of the first protective layer 195 and the second protective layer 195 may be omitted.

[0165] Preferably, Figure 2 The first protective layer 195 may be omitted in the circuit board 100. Therefore, the upper surface of the first insulating layer 111 and the upper surface and side surface of the first circuit layer 120 may be exposed to the outside of the circuit board 100. In addition, at least a portion of the upper surface of the first insulating layer 111 and the upper surface and side surface of the first circuit layer 120 may be covered by a molding layer in a semiconductor packaging process.

[0166] Meanwhile, although not shown in the drawings, a surface treatment layer may be provided on the first circuit layer 120 of the circuit board 100. For example, the surface treatment layer may be provided on the upper surface of at least one of the bump part 121 and the pad 122 of the first circuit layer 120. The surface treatment layer may be formed to prevent corrosion and oxidation of the circuit layer while increasing solderability.

[0167] The surface treatment layer may be an OSP (Organic Solderability Preservative) layer. Preferably, the surface treatment layer may be an organic layer formed of an organic material such as benzimidazole coated on the circuit layer.

[0168] Different from this, the surface treatment layer may be a plating layer. For example, the surface treatment layer may include a chemical gold (Au) plating layer. For example, the surface treatment layer may include a chemical nickel (Ni) plating layer and a chemical gold (Au) plating layer on the nickel plating layer. For example, the surface treatment layer may include a chemical nickel (Ni) plating layer, a chemical palladium (Pd) plating layer on the nickel plating layer, and a chemical gold (Au) plating layer on the palladium plating layer.

[0169] Hereinafter, circuit layers included in the circuit board of the embodiment will be described in more detail.

[0170] Figure 3 is a cross-sectional view showing the layer structure of the bump component of the first circuit layer of the first embodiment, Figure 4 is a cross-sectional view showing the layer structure of the pad of the first circuit layer of the first embodiment, Figure 5 is a cross-sectional view showing the layer structure of the traces of the first circuit layer of the first embodiment, Figure 6 is a cross-sectional view showing the layer structure of the second circuit layer of the embodiment, and Figure 7 is a cross-sectional view showing the layer structure of the bump component of the first circuit layer of the second embodiment.

[0171] Reference again Figure 2 , the first circuit layer 120 includes a bump part 121, a pad 122, and a trace 123. In addition, the first circuit layer 120, the bump part 121, and the pad 122 have the same layer structure, but at least one has a different thickness from at least one other.

[0172] On the other hand, the second circuit layer 130 has a different layer structure from the first circuit layer 120. For example, the second circuit layer 130 has fewer layers than the first circuit layer 120. For example, the number of layers of the seed layer of the second circuit layer 130 is smaller than that of the first circuit layer 120.

[0173] Meanwhile, the first circuit layer 120 of the embodiment may have different layer structures depending on the manufacturing method. For example, when the first circuit layer 120 is manufactured by the SAP method, the first circuit layer 120 only includes the first to third metal layers 121-1, 121-2 and 121-3, and does not include the fourth metal layer 121-4 corresponding to the copper layer. In addition, when the first circuit layer 120 is manufactured by the MSAP method, the first circuit layer 120 may include the first to fourth metal layers 121-1, 121-2, 121-3 and 121-4 including the copper layer.

[0174] refer to Figure 3 , the circuit board 100 includes a first-first through electrode 160 a passing through the first insulating layer 111 and a bump part 121 of the first circuit layer 120 disposed on the first-first through electrode 160 a .

[0175] At this time, the first-first through electrode 160 a and the bump part 121 are integrally formed.

[0176] The bump part 121 includes a plurality of metal layers. In addition, the first-first through electrode 160a also includes a plurality of metal layers corresponding to the plurality of metal layers of the bump part 121. In addition, each of the plurality of metal layers of the bump part 121 is formed integrally with a corresponding metal layer among the plurality of metal layers of the first-first through electrode 160a. Integrally formed may mean that any one of the plurality of metal layers constituting the bump part 121 and any one of the plurality of metal layers constituting the first-first through electrode 160a are formed as one layer.

[0177] The bump part 121 includes a first metal layer 121-1. The first metal layer 121-1 is disposed on the upper surface of the first insulating layer 111 in the circuit board of the first embodiment.

[0178] The first metal layer 121 - 1 of the bump part 121 may be a chemically plated layer. For example, the first metal layer 121 - 1 of the bump part 121 may be a chemically plated copper layer.

[0179] For example, the first metal layer 121 - 1 of the bump part 121 can be formed by a chemical copper plating method which is performed in the order of a degreasing process, a soft corrosion process, a pre-catalyst treatment process, a catalyst treatment process, an activation process, a chemical plating process, and an anti-oxidation treatment process.

[0180] The first metal layer 121-1 of the bump component 121 can have a first thickness. The first thickness of the first metal layer 121-1 of the bump component 121 can satisfy the range of 0.5μm to 1.5μm. Preferably, the first thickness of the first metal layer 121-1 of the bump component 121 can satisfy the range of 0.7μm to 1.3μm. More preferably, the first thickness of the first metal layer 121-1 of the bump component 121 can satisfy the range of 0.8μm to 1.2μm. If the first thickness of the first metal layer 121-1 of the bump component 121 is less than 0.5μm, the first metal layer 121-1 may not be properly used as a seed layer. If the first thickness of the first metal layer 121-1 of the bump component 121 is greater than 1.5μm, the reliability of the bump component 121 may be deteriorated. For example, if the first thickness of the first metal layer 121-1 of the bump component 121 is greater than 1.5 μm, the depth of the recessed portion (or undercut) may increase in the etching process of the first metal layer 121-1 performed after the bump component 121 is formed. In addition, if the first thickness of the first metal layer 121-1 of the bump component 121 is greater than 1.5 μm, the etching process time may increase. In addition, if the first thickness of the first metal layer 121-1 of the bump component 121 is greater than 1.5 μm, deformation of the third metal layer 123 of the bump component 121 may occur during the etching process of the first metal layer 121-1.

[0181] The bump component 121 may include a second metal layer 121-2 disposed on the first metal layer 121-1. The second metal layer 121-2 of the bump component 121 may be an electrolytic plated layer. For example, the second metal layer 121-2 of the bump component 121 may be a first electrolytic plated layer formed by electrolytic plating using the first metal layer 121-1 of the bump component 121 as a seed layer.

[0182] The second metal layer 121-2 of the bump component 121 may have a second thickness greater than the first thickness of the first metal layer 121-1 of the bump component 121. For example, the second thickness of the second metal layer 121-2 of the bump component 121 may be 1.3 times or more of the first thickness of the first metal layer 121-1 of the bump component 121. For example, the second thickness of the second metal layer 121-2 of the bump component 121 may be 1.5 times or more of the first thickness of the first metal layer 121-1 of the bump component 121. For example, the second thickness of the second metal layer 121-2 of the bump component 121 may be 2 times or more of the first thickness of the first metal layer 121-1 of the bump component 121.

[0183] The second thickness of the second metal layer 121-2 of the bump component 121 can satisfy the range of 3 μm to 5 μm. For example, the second thickness of the second metal layer 121-2 of the bump component 121 can satisfy the range of 3.2 μm to 4.8 μm. For example, the second thickness of the second metal layer 121-2 of the bump component 121 can satisfy the range of 3.5 μm to 4.5 μm.

[0184] If the second thickness of the second metal layer 121-2 of the bump component 121 is less than 3μm, the effect of forming the second metal layer 121-2 may not be significant. For example, the second metal layer 121-2 of the bump component 121 can have the function of reducing the depth of the recessed portion in the etching process of the first metal layer 121-1, while improving the workability in the plating process of the bump component 121. For example, the second metal layer 121-2 of the bump component 121 can have the function of reducing the thickness deviation between multiple bump components. In addition, if the second thickness of the second metal layer 121-2 of the bump component 121 is less than 3μm, the effect of the second metal layer 121-2 may not be significant. If the second thickness of the second metal layer 121-2 of the bump component 121 exceeds 5μm, the process time in the process of etching the second metal layer 121-2 may increase.

[0185] The first metal layer 121-1 and the second metal layer 121-2 of the bump part 121 are used as seed layers for forming the third metal layer 121-3 by electrolytic plating. Specifically, the first metal layer 121-1 is used as a seed layer for forming the second metal layer 121-2 by electrolytic plating. In addition, the first metal layer 121-1 and the second metal layer 121-2 are used as seed layers for forming the third metal layer 121-3 by electrolytic plating.

[0186] That is, the bump component 121 includes a third metal layer 121-3 disposed on the second metal layer 121-2 of the bump component 121. The third metal layer 121-3 is an electrolytic plating layer formed by electrolytically plating the first metal layer 121-1 and the second metal layer 121-2 as a seed layer. For example, the third metal layer 121-3 of the bump component 121 may also be referred to as a second electrolytic plating layer of the bump component 121.

[0187] The third thickness of the third metal layer 121-3 of the bump component 121 may exceed 95 μm. For example, the third thickness of the third metal layer 121-3 of the bump component 121 may exceed 115 μm. The third thickness of the third metal layer 121-3 of the bump component 121 may exceed 135 μm. The third thickness of the third metal layer 121-3 of the bump component 121 may exceed 155 μm. The third thickness of the third metal layer 121-3 of the bump component 121 may exceed 195 μm.

[0188] That is, the bump component 121 includes a first metal layer 121-1, a second metal layer 121-2, and a third metal layer 121-3. In addition, the thickness T1 of the bump component 121 including the first metal layer 121-1, the second metal layer 121-2, and the third metal layer 121-3 can meet the range of 100um to 220um. Preferably, the thickness T1 of the bump component 121 can meet the range of 110um to 215um. More preferably, the thickness T1 of the bump component 121 can meet the range of 115um to 210um.

[0189] If the thickness T1 of the bump component 121 is less than 100 μm, the external substrate (e.g., the main board of the electronic device) may not be stably bonded to the first bump component 121. For example, if the thickness T1 of the bump component 121 exceeds 220 μm, the rigidity of the bump component 121 may be reduced, and therefore, reliability problems such as collapse may occur in a state where the external substrate is coupled. In addition, if the thickness T1 of the bump component 121 exceeds 220 μm, the thickness deviation between the plurality of bump components may increase, and therefore, the time of the polishing process may increase. In addition, if the thickness T1 of the bump component 121 exceeds 220 μm, the thickness of the circuit board 100 and the thickness of the semiconductor package may increase.

[0190] In an embodiment, the bump component 121 includes a first metal layer 121-1, a second metal layer 121-2, and a third metal layer 121-3. In addition, the second metal layer 121-2 is a first electroplated layer in which the first metal layer 121-1 is electroplated as a seed layer, and the third metal layer 121-3 is a second electroplated layer in which the first metal layer 121-1 and the second metal layer 121-2 are electroplated as a seed layer.

[0191] Therefore, the embodiment can minimize the depth of the recessed portion generated in the etching process of the seed layer performed after the circuit layer is formed. That is, the second metal layer 121-2 can have a higher metal density than the first metal layer 121-1 as an electrolytic plating layer. Therefore, the second metal layer 121-2 can be used as a barrier layer, which minimizes the depth of the recessed portion formed at the side surface of the first metal layer 121-1 during the etching process. In addition, the second metal layer 121-2 can play a role in preventing the third metal layer 121-3 from deforming during the etching process. Therefore, the embodiment can minimize the depth of the recessed portion formed at the lower side surface of the bump component 121 by further including the second metal layer 121-2. Therefore, the embodiment can improve the physical reliability and electrical reliability of the bump component 121.

[0192] In addition, the third metal layer 121 - 3 of the bump part 121 is plated not only with the first metal layer 121 - 1 but also with the second metal layer 121 - 2 as a seed layer. Therefore, the embodiment can minimize thickness deviation among a plurality of bump parts included in the circuit board 100 .

[0193] Specifically, in the circuit board of the comparative example, the electroplating of the bump component is performed using only a chemical copper plating layer as a seed layer. At this time, the bump component has a thickness of 100um or more. Therefore, when plating a metal layer with a thickness of 100um or more, it is difficult to perform a plating process with uniform thickness over the entire area using only a chemical copper plating layer. Therefore, in the circuit board of the comparative example, the thickness deviation of each bump component exceeds 30% compared with the average value of the thickness of a plurality of bump components. For example, when the average value is 100um, the thickness of at least one bump component among the plurality of bump components is less than 70um or exceeds 130um. Therefore, the circuit board of the comparative example performs a plating process to have a thickness greater than the target thickness, so as to match the thickness of each bump component. Therefore, the problem of the comparative example is that while the thickness of the bump component is finally adjusted to the target thickness, a polishing process must be included to make the thickness uniform, and the polishing process time increases.

[0194] In contrast, the embodiment uses not only the first metal layer 121-1 of the bump component 121, but also the second metal layer 121-2 as a seed layer to perform electrolytic plating on the third metal layer 121-3 of the bump component 121. Therefore, the embodiment can minimize the thickness deviation between the plurality of bump components. Therefore, the embodiment can perform the plating process under the condition that the bump component 121 has a thickness corresponding to the target thickness. Therefore, the embodiment can omit the polishing process or greatly shorten the polishing process time.

[0195] Specifically, the circuit board 100 of the embodiment includes a plurality of bump components 121a and 121b spaced apart from each other in the horizontal direction. Then, the embodiment can adjust the thickness deviation of each bump component 121a and 121b to 20% or less based on the average value of the thickness of the plurality of bump components 121a and 121b. For example, the embodiment can adjust the thickness deviation of each bump component 121a and 121b to 15% or less based on the average value of the thickness of the plurality of bump components 121a and 121b. For example, the embodiment can adjust the thickness deviation of each bump component 121a and 121b to 10% or less based on the average value of the thickness of the plurality of bump components 121a and 121b.

[0196] Meanwhile, the first through electrode 160 of the circuit board of the embodiment includes the first-first through electrode 160a overlapping the bump part 121 in the vertical direction. In addition, the first-first through electrode 160a may have a layer structure corresponding to the bump part 121.

[0197] For example, the first-first through electrode 160 a may include first, second, and third metal layers 161 , 162 , and 163 of the first-first through electrode 160 a corresponding to the first, second, and third metal layers 121 - 1 , 121 - 2 , and 121 - 3 of the bump part 121 .

[0198] The first metal layer 161 of the first-first through electrode 160a may correspond to the first metal layer 121-1 of the bump part 121. In other words, the first metal layer 161 of the first-first through electrode 160a may be integrally formed with the first metal layer 121-1 of the bump part 121.

[0199] In addition, the second metal layer 162 of the first-first through electrode 160a may correspond to the second metal layer 121-2 of the bump part 121. In other words, the second metal layer 162 of the first-first through electrode 160a may be integrally formed with the second metal layer 121-2 of the bump part 121.

[0200] In addition, the third metal layer 163 of the first-first through electrode 160a may correspond to the third metal layer 121-3 of the bump part 121. In other words, the third metal layer 163 of the first-first through electrode 160a may be integrally formed with the third metal layer 121-3 of the bump part 121.

[0201] Therefore, the bump part 121 of the embodiment may have a structure integrally formed with the first-first through electrode 160 a of the first through electrode 160 .

[0202] At the same time, reference Figure 4 , the first circuit layer 120 includes a pad 122 . At this time, a thickness T2 of the pad 122 is smaller than a thickness T1 of the bump part 121 .

[0203] At this time, the pad 122 includes first to third metal layers 122 - 1 , 122 - 2 , and 122 - 3 .

[0204] In addition, the first metal layer 122 - 1 and the second metal layer 122 - 2 of the pad 122 correspond to the first metal layer 121 - 1 and the second metal layer 121 - 2 of the bump part 121 .

[0205] At this time, the third metal layer 122 - 3 of the pad 122 is the same as the third metal layer 121 - 3 of the bump part 121 in that the first metal layer 122 - 1 and the second metal layer 122 - 2 of the pad 122 are electrolytically plated as a seed layer.

[0206] However, the thickness of the third metal layer 122-3 of the pad 122 is smaller than that of the bump part 121. In other words, the thickness of the third metal layer 122-3 of the pad 122 can be determined based on the overall thickness T2 of the pad 122.

[0207] In addition, the circuit board 100 includes first-second through electrodes 160 b vertically overlapping the pads 122 .

[0208] The first-second through-electrode 160 b may have a layer structure corresponding to that of the pad 122 .

[0209] For example, the first-second through electrode 160b may include a first metal layer 161 of the first-second through electrode 160b corresponding to the first metal layer 122-1 of the pad 122. The first metal layer 161 of the first-second through electrode 160b may be integrally formed with the first metal layer 122-1 of the pad 122.

[0210] For example, the first-second through electrode 160b may include a second metal layer 162 of the first-second through electrode 160b corresponding to the second metal layer 122-2 of the pad 122. The second metal layer 162 of the first-second through electrode 160b may be integrally formed with the second metal layer 122-2 of the pad 122.

[0211] For example, the first-second through electrode 160b may include a third metal layer 163 of the first-second through electrode 160b corresponding to the third metal layer 122-3 of the pad 122. The third metal layer 163 of the first-second through electrode 160b may be integrally formed with the third metal layer 122-3 of the pad 122.

[0212] At the same time, reference Figure 5 , the trace 123 of the first circuit layer 120 may include first to third metal layers 123 - 1 , 123 - 2 , 123 - 3 .

[0213] At this time, the first to third metal layers 123-1, 123-2, 123-3 of the trace 123 may correspond to the first to third metal layers 122-1, 122-2, 122-3 of the pad 122. In addition, the thickness T3 of the trace 123 may correspond to the thickness T2 of the pad 122.

[0214] Therefore, a detailed description of the first to third metal layers 123 - 1 , 123 - 2 , 123 - 3 of the trace 123 will be omitted.

[0215] At the same time, reference Figure 6 , the second circuit layer 130 of the circuit board 100 may have a layer structure different from that of the first circuit layer 120. For example, the number of layers of the second circuit layer 130 may be different from that of the first circuit layer 120. For example, the number of layers of the metal layer of the second circuit layer 130 may be less than that of the metal layer of the first circuit layer 120.

[0216] Accordingly, the second through electrode 170 passing through the second insulating layer 112 of the circuit board 100 may have a layer structure different from that of the first through electrode 160. For example, the second through electrode 170 may include a metal layer having a smaller number of layers than that of the first through electrode 160.

[0217] For example, the second circuit layer 130 includes a first metal layer 130-1 corresponding to the first metal layer (122-1 or 123-1) of the pad 122 or the trace 123 of the first circuit layer 120. In addition, the second circuit layer 130 includes a third metal layer 130-2 corresponding to the third metal layer (122-3 or 123-3) of the pad 122 or the trace 123 of the first circuit layer 120. In other words, compared with the pad 122 or the trace 123 of the first circuit layer 120, the second circuit layer 130 may have a structure that does not include the second metal layer (122-2 or 123-2) of the pad 122 or the trace 123.

[0218] In addition, the second through-electrode 170 includes a first metal layer 171 corresponding to the first metal layer 160-1 of the first-first through-electrode 160a or the first-second through-electrode 160b. In addition, the second through-electrode 170 includes a second metal layer 172 corresponding to the third metal layer 160-3 of the first-first through-electrode 160a or the first-second through-electrode 160b. In other words, compared with the first-first through-electrode 160a or the first-second through-electrode 160b, the second through-electrode 170 may have a structure that does not include the second metal layer 160-2 of the first-first through-electrode 160a or the first-second through-electrode 160b.

[0219] At the same time, reference Figure 7 , the circuit board 100 of the embodiment can be manufactured by the MSAP process.

[0220] Specifically, Figures 3 to 5In contrast, the first circuit layer 120 may further include a fourth metal layer. In other words, each of the bump part 121, the pad 122, and the trace 123 of the first circuit layer 120 may further include a fourth metal layer disposed between the upper surface of the first insulating layer 111 and the first metal layer. In contrast, the first through electrode 160 may include Figures 3 to 5 The first to third metal layers 161 , 162 , and 163 are described.

[0221] At this time, the bump part 121, the pad 122, and the trace 123 of the first circuit layer 120 all include the same fourth metal layer. Therefore, the following description will focus on the fourth metal layer 121-4 of the bump part 121.

[0222] The bump part 121 of the first circuit layer 120 further includes a fourth metal layer 121-4. The fourth metal layer 121-4 is disposed between the first metal layer 121-1 of the bump part 121 and the upper surface of the first insulating layer 111. The fourth metal layer 121-4 may be a copper foil layer. Specifically, the fourth metal layer 121-4 may be a copper foil attached to the upper surface of the first insulating layer 111 in the process of laminating the first insulating layer 111.

[0223] In addition, the circuit board 100 of the second embodiment is manufactured using the MSAP process, and therefore, the circuit layer forming process is performed without removing the fourth metal layer 121 - 4 , which is a copper layer disposed on the upper surface of the first insulating layer 111 .

[0224] The fourth metal layer 121-4 may have a fourth thickness. For example, the fourth thickness of the fourth metal layer 121-4 may satisfy the range of 0.8 μm to 2 μm. The fourth thickness of the fourth metal layer 121-4 may satisfy the range of 1.0 μm to 1.8 μm. The fourth thickness of the fourth metal layer 121-4 may satisfy the range of 1.2 μm to 1.6 μm. If the fourth thickness of the fourth metal layer 121-4 is less than 0.8 μm, reliability issues such as reduced flatness may occur in the process of laminating the first insulating layer 111. If the fourth thickness of the fourth metal layer 121-4 exceeds 2 μm, processability in the process of etching the fourth metal layer 121-4 (for example, a process of etching a seed layer or a process of forming a through hole) may be deteriorated.

[0225] Therefore, the thickness T5 of the bump part 121 of the second embodiment may be greater than the thickness T1 of the bump part 121 of the first embodiment by the fourth thickness of the fourth metal layer 121 - 4 .

[0226] Hereinafter, a recessed portion formed at a lower region of the bump part 121 of the embodiment will be described.

[0227] Figure 8 According to the first embodiment Figure 7 A magnified view of area A, and Fig. 9 According to the second embodiment Figure 7 Magnified view of area A.

[0228] refer to Figure 8 and Fig. 9 , the first circuit layer 120 of the embodiment may include a recessed portion formed in a lower region adjacent to the upper surface of the first insulating layer 111. The recessed portion may also be referred to as an undercut. The recessed portions may be formed in lower regions of the bump component 121, the pad 122, and the trace 123 of the first circuit layer 120, respectively.

[0229] Specifically, refer to Figure 7 , the recessed portion may be formed in the first metal layer and the fourth metal layer of each of the bump part 121 , the pad 122 , and the trace 123 .

[0230] Differently, reference Figure 8 , the recessed portion may be formed in the first, second and fourth metal layers.

[0231] Hereinafter, a description will be given of the recessed portion formed in the bump part 121. In addition, recessed portions may also be formed in the pad 122 and the trace 123 of the first circuit layer 120 corresponding to the recessed portion formed in the bump part 121.

[0232] At this time, there is no interface between the bump part 121 and the first-first through electrode 160a. That is, the absence of the interface may mean that the bump part 121 and the first-first through electrode 160a are formed integrally with each other.

[0233] refer to Figure 7 , the recessed portion in the bump part 121 may be formed in the first metal layer 121-1 and the fourth metal layer 121-4 of the bump part 121. In addition, when the bump part 121 is formed by the SAP process, the recessed portion of the bump part 121 may be formed only in the first metal layer 121-1 of the bump part 121.

[0234] Therefore, the bump part 121 may include a portion in which the width thereof changes in the thickness direction.

[0235] For example, the width of the bump component 121 in the region where the first metal layer 121-1 is disposed may be smaller than the width in the region where the third metal layer 121-3 is disposed. In addition, the width of the bump component 121 in the region where the fourth metal layer 121-4 is disposed may be smaller than the width in the region where the third metal layer 121-3 is disposed.

[0236] In addition, the width of the bump part 121 in the region where the first metal layer 121-1 is provided may be smaller than the width in the region where the second metal layer 121-2 is provided. In addition, the width of the bump part 121 in the region where the second metal layer 121-2 is provided may be larger than the width in the region where the fourth metal layer 121-4 is provided.

[0237] In addition, the bump part 121 has a width in a region where the second metal layer 121 - 2 is disposed, which may be the same as the width in a region where the third metal layer 121 - 3 is disposed.

[0238] At this time, the embodiment additionally forms the second metal layer 121-2 on the first metal layer 121-1, and forms the third metal layer 121-3 using the formed second metal layer 121-2 as an additional seed layer. In addition, the embodiment can prevent the second metal layer 121-2 from excessively etching the first metal layer 121-1 in the process of etching the seed layer after forming the third metal layer 121-3. Therefore, the embodiment can minimize the depth of the recessed portion (specifically, the width of the recessed portion in the horizontal direction).

[0239] Likewise, reference Figure 8 , the recessed portion in the bump component 121 may be formed in the first metal layer 121-1, the second metal layer 121-2, and the fourth metal layer 121-4 of the bump component 121. In addition, when the bump component 121 is formed by the SAP process, the recessed portion of the bump component 121 may be formed in the first metal layer 121-1 and the second metal layer 121-2 of the bump component 121.

[0240] Therefore, the bump part 121 may include a portion in which the width thereof changes in the thickness direction.

[0241] For example, the width of the bump component 121 in the region where the first metal layer 121-1 is provided may be smaller than the width in the region where the third metal layer 121-3 is provided. In addition, the width of the bump component 121 in the region where the fourth metal layer 121-4 is provided may be smaller than the width in the region where the third metal layer 121-3 is provided. In addition, the width of the bump component 121 in the region where the second metal layer 121-2 is provided may be smaller than the width in the region where the third metal layer 121-3 is provided.

[0242] At this time, in the embodiment, a portion of the recessed portion may also be formed in the second metal layer 121-2. However, the depth of the recessed portion in the second metal layer 121-2 is less than the depth of the recessed portion in the first metal layer 121-1.

[0243] For example, at least a portion of the region where the second metal layer 121-2 is provided has a width greater than that of the region where the first metal layer 121-1 is provided. In addition, in the embodiment, although a recessed portion can be formed in the second metal layer 121-2 of the bump part 121, the depth of the recessed portion formed at the second metal layer 121-2 can be minimized, and further, the depth of the recessed portion formed by the second metal layer 121-2 at the first metal layer 121-1 and the fourth metal layer 121-4 can also be minimized.

[0244] The circuit board of the embodiment includes an insulating layer, a through electrode passing through the insulating layer, and a first circuit layer disposed on the insulating layer. In this case, the first circuit layer includes a bump component. The bump component is provided to pass through a protective layer disposed on the insulating layer and protrude on the protective layer.

[0245] The bump component includes a first portion disposed on the insulating layer and the through electrode, and a second portion on the first portion. There is no interface between the first portion and the second portion of the bump component. In other words, the first portion and the second portion are formed integrally with each other. In addition, the through electrode is formed integrally with the first portion and the second portion of the bump component. In other words, there is no interface between the through electrode and the bump component.

[0246] Therefore, the bump component of the embodiment does not have an additional layer disposed between the first portion and the second portion. Specifically, the bump component does not have a seed layer between the first portion and the second portion. Thus, the embodiment can improve the physical connectivity and electrical connectivity between the first portion and the second portion of the bump component. In addition, the bump component of the embodiment is formed integrally with the through electrode, and thus the electrical and physical reliability can be further improved.

[0247] At this time, in the comparative example, the pad part and the bump part are formed by separate plating processes separated from each other. Therefore, the comparative example has the problem that the electrical and physical connectivity between them is reduced and the signal transmission loss is increased. In addition, the comparative example has a structure in which a seed layer is additionally provided between the pad part and the bump part, and therefore the overall reliability of the bump part is reduced due to the physical reliability problem of the seed layer.

[0248] In contrast, the embodiment has a structure in which the through electrode, the first portion of the bump component and the second portion of the bump component are formed integrally with each other. Therefore, the embodiment can improve the electrical and physical connectivity between the through electrode and the bump component. Therefore, the embodiment can improve the physical reliability and electrical reliability of the circuit board.

[0249] In addition, the bump component of the embodiment includes a first metal layer, a second metal layer and a third metal layer. In addition, the second metal layer is a first electroplated layer in which the first metal layer is electroplated as a seed layer, and the third metal layer is a second electroplated layer in which the first metal layer and the second metal layer are electroplated as a seed layer.

[0250] Therefore, the embodiment can minimize the depth of the recessed portion generated in the etching process of the seed layer performed after the circuit layer is formed. That is, the second metal layer can have a higher strength than the first metal layer as an electroplating layer. Therefore, the second metal layer can be used as a barrier layer, which minimizes the depth of the recessed portion generated at the side surface of the first metal layer in the etching process. In addition, the second metal layer can play a role in preventing the third metal layer from deforming in the etching process. Therefore, by further including the second metal layer in the bump component, the embodiment can minimize the depth of the recessed portion formed at the lower side surface of the bump component. Therefore, the embodiment can improve the physical reliability and electrical reliability of the bump component.

[0251] In addition, the third metal layer of the bump part is plated not only on the first metal layer but also on the second metal layer as a seed layer. Therefore, the embodiment can minimize the thickness deviation between the plurality of bump parts included in the circuit board.

[0252] Specifically, in the circuit board of the comparative example, only the chemical copper plating layer is used as the seed layer to perform the plating of the bump component. At this time, the bump component has a thickness of 100 μm or more. Therefore, when the plating has a metal layer with a thickness of 100 μm or more, it is difficult to perform a plating process with uniform thickness over the entire area using only the chemical copper plating layer. Therefore, in the circuit board of the comparative example, the thickness deviation of each bump component exceeds 30% compared with the average value of the thickness of the plurality of bump components. For example, when the average value is 100 μm, the thickness of at least one bump component among the plurality of bump components is less than 70 μm or exceeds 130 μm. Therefore, in the circuit board of the comparative example, the plating process is performed so that the thickness of each bump component is greater than the target thickness, so as to match the thickness of each bump component. Therefore, the comparative example has the following problem: while the thickness of the bump component is finally adjusted to the target thickness, a polishing process must be included to make the thickness uniform, and the polishing process time increases.

[0253] In contrast, the embodiment not only uses the first metal layer of the bump component, but also uses the second metal layer as a seed layer to perform electrolytic plating on the third metal layer of the bump component. Therefore, the embodiment can minimize the thickness deviation between the plurality of bump components. Therefore, the embodiment can perform the plating process under the condition that the bump component has a thickness corresponding to the target thickness. Therefore, the embodiment can omit the polishing process or greatly shorten the polishing process time.

[0254] Specifically, in the circuit board of the comparative example, only the chemical copper plating layer is used as the seed layer to perform the plating of the bump component. At this time, the bump component has a thickness of 100 μm or more. Therefore, when the plating has a metal layer with a thickness of 100 μm or more, it is difficult to perform a plating process with uniform thickness over the entire area using only the chemical copper plating layer. Therefore, in the circuit board of the comparative example, the thickness deviation of each bump component exceeds 30% compared with the average value of the thickness of the plurality of bump components. For example, when the average value is 100 μm, the thickness of at least one bump component among the plurality of bump components is less than 70 μm or exceeds 130 μm. Therefore, in the circuit board of the comparative example, the plating process is performed so that the thickness of each bump component is greater than the target thickness, so as to match the thickness of each bump component. Therefore, the comparative example has the following problem: while the thickness of the bump component is finally adjusted to the target thickness, a polishing process must be included to make the thickness uniform, and the polishing process time increases.

[0255] In contrast, the embodiment not only uses the first metal layer of the bump component, but also uses the second metal layer as a seed layer to perform electrolytic plating on the third metal layer of the bump component. Therefore, the embodiment can minimize the thickness deviation between the plurality of bump components. Therefore, the embodiment can perform the plating process under the condition that the bump component has a thickness corresponding to the target thickness. Therefore, the embodiment can omit the polishing process or greatly shorten the polishing process time.

[0256] Fig.10 2 is a view showing a semiconductor package according to an embodiment.

[0257] refer to Fig.10 , the semiconductor package of the embodiment may have a Figure 2 A structure in which a plurality of chips and an external substrate are arranged on a circuit board.

[0258] To this end, the circuit board includes a bump part 121 and a pad 122 of a first circuit layer 120 .

[0259] In addition, the semiconductor package may include a first adhesive part 210 disposed on the pad 122 of the circuit board. In addition, the semiconductor package may include a second adhesive part 240 disposed on the bump part 121.

[0260] The first adhesive member 210 and the second adhesive member 240 may have the same shape, or may have different shapes.

[0261] For example, the first adhesive component 210 and the second adhesive component 240 may have a hexahedral shape. For example, the cross-section of the first adhesive component 210 and the second adhesive component 240 may include a square. The cross-section of the first adhesive component 210 and the second adhesive component 240 may include a rectangle or a square. For example, the first adhesive component 210 and the second adhesive component 240 may include a spherical shape. For example, the cross-section of the first adhesive component 210 and the second adhesive component 240 may include a circle or a semicircle. For example, the cross-section of the first adhesive component 210 and the second adhesive component 240 may include a partial or full circle. The cross-sectional shape of the first adhesive component 210 and the second adhesive component 240 may be flat on one side and curved on the other side. The first adhesive component 210 and the second adhesive component 240 may be a solder ball, but is not limited thereto.

[0262] Embodiments may include a chip 220 disposed on the first adhesive portion 210. The chip 220 may be a first processor chip. For example, the chip 220 may be an application processor (AP) chip among a central processing unit (e.g., CPU), a graphics processor (e.g., GPU), a digital signal processor, an encryption processor, a microprocessor, and a microcontroller. The terminal 225 of the chip 220 may be electrically connected to the pad 122 through the first adhesive portion 210.

[0263] Additionally, embodiments may include an external substrate 250 coupled to the second adhesive portion 240. The external substrate 250 may include a terminal portion 255 electrically connected to the second adhesive member 240 on the lower surface.

[0264] The external substrate 250 may be a main board. For example, the external substrate 250 may be a main board of an electronic device.

[0265] Alternatively, the external substrate 250 may be an interposer. For example, the external substrate 250 may be an interposer that connects the semiconductor package of the embodiment and another package (eg, a memory package).

[0266] Alternatively, the external substrate 250 may be a memory substrate or a memory package on which a memory chip is mounted.

[0267] The semiconductor package may include a mold layer 230 . The mold layer 230 may be provided to cover the chip 220 and the bump part 121 .

[0268] If the first protective layer 195 is omitted from the circuit board, the mold layer 230 may be disposed to cover the devices disposed on the upper side of the circuit board.

[0269] The mold layer 230 may be EMC (Epoxy Molding Compound) formed to protect the mounted chip 220 , but is not limited thereto.

[0270] At this time, the mold layer 230 may have a low dielectric constant to enhance the heat dissipation characteristics. For example, the dielectric constant (Dk) of the mold layer 230 may be 0.2 to 10. For example, the dielectric constant (Dk) of the mold layer 230 may be 0.5 to 8. For example, the dielectric constant (Dk) of the mold layer 230 may be 0.8 to 5. Therefore, the embodiment allows the mold layer 230 to have a low dielectric constant, thereby improving the heat dissipation characteristics of the heat generated from the chip 220.

[0271] Meanwhile, the semiconductor package may include a third adhesive member 260 disposed at the lowermost side of the circuit board The third adhesive member 260 may be disposed on the lower surface of the fourth circuit layer 150 exposed through the opening of the second protective layer 195 .

[0272] Hereinafter, a method for manufacturing a circuit board according to an embodiment will be described.

[0273] Figures 11 to 22 It is shown in the order of process Figure 2 A cross-sectional view of a method of manufacturing a circuit board is illustrated.

[0274] refer to Fig.11 , the embodiment can proceed to the process of manufacturing the inner layer of the circuit board 100. To this end, the embodiment prepares the second insulating layer 112. Then, the embodiment forms a through hole in the second insulating layer 112. Thereafter, the embodiment can proceed to the process of forming the second circuit layer 130 disposed on the upper surface of the second insulating layer 112 and the third circuit layer 140 disposed on the lower surface of the second insulating layer 112 together with the second through electrode 170 filling the through hole of the second insulating layer 112.

[0275] Meanwhile, if the circuit board 100 of the embodiment is not a core board, it is able to perform a process of manufacturing an inner layer using a carrier board.

[0276] In addition, if the circuit board 100 has a multi-layer structure of four or more layers, the process of manufacturing the inner layer can be repeatedly performed a plurality of times.

[0277] Next, refer to Fig.12 , the embodiment can continue the process of manufacturing the outer layer on the manufactured inner layer.

[0278] To this end, the embodiment can continue the process of stacking the first insulating layer 111 on the second insulating layer 112. At this time, the first insulating layer 111 can have a structure in which the copper layer M1 is stacked. In addition, the copper layer M1 can be removed and disappear in the SAP process, and can form a part of the first circuit layer 120 in the MSAP process.

[0279] In this regard, the embodiment can continue the process of laminating the third insulating layer 113 under the second insulating layer 112. At this time, the embodiment can have a structure in which the copper layer M2 is laminated under the third insulating layer 113. In addition, the copper layer M2 can be removed and disappear in the SAP process, and can form a part of the fourth circuit layer 150 in the MSAP process.

[0280] Next, refer to Fig.13 , the embodiment may perform a process of forming a via hole by processing the first insulating layer 111 and the third insulating layer 113. For example, the embodiment may perform a process of forming a first via hole VH1 by processing the first insulating layer 111 and the copper layer M1.

[0281] In addition, embodiments may perform a process of forming the second via hole VH2 by processing the third insulating layer 113 and the copper layer M2 .

[0282] Meanwhile, the embodiment may perform a process of forming the first circuit layer 120 and the first through electrode 160 in the first insulating layer 111 and a process of forming the fourth circuit layer 150 and the third through electrode 180 in the third insulating layer 113 .

[0283] Hereinafter, the manufacturing process will be described based on the manufacturing process of forming the first circuit layer 120 and the first through electrode 160 in the first insulating layer 111. In addition, the process of forming the fourth circuit layer 150 and the third through electrode 180 in the third insulating layer 113 may be performed accordingly.

[0284] refer to Fig.14 , the embodiment may perform a process of forming a chemical plating layer M2 on the copper layer M1 and the inner wall of the first through hole VH1 after forming the first through hole VH1. At this time, the chemical plating layer M2 may mean a chemical copper plating layer.

[0285] The chemical plating layer M2 may also be disposed on the upper surface of the second circuit layer 120 vertically overlapping the first via hole VH1. The chemical plating layer M2 constitutes a first metal layer of each of the bump part 121, the pad 122, and the trace 123 of the first circuit layer 120 in the circuit board.

[0286] refer to Fig.15 , an embodiment may perform a process of forming a first electrolytic plating layer M3 on the chemical plating layer M2. The first electrolytic plating layer M3 can be formed by performing primary electrolytic plating using the chemical plating layer M2 as a seed layer. In addition, the first electrolytic plating layer M3 constitutes a second metal layer of each of the bump parts 121, the pads 122, and the traces 123 of the first circuit layer 120 in the circuit board. The first electrolytic plating layer M3 can be formed to correspond to the surface profile of the chemical plating layer M2.

[0287] refer to Fig.16, the embodiment enables a process of forming a first mask DF1 on the first electrolytic plating layer M3. At this time, the first mask DF1 includes a first opening area OR1 and a second opening area OR2. Preferably, the first mask DF1 may be formed with a first opening area OR1 corresponding to an area in the upper area of ​​the first electrolytic plating layer M3 where the pad 122 of the first circuit layer 120 and the first through electrode 160 are to be set. In addition, the first mask DF1 may be formed with a second opening area OR2 corresponding to an area in the upper area of ​​the first electrolytic plating layer M3 where the trace 123 of the first circuit layer 120 is to be set. At this time, the first mask DF1 is set to cover an area in the upper area of ​​the first electrolytic plating layer M3 where the bump component 121 is to be set.

[0288] refer to Fig.17 , the embodiment forms a process of forming a second electrolytic plating layer M4 by performing electrolytic plating on the chemical plating layer M2 and the first electrolytic plating layer M3 as a seed layer. Therefore, a second electrolytic plating layer M4 corresponding to the first opening area OR1 and the second opening area OR2 of the first mask DF1 can be formed. The second electrolytic plating layer M4 can constitute the first-second through electrode 160b of the first through electrode 160, the pad 122 of the first circuit layer 120, and the third metal layer of the trace 123.

[0289] Next, refer to Fig.18 , the embodiment can perform a process of removing the first mask DF1 disposed on the first electrolytic plating layer M3.

[0290] Next, refer to Fig.19 , the embodiment can perform a process of forming a second mask DF2 on the first electrolytic plating layer M3 and the second electrolytic plating layer M4. The second mask DF2 can include a third opening area OR3. The third opening area OR3 can be formed corresponding to the area where the bump part 121 of the first through electrode 160 and the first-first through electrode 160a are to be set in the upper area of ​​the first electrolytic plating layer M3.

[0291] Next, refer to Fig. 20 , the embodiment may perform electrolytic plating on the chemical plating layer M2 as a seed layer and the first electrolytic plating layer M3 to form a third electrolytic plating layer M5 filling the third opening region OR3 of the second mask DF2. At this time, the third electrolytic plating layer M5 may constitute a third metal layer of each of the first-first through electrode 160a and the bump part 121.

[0292] Next, refer to Fig.21 , embodiments may perform a process of removing the second mask DF2.

[0293] Next, refer to Fig. 22, the embodiment can perform an etching process to remove the copper layer M1 , the chemical plating layer M2 , and the first electrolytic plating layer M3 in a region that does not vertically overlap with the second electrolytic plating layer M4 and the third electrolytic plating layer M5 .

[0294] Through this, the embodiment can form a first circuit layer 120, which includes a bump component 121, a pad 122, and a trace 123 formed integrally with the first through electrode, and includes first to fourth metal layers respectively. At this time, in the etching process, a first recessed portion 121U can be formed at the side surface of the lower region of the bump component 121. In addition, in the etching process, a second recessed portion 122U can be formed at the side surface of the lower region of the pad 122. In addition, in the etching process, a third recessed portion 123U can be formed at the side surface of the lower region of the trace 123.

[0295] The characteristics, structures and effects described in the above embodiments are at least included in one embodiment, but are not limited to one embodiment. In addition, those skilled in the art can combine or modify the characteristics, structures and effects described in each embodiment for other embodiments. Therefore, it should be understood that the content related to such combination and such modification is included in the scope of the present invention.

[0296] The embodiments are mainly described above. However, they are only examples and do not limit the present invention. It will be appreciated by those skilled in the art that several variations and applications not mentioned above may be made without departing from the essential characteristics of the embodiments. For example, each component specifically shown in the embodiments may be varied. In addition, it should be understood that the differences associated with such variations and such applications are included within the scope of the present invention defined in the following claims.

Claims

1. A semiconductor package, comprising: Insulation layer; a protective layer, the protective layer being disposed on the insulating layer; A through electrode, wherein the through electrode passes through the insulating layer; as well as a bump component provided on the through-electrode and passing through the protective layer, The bump component includes: a first portion connected to the through-electrode; and a second portion disposed on the first portion and protruding onto the protective layer, and The width of the first portion in the horizontal direction is the same as the width of the second portion in the horizontal direction.

2. The semiconductor package according to claim 1, wherein A width of the first portion in the horizontal direction is greater than a width of an upper surface of the through electrode.

3. The semiconductor package according to claim 1, wherein: The first portion and the second portion of the projection member are integrally formed.

4. The semiconductor package according to claim 1, wherein: The first portion and the second portion of the bump member are formed integrally with the through-electrode.

5. The semiconductor package according to claim 1, wherein The bump component includes a plurality of metal layers, and Wherein, a width of at least one of the plurality of metal layers is different from a width of at least another of the plurality of metal layers.

6. The semiconductor package according to claim 5, wherein: The plurality of metal layers include: a first metal layer, the first metal layer being disposed on the insulating layer, a second metal layer, the second metal layer being disposed on the first metal layer; and a third metal layer, the third metal layer being disposed on the second metal layer, Wherein, the width of the first metal layer is smaller than the width of the third metal layer.

7. The semiconductor package according to claim 6, wherein: The width of the second metal layer is greater than the width of the first metal layer.

8. The semiconductor package according to claim 6, wherein: The width of the third metal layer is greater than the width of the second metal layer.

9. The semiconductor package according to claim 6, wherein: The first metal layer is a chemically plated copper layer, wherein the second metal layer is a first electrolytic plating layer, and Wherein, the third metal layer is a second electrolytic plating layer.

10. The semiconductor package according to claim 6, wherein The bump feature further includes a fourth metal layer provided between the insulating layer and the first metal layer, Wherein, the width of the third metal layer is greater than the width of the fourth metal layer.

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