Efficient multi-core processor fault injection method based on dynamic instruction stream

Abstract

The invention relates to an efficient multi-core processor fault injection method based on a dynamic instruction stream, and the method comprises the steps: executing injection based on fine-grained time divided by program dynamic instruction level execution, and carrying out fault injection through an instruction feature register sensitive to a single-particle irradiation effect. The influence of the space irradiation effect on different functional resources of the multi-core processor is simulated, the purpose of rapidly and efficiently evaluating the reliability design of the system is achieved, the dependence on a single particle test is reduced, the injection opportunity with controllable precision is achieved, and the fault injection accuracy and the system anti-SEU evaluation efficiency are improved.

Description

Technical Field

[0001] The invention belongs to the technical field of system single particle soft error reliability assessment and relates to an efficient multi-core processor fault injection method based on dynamic instruction stream. Background Art

[0002] In space applications, embedded processor systems are widely used in data information processing and control fields such as high-speed data transmission, signal communication, and navigation processing. However, due to the existence of single-particle radiation effects in space, single-particle soft errors affect the operating state of the processor. The fault forms are manifested in the following two categories: (1) The system operating state is abnormal or runs away or loops. This type of fault is called a symptomatic fault. When the fault is observed, the system has already crashed; (2) The system result is wrong. This type of result fault caused by state error is called a state error fault. At this time, the entire program state appears to be running normally, but the output result is wrong, which can cause a chain error indication of the system. The system faults caused by the above state errors are difficult to observe and recover in time due to their randomness and concealment, but they are also prone to occur. Therefore, by adopting the ground-based simulated fault injection method, fault injection is realized on the system single-particle flip-sensitive dynamic instruction flow, simulating the system working stability under the space radiation environment, and performing fault prediction analysis in advance, reducing the probability of system failures, and improving the reliability of the system on orbit.

[0003] Current technologies are mostly based on modifying instruction-level code to express fault injection behavior, or injecting based on hardware faults. The injection behavior often needs to be precompiled and is a rough injection. In the implementation process, it is impossible to simulate the single-particle upset effect for real-time, effective and accurate fault injection, resulting in shortcomings such as reduced fault injection test range and detection efficiency. Therefore, current technologies still have room for improvement in terms of design coverage, effectiveness and detection efficiency. Summary of the invention

[0004] The technical problem solved by the present invention is to overcome the deficiencies of the prior art and propose an efficient multi-core processor fault injection method based on dynamic instruction stream.

[0005] The solution of the present invention is:

[0006] An efficient multi-core processor fault injection method based on dynamic instruction flow, comprising:

[0007] Determine the core ID of a multi-core processor;

[0008] Extract the original instruction stream according to the determined processor core ID;

[0009] Format the extracted original instruction stream into a dynamic instruction stream;

[0010] Based on the dynamic instruction stream, the instructions susceptible to single-particle upset are screened, and the screened dynamic instruction stream file is generated;

[0011] The dynamic instructions are randomly distributed and intercepted using the filtered dynamic instruction stream file, and the GDB debugger is switched to the processor core ID to be injected;

[0012] Read compiled application source files with debugging function and provide breakpoint debugging information for GDB debugger;

[0013] Create fault injection breakpoints based on the intercepted dynamic instructions, and determine the stop position based on the number of times the injected instructions are executed;

[0014] Inject faults to the corresponding resources, restore multi-core synchronous execution, and continue executing the application.

[0015] Preferably, according to the determined processor core ID, the method for extracting the original instruction stream is as follows:

[0016] For each running instruction, use the breakpoint function of the GDB debugger to pause the application at the instruction entry for subsequent GDB debugging;

[0017] The single-step execution function of the GDB debugger allows the application assembly instructions of the processor core to be executed step by step according to single instructions;

[0018] At the instruction breakpoints of each execution, the PC register is checked through commands to obtain the current assembly instruction information and generate the original instruction stream for dynamic execution.

[0019] Preferably, the extracted original instruction stream is formatted into a dynamic instruction stream, and the formatting content is as follows:

[0020] <coreId,curIndex,machCode,func+offset,asmCode>

[0021] Among them, coreId refers to the processor core ID of the current injection, curIndex refers to the running sequence number of the current instruction, which represents its execution number in the total instruction execution process; machCode refers to the machine code of the current instruction; func+offset represents the breakpoint position provided for fault injection during the running process of the instruction; asmCode refers to the assembly instruction of the current instruction.

[0022] Preferably, the instructions susceptible to single event upsets include load and store instructions, integer and floating point operation instructions, logic operation instructions, and jump instructions.

[0023] Preferably, the dynamic instructions are randomly distributed and intercepted using the screened dynamic instruction stream file, and the GDB debugger is switched to the processor core ID to be injected through a thread command.

[0024] Preferably, a fault injection breakpoint is created according to the intercepted dynamic instruction, and the stop position is determined according to the number of executions of the injected instruction. The implementation method is as follows:

[0025] Obtain the register number and register flip bit to be injected according to random distribution;

[0026] Fault injection is performed through the set instruction of the GDB debugger. The injected fault is implemented by bit flipping. The fault mask is a mask value in which only the fault injection bit is 1 in the data bit width and the other bits are 0.

[0027] Preferably, bit flipping is implemented by performing a bitwise XOR operation on the target resource value and the fault mask. According to the binary addition property of bitwise XOR, when the value of the injected bit is XORed with 1, the current value of the register will be flipped to 0 or 1, while other values ​​remain at their original values, thereby implementing bitwise flip fault injection.

[0028] Preferably, after the fault is injected, the impact of the fault injection on the system operation is determined through the application execution result, and the reliability of the system design is evaluated.

[0029] The beneficial effects of the present invention compared with the prior art are:

[0030] (1) The present invention selects dynamic instruction streams sensitive to single-particle upsets based on the storage operation and instruction jump characteristics of multi-core processors, and implements a fault working mode of a program affected by a single-particle upset by means of a simulated injection method;

[0031] (2) The fault injection of the present invention adopts a breakpoint dynamic injection method that accompanies the execution time scale of program instructions, and a fine fault injection at the granularity of a single instruction, which has a controllable and precise injection timing, effectively avoiding the effect of injection timing selection on injection errors, and avoiding invalid injection to the greatest extent, effectively improving coverage, effectiveness and detection efficiency;

[0032] (3) The present invention implements fault injection into multi-core processors, which expands the applicable scope of fault injection compared to single-core processors;

[0033] (4) The present invention does not rely solely on single particle irradiation testing to evaluate the reliability of single particle protection of the system, thereby reducing dependence on single particle testing and improving the efficiency of the evaluation system's anti-SEU evaluation. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 It is a schematic diagram of the process of the present invention;

[0035] Figure 2 It is a schematic diagram of a dynamic instruction stream file;

[0036] Figure 3 Implement the principle of bit flipping for fault injection;

[0037] Figure 4 Design architecture for fault injection system software for multi-core processor simulation;

[0038] Figure 5 This is a schematic diagram of multi-core fault injection;

[0039] Figure 6 This is a diagram of GDB connecting to the device under test;

[0040] Figure 7 To switch to the corresponding multi-core processor core 2;

[0041] Figure 8 To load the symbol table file of core 2 of the multi-core processor;

[0042] Fig. 9 To determine the breakpoint location and enter the debug injection model;

[0043] Fig.10 A fault injection is performed to determine register w0. DETAILED DESCRIPTION

[0044] The present invention will be further described below in conjunction with the embodiments.

[0045] The present invention aims to analyze and extract the instruction flow during the dynamic execution of a multi-core application, generate fault injection vectors related to registers or memories for program instructions of different execution times and categories, and finally control the execution flow of the multi-core processor and perform fault injection based on the fault injection vectors through the GDB debugging interface. The following is the overall architecture design diagram of the method of the present invention, as shown in the figure. Figure 1 shown.

[0046] Phase 1: Dynamic instruction flow analysis and extraction

[0047] Embedded processors complete specified tasks by executing programs, and programs are composed of a series of ordered instructions. Instructions are commands that instruct the processor to perform certain operations. The collection of instructions is called an instruction set. During the execution of a single application, the total number of executed instructions is fixed. By extracting each executed instruction and its number of runs, fault injection can be refined to the instruction execution level.

[0048] Step 1: Determine the core ID of the multi-core processor and prepare to extract the instruction stream file of each core in the multi-core program.

[0049] Step 2: Based on the determined processor core ID, extract the original instruction stream through breakpoints, single-step execution, and viewing current register values ​​in the GDB debugger.

[0050] Step 2-1: For each running instruction, use the breakpoint function of the GDB debugger to pause the application at the instruction entry for subsequent GDB debugging.

[0051] Step 2-2: Use the GDB single-step execution function to execute the application assembly instructions of the processor core step by step according to single instructions.

[0052] Step 2-3: At the instruction breakpoints that are executed one by one, use the command to view the PC register to obtain the current assembly instruction information and generate the original instruction stream for dynamic execution.

[0053] Step 3: According to the original instruction stream extracted in step 2, format the original instructions into a dynamic instruction stream one by one in the following instruction information mode. The formatting content is as follows:

[0054] <coreId,curIndex,machCode,func+offset,asmCode>

[0055] Among them, coreId refers to the core number of the currently injected processor core, curIndex refers to the running sequence number of the current instruction, representing its execution order in the total instruction execution process; machCode refers to the machine code of the current instruction. When fault injection at the instruction code level is required, the machine code characteristics of the instruction can be analyzed based on this information to determine the resource location of the fault injection; func+offset represents the breakpoint location provided for fault injection during the running process of the instruction; asmCode refers to the assembly instruction of the current instruction. When fault injection at the assembly code level is required, the assembly code characteristics of the instruction can be analyzed based on this information to determine the resource location of the fault injection.

[0056] Step 4: According to the dynamic instruction stream formatted in step 3, according to the screening mechanism susceptible to single particle upset, load and store instructions (such as LDR, STR, MOV, FMOV), integer and floating point operation instructions (ADD, SUB, FADD, etc.), logical operation instructions (AND, ORR, EOR) and jump instructions (B, BL, RET, etc.) are used as screening objects of the dynamic instruction stream, and finally the following is generated: Figure 2 The dynamic instruction stream file shown.

[0057] For example, the generated dynamic instructions are as follows:

[0058] 0,41,0x54fffec1,bit_count+64,b.ne 0xdc0

[0059] Among them, 0 means the core ID of the multi-core processor is 0, b.ne 0xdc0 is to run the dynamic assembly instruction, 41 means the currently executed assembly instruction is the 41st execution, 0x54ffec1 is the assembled machine code, and bit_count+64 represents the breakpoint position to be provided for fault injection.

[0060] Phase 2: Fault injection into multi-core processor registers

[0061] When injecting into a multi-core processor, since each processor core is regarded as a "thread" by the GDB debugging tool, the thread switching instruction thread of the GDB debugging tool is used to switch to the corresponding processor core for debugging. The format used is the thread number of the thread processor core in GDB.

[0062] Based on the existing dynamic instruction stream file, multi-core fault injection is performed according to the fault vectors generated by different fault strategies. The basic steps are as follows:

[0063] Step 5: Build a fault injection environment, randomly distribute and intercept dynamic instructions using the filtered dynamic instruction stream obtained in stage 1, and switch GDB to the injected processor core through the thread command based on the injected core ID.

[0064] Step 6: Read the compiled application source file with debugging function and provide GDB breakpoint debugging information for subsequent breakpoint fault injection.

[0065] Step 7: Create a fault injection breakpoint based on the dynamic instructions intercepted in step 5, and determine the stop position based on the number of executions of the injected instructions.

[0066] Step 7-1: Obtain the register number and register flip bit to be injected according to random distribution.

[0067] Step 7-2: Perform fault injection through the set instruction of GDB. The injected fault is implemented by bit flipping. The fault mask is a mask value in which only the fault injection bit is 1 in the data bit width, and the rest of the bits are 0. Bit flipping is implemented by bitwise XORing the target resource value with the fault mask. According to the binary addition characteristic of bitwise XOR, when the value of the injected bit is XORed with 1, the current value of the register will be flipped to 0 or 1, while other values ​​remain the original values, thereby implementing bitwise flip fault injection. Figure 3 This is the schematic diagram of the fault injection bit flip implementation.

[0068] Step 8: Inject faults to the corresponding resources, restore multi-core synchronous execution, and continue executing the application.

[0069] Step 9: Determine the impact of fault injection on system operation through application execution results and evaluate the reliability of system design.

[0070] Figure 4 The software architecture of the fault injection simulation system for multi-core processors is designed. The executable file of the multi-core processor application (such as .elf file) is used as the input of the software. It is first processed by the fault injection preprocessing module to extract the assembly instructions of the application and pre-screen resource-sensitive instructions. Finally, the original assembly instruction stream is formatted into an instruction stream file that can be recognized by the fault injection strategy module as the basis of the fault injection system.

[0071] Secondly, the fault vector is generated according to the formatted processor instruction stream file, which includes the steps of determining the fault core, fault injection resource object, dividing the instruction subset according to the fault model, determining the fault injection time and injection location, generating the fault mask, and finally generating a fault vector group containing the fault injection information and passing it to the fault injection scheduling module.

[0072] Subsequently, the fault injection scheduling module is responsible for converting the previously generated fault vector group into specific fault injection execution steps, simulating the execution of the application on the device under test, that is, the multi-core processor, through the software QEMU, and connecting to the GDB SERVER of the device under test through GDB, so as to realize the execution of fault injection on the application on the multi-core processor, and after the injection is executed, the output results of the application and the injection parameters are generated as injection data and passed to the fault injection result analysis module.

[0073] Finally, the fault injection result analysis module compares and classifies the fault injection results based on the correct output file of the application, the output result file after fault injection, and the injection parameter file, and classifies and summarizes the analysis results according to the type of injected resources and the type of injected processor core, and outputs a reliability assessment report.

[0074] Example:

[0075] The specific method of using dynamic instruction stream to implement multi-core processor fault injection is as follows:

[0076] 1. Take the multi-core processor with the core ID 2 as an example. The injected resource is the 14th bit of register w0. The timing of injecting the breakpoint is bit_count+44. When the execution sequence is the 36th time, the specific fault injection is as follows: Figure 5 shown.

[0077] 2. First, use the target remote command to specify port 1237 to connect GDB to the device under test and establish a basic fault injection debugging environment, such as Figure 6 shown.

[0078] 3. Then, specify the injected processor core as core 2 through the thread instruction, and fix the injected core, such as Figure 7 shown.

[0079] 4. Use the symbol file instruction to load the application bitcount_apu1.elf file of the second core of the multi-core processor, and provide program information for GDB to implement breakpoints and debug injection functions, such as Figure 8 shown.

[0080] 5. Create a breakpoint at *bit_count+44 through instruction b, and skip the first 35 executions according to ignore to reach the 36th execution of the instruction to stop the operation of the multi-core processor and enter the debugging mode to modify the registers or memory resources, such as Fig. 9 shown.

[0081] 6. Finally, the original value of the w0 register is read through the print instruction, which is 4294966783. The 14th bit of w0 is injected through the set instruction. The modified value of the w0 register is read through the print instruction again, which is 4294950399. The schedule-multiple on is set through the set instruction to maintain the synchronous execution state of the multi-core processor. Then, the debug mode is exited through the c instruction, the running state of the multi-core processor is restored, and the fault injection is completed. Fig.10 Schematic diagram of performing fault injection to determine register w0.

[0082] This embodiment achieves controllable and accurate injection timing through fault injection based on program instruction level, thereby achieving the effect of doubling the accuracy of fault injection.

[0083] The present invention proposes an efficient multi-core processor fault injection method based on dynamic instruction stream. The method is based on fine-grained time execution injection of program dynamic instruction-level execution division. By injecting faults into instruction feature registers that are sensitive to single-particle radiation effects, the method simulates the influence of space radiation effects on different functional resources of multi-core processors, thereby achieving the purpose of fast and efficient evaluation of system reliability design, reducing dependence on single-particle tests, achieving precision-controllable injection timing, and improving the accuracy of fault injection and the efficiency of system anti-SEU evaluation.

[0084] The contents not described in detail in the specification of the present invention belong to the common knowledge of those skilled in the art.

Claims

1. An efficient multi-core processor fault injection method based on dynamic instruction flow, characterized in that: include: Determine the core ID of a multi-core processor; Extract the original instruction stream according to the determined processor core ID; Format the extracted original instruction stream into a dynamic instruction stream; Based on the dynamic instruction stream, the instructions susceptible to single-particle upset are screened, and the screened dynamic instruction stream file is generated; The dynamic instructions are randomly distributed and intercepted using the filtered dynamic instruction stream file, and the GDB debugger is switched to the processor core ID to be injected; Read compiled application source files with debugging function and provide breakpoint debugging information for GDB debugger; Create fault injection breakpoints based on the intercepted dynamic instructions, and determine the stop position based on the number of times the injected instructions are executed; Inject faults to the corresponding resources, restore multi-core synchronous execution, and continue executing the application.

2. According to the method of claim 1, the method is characterized in that: Based on the determined processor core ID, the method to extract the original instruction stream is as follows: For each running instruction, use the breakpoint function of the GDB debugger to pause the application at the instruction entry for subsequent GDB debugging; The single-step execution function of the GDB debugger allows the application assembly instructions of the processor core to be executed step by step according to single instructions; At the instruction breakpoints of each execution, the PC register is checked through commands to obtain the current assembly instruction information and generate the original instruction stream for dynamic execution.

3. The method for efficient multi-core processor fault injection based on dynamic instruction flow according to claim 1, characterized in that: The extracted original instruction stream is formatted into a dynamic instruction stream. The formatting content is as follows: <coreId,curIndex,machCode,func+offset,asmCode> Among them, coreId refers to the processor core ID of the current injection, curIndex refers to the running sequence number of the current instruction, which represents its execution number in the total instruction execution process; machCode refers to the machine code of the current instruction; func+offset represents the breakpoint position provided for fault injection during the running process of the instruction; asmCode refers to the assembly instruction of the current instruction.

4. The method for efficient multi-core processor fault injection based on dynamic instruction flow according to claim 1, characterized in that: Instructions that are susceptible to single-event upsets include load and store instructions, integer and floating-point operation instructions, logical operation instructions, and jump instructions.

5. The method for efficient multi-core processor fault injection based on dynamic instruction flow according to claim 1, characterized in that: The dynamic instructions are randomly distributed and intercepted using the filtered dynamic instruction stream file, and the GDB debugger is switched to the processor core ID to be injected through the thread command.

6. The method for efficient multi-core processor fault injection based on dynamic instruction flow according to claim 1, characterized in that: Create a fault injection breakpoint based on the intercepted dynamic instructions, and determine the stop position based on the number of times the injected instructions are executed. The implementation method is as follows: Obtain the register number and register flip bit to be injected according to random distribution; Fault injection is performed through the set instruction of the GDB debugger. The injected fault is implemented by bit flipping. The fault mask is a mask value in which only the fault injection bit is 1 in the data bit width and the other bits are 0.

7. The method for efficient multi-core processor fault injection based on dynamic instruction flow according to claim 6, characterized in that: Bit flipping is achieved by performing bitwise XOR on the target resource value and the fault mask. According to the binary addition characteristic of bitwise XOR, when the value of the injected bit is XORed with 1, the current value of the register will be flipped to 0 or 1, while other values ​​remain the original values, thus achieving bitwise flip fault injection.

8. The method for efficient multi-core processor fault injection based on dynamic instruction flow according to claim 1, characterized in that: After the fault is injected, the impact of the fault injection on the system operation is judged through the application execution results, and the reliability of the system design is evaluated.

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