Device model updating method and device, electronic equipment and storage medium

Abstract

The invention provides a device model updating method and device, electronic equipment and a storage medium, and the method comprises the steps: carrying out the simulation of a device required by a to-be-processed process node through electronic design automation simulation software, constructing a device simplified model based on the model simulation parameters of the device extracted in the simulation process, and carrying out the simulation of a device model. Generating a corresponding standard unit circuit according to the device simplification model; in electronic design automation simulation software, a simulation test circuit comprising a standard unit circuit is built by using a simulation circuit simulator, and netlist simulation is carried out on the simulation test circuit; calculating a difference value between the netlist simulation result and an actual circuit test result of the device, and adjusting model simulation parameters according to the difference value; and generating an updated device model of the device by using the adjusted model simulation parameters.

Description

Technical Field

[0001] The present disclosure relates to the field of device simulation, and in particular to a device model updating method, device, electronic device and storage medium. Background Art

[0002] As the size of advanced semiconductor nodes continues to decrease and the process becomes more and more complex, how to maximize the benefits that advanced semiconductor nodes bring to chips has received more and more attention, and the corresponding circuit design and process co-optimization (design technology co-optimization, DTCO) has become the focus of attention.

[0003] Conventional semiconductor chip design is to optimize circuit design given the process and process design kit (Puppet Development Kit, PDK). Traditional semiconductor PDK components include device libraries (including symbols and layouts), verification rule sets (such as design rule checking and circuit layout verification), technical data (such as layers, colors and process constraints), simulation models of original devices (such as transistors, capacitors, resistors and inductors) and design rule manuals. Since it takes a long time to develop a set of PDK components and perform device simulation and performance evaluation on the simulated devices based on the PDK components, it is necessary to improve the updating efficiency of device models. Summary of the invention

[0004] The present disclosure provides a device model updating method, apparatus, electronic device and storage medium, which are used to improve the updating efficiency of the device model.

[0005] The embodiment of the present disclosure provides a device model updating method, comprising: using electronic design automation simulation software to simulate a device required for a process node to be processed, constructing a device simplified model based on model simulation parameters of the device extracted during the simulation process, and generating a corresponding standard unit circuit according to the device simplified model; in the electronic design automation simulation software, using a simulation circuit simulator to build a simulation test circuit including a standard unit circuit, and performing a netlist simulation on the simulation test circuit; calculating the difference between the netlist simulation result and the actual circuit test result of the device, and adjusting the model simulation parameters according to the difference; and using the adjusted model simulation parameters to generate an updated device model of the device.

[0006] The embodiment of the present disclosure provides a device model updating apparatus, including: a device simulation module, used to use electronic design automation simulation software to simulate the device required for the process node to be processed, build a device simplified model based on the model simulation parameters of the device extracted during the simulation process, and generate a corresponding standard unit circuit according to the device simplified model; a circuit simulation module, used to use a simulation circuit simulator in the electronic design automation simulation software to build a simulation test circuit including a standard unit circuit, and perform netlist simulation on the simulation test circuit; a parameter adjustment module, used to calculate the difference between the netlist simulation result and the actual circuit test result of the device, and adjust the model simulation parameters according to the difference; a model update module, used to use the adjusted model simulation parameters to generate an updated device model of the device.

[0007] An embodiment of the present disclosure provides an electronic device, comprising: one or more processors; a memory on which one or more programs are stored, and when the one or more programs are executed by the one or more processors, the one or more processors implement any one of the device model updating methods in the embodiments of the present disclosure.

[0008] An embodiment of the present disclosure provides a storage medium, wherein the storage medium stores a computer program, and when the computer program is executed by a processor, any device model updating method in the embodiment of the present disclosure is implemented.

[0009] According to the device model updating method of the embodiment of the present disclosure, the device required for the process node to be processed can be simulated using electronic design automation simulation software, the model simulation parameters of the device can be extracted, the device simplified model can be constructed according to the extracted model simulation parameters, and the corresponding standard unit circuit can be generated according to the device simplified model; in the electronic design automation simulation software, a simulation test circuit containing a standard unit circuit can be constructed using a simulation circuit simulator, and the device can be simulated by a netlist, so that the model simulation parameters can be adjusted according to the difference between the calculated netlist simulation result and the actual test result, and the updated device model can be generated by using the adjusted model simulation parameters. According to this method, the device under the process node to be processed can be simulated, the device simplified model can be constructed, and the standard unit circuit can be designed, so that the device can be quickly constructed and the netlist simulation can be performed according to the device simplified model and the standard unit circuit in the electronic design automation simulation software, and the device model can be updated according to the difference between the simulation result and the actual test result, so as to achieve device model optimization or calibration, which is conducive to quickly evaluating the design effect of the device model, shortening the processing cycle of the performance evaluation of the device model, saving development costs and improving the efficiency of device model update.

[0010] With regard to the above embodiments and other aspects of the present disclosure and their implementations, more description is provided in the accompanying drawings, detailed description and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 A flow chart of a device model updating method according to an embodiment of the present disclosure is shown.

[0012] Figure 2 A layout diagram of a fin field effect transistor according to an embodiment of the present disclosure is shown.

[0013] Figure 3 A schematic diagram showing a process of extracting device parasitic parameters according to an embodiment of the present disclosure.

[0014] Figure 4 A schematic diagram of the simulation circuit structure in the hybrid mode of an embodiment of the present disclosure is shown.

[0015] Figure 5 A block diagram of a ring circuit oscillator according to an exemplary embodiment of the present disclosure is shown.

[0016] Figure 6 A detailed flow chart of a device model updating method according to an exemplary embodiment of the present disclosure is shown.

[0017] Figure 7 A schematic diagram of the structure of a business processing device according to an embodiment of the present disclosure is shown.

[0018] Figure 8 is a structural diagram showing an exemplary hardware architecture of a computing device capable of implementing the method and apparatus according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0019] In order to make the purpose, technical solution and advantages of the present disclosure more clear, the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. It should be noted that the embodiments and features in the embodiments of the present disclosure can be combined with each other arbitrarily without conflict.

[0020] The terms used in the present disclosure are only used to describe specific embodiments and are not intended to limit the present disclosure. The term "and / or" as used in the present disclosure includes any and all combinations of one or more related enumerated items. The singular forms "one" and "the" as used in the present disclosure are also intended to include plural forms, unless the context clearly indicates otherwise. The terms "including", "made of..." as used in the present disclosure specify the presence of the features, wholes, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or groups thereof.

[0021] Unless otherwise defined, all terms (including technical and scientific terms) used in this disclosure have the same meaning as commonly understood by those of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and this disclosure, and will not be interpreted as having an idealized or overly formal meaning unless explicitly defined in this disclosure.

[0022] In some scenarios, conventional semiconductor chip design is to optimize circuit design given the process and PDK. However, developing a PDK and evaluating the performance of new devices is a long-term task that may affect the product launch cycle. Therefore, an accurate and low-cost optimization and evaluation process is needed.

[0023] Based on this, the embodiments of the present disclosure provide a device model updating method, apparatus, electronic device and storage medium, which can be used to improve the updating efficiency of the device model.

[0024] First, refer to Figure 1 , an embodiment of the present disclosure provides a device model updating method, which can be applied to electronic devices and may include the following steps.

[0025] S110, using electronic design automation simulation software to simulate the device required for the process node to be processed, constructing a device simplified model based on the device model simulation parameters extracted during the simulation process, and generating a corresponding standard unit circuit according to the device simplified model.

[0026] In this step, the process node is a visual abstraction of the product's processing technology, and the process node may include process information and resource / material information; the electronic design automation simulation software may be a process simulation and device simulation tool (Technology Computer Aided Design, TCAD), which may also be called a semiconductor process simulation and device simulation tool.

[0027] Specifically, TCAD simulation software can provide simulation of multi-dimensional (one-dimensional, two-dimensional, three-dimensional) electrical, thermal and optical properties of devices, and can also perform process simulation of power metal-oxide-semiconductor field-effect transistors (MOSFETs) under deep submicron / nano processes, such as silicon MOSFETs, bipolar devices, silicon carbide (SiC) devices, III-V compounds and heterojunction devices.

[0028] The specific functions that TCAD simulation software can achieve include, for example, process simulation, structure editing, parasitic parameter extraction and performance simulation. Among them, process simulation can provide a process modeling / simulation environment. In this module, users can add ion implantation steps, diffusion species, annealing steps, etc., to partially complete and sequentially model the complete integrated circuit (IC) or photonics manufacturing process; structure editing can be used to edit two-dimensional and three-dimensional device structures, and doping profiles and discretization strategies can also be defined; parasitic parameter extraction can perform 2D and 3D resistance, capacitance and inductance extraction tools, which can be used to optimize the chip parasitic effects of multi-level interconnect structures in small circuit units; performance simulation can simulate the electrical, thermal and optical properties of semiconductor devices. It handles one-dimensional, two-dimensional and three-dimensional devices and can use streamlined models to perform circuit simulation in mixed mode.

[0029] In the disclosed embodiments, the device simulation performed by TCAD software can be regarded as a device-level simulation. The device-level TCAD simulation can solve the basic equations of semiconductor physics under specific boundary conditions to obtain the process of redistribution of physical quantities inside the device. Device simulation requires a physical model selected according to the different characteristic sizes of semiconductor devices. The drift diffusion model is currently widely used, mainly including: Poisson's equation, carrier continuity equation, current density equation, among which the recombination of carriers generally considers SRH recombination and Auger recombination. Use TCAD simulation software to study the influence of different process parameters on device performance.

[0030] In this step, the device compact model (Compact Model) is a compact model of the device required for the process node to be processed, which can also be called a compact model or an intensive model. The compact model is a predetermined model type of semiconductor device model. Semiconductor device modeling can generally be divided into two categories: physical model and compact model.

[0031] Among them, the physical model is based on the basic characteristics and transport mechanism of semiconductor devices, and establishes the current model of semiconductor devices and some physical effect models; the disadvantage of the physical model is that the model is usually complex and requires a lot of calculations; while the simplified model is usually based on the physical model, combined with engineering experience or mathematical methods, to reasonably simplify the model (such as removing occlusions, de-duplication, and simplifying small-size surfaces, etc.), for example, to obtain a relatively simple and explicit model. Since the simplified model is relatively simple in form and requires less calculations, it can usually be used for circuit simulation.

[0032] In this step, a standard cell circuit is a collection of circuit devices that provide the integrated circuit functionality and conform to the specific design rules of the chosen manufacturing technology.

[0033] S120, in the electronic design automation simulation software, using a simulation circuit simulator to build a simulation test circuit including a standard unit circuit, and perform a netlist simulation on the simulation test circuit.

[0034] In this step, the simulation program with integrated circuit emphasis (SPICE) is a circuit-level simulation. Its modeling is a simplified model. It can convert device mechanisms and characteristics into relatively simple analytical expressions. It is widely used in simulating analog circuits, mixed-signal circuits, precise digital circuits, establishing timing and power unit libraries of system-on-chip (SoC), and analyzing system-level signal integrity.

[0035] For example, in TCAD software, the generated TCAD model and SPICE model can be combined to simulate the netlist, realize simulation in mixed mode, and calculate PPAC based on the simulation results. The netlist circuit can be designed as different types of multi-stage ring oscillators, and simulation results such as oscillation frequency, power consumption and other parameters can be obtained. The model can be continuously optimized based on the simulation results to improve device performance.

[0036] In the related art, with the application of new materials and the increase in the complexity of device structures, the process of developing a complete model of a new device using SPICE simulation is complicated and time-consuming. The simulation mode provided in the embodiment of the present disclosure is a mixed mode simulation based on TCAD, which can use TCAD device models and SPICE models for simulation at the same time.

[0037] Since the device model constructed by TCAD (TCAD model for short) has the advantages of rich results and is conducive to the research of new devices, the two can be combined to package the TCAD model and directly participate in SPICE circuit analysis, which is conducive to reducing the errors caused by parameter extraction and device modeling in the process of device parameter extraction; the device can directly perform TCAD calculations under real bias conditions, and instantly display the electric field distribution, potential distribution, carrier distribution and temperature field distribution inside the device, which greatly improves the accuracy of device design and saves the device design cycle.

[0038] S130, calculating the difference between the netlist simulation result and the actual circuit test result of the device, and adjusting the model simulation parameters according to the difference.

[0039] S140, generating an updated device model of the device using the adjusted model simulation parameters.

[0040] According to the device model updating method of the embodiment of the present disclosure, the device required for the process node to be processed can be simulated using electronic design automation simulation software, the model simulation parameters of the device can be extracted, the device simplified model can be constructed according to the extracted model simulation parameters, and the corresponding standard unit circuit can be generated according to the device simplified model; in the electronic design automation simulation software, a simulation test circuit containing a standard unit circuit can be constructed using a simulation circuit simulator, and the device can be simulated by a netlist, so that the model simulation parameters can be adjusted according to the calculated difference between the netlist simulation result and the actual circuit test result, and the updated device model can be generated by using the adjusted model simulation parameters. According to this method, the device under the process node to be processed can be simulated, the device simplified model can be constructed, and the standard unit circuit can be designed, so that the device can be quickly constructed and the netlist simulation can be performed according to the device simplified model and the standard unit circuit in the electronic design automation simulation software, and the device model can be updated according to the difference between the simulation result and the actual circuit test result, so as to achieve device model optimization or calibration, which is conducive to shortening the device development cycle, thereby facilitating the rapid evaluation of the design effect of the device model and improving the optimization efficiency of the device model.

[0041] In some embodiments, the step of using electronic design automation simulation software to simulate the device required for the process node to be processed in the above step S110 may specifically include: S11, obtaining the device structure information and simulation parameters of the device required for the process node to be processed; S12, using electronic design automation simulation software to simulate the device based on the device structure information and simulation parameters.

[0042] In step S11, the devices required for the process node to be processed may include multiple types of transistors, and different types of transistors can be determined by parameters such as device type, number of channels (number of fins), number of single transistors in a forked-finger shape (number of fingers), and type of simulated threshold voltage (Vt).

[0043] The device class may include, for example, at least one of the following items: a planar transistor structure, a fin field-effect transistor (Fin Field-Effect Transistor, FinFET), and a gate-all-around FET (Gate-All-Around FET, GAA).

[0044] For Planar transistors, the drain current can be controlled by applying different voltages to the gate and source. The channel length (which can be simply approximated as the distance between the gate and the source) is about a few microns, and the voltage between the gate and the source can well control the drain current.

[0045] For FinFET, which can be called a tri-gate transistor, the FinFET structure consists of a thin (vertical) fin of silicon body on a substrate, and the gate surrounds the channel to provide good control of the channel on three sides.

[0046] For GAA transistors, multiple horizontal nanosheets or nanowires are stacked through GAA technology, and these channels are surrounded by gate materials on each side, thus achieving a higher current carrying capacity than FinFET. In addition, the four sides of the GAA transistor are surrounded by the gate. In the FinFET process, there are three sides. Since the gate can contact the four sides of the transistor, the structure of the transistor is improved. Therefore, the GAAFET structure can control the current more accurately than the FinFET process.

[0047] Figure 2 The layout of FinFETs with different structures is shown as an example. Figure 2 In the layout of each type of FinFET, "G" stands for gate, "S" stands for source, and "D" stands for drain; Fin stands for the number of channels; and NF stands for the number of gates.

[0048] Fin=2, NF=1, indicating a FinFET layout structure with 2 channels and 1 gate.

[0049] Fin=2, NF=2, indicating a FinFET layout structure with 2 channels and 2 gates;

[0050] Fin=3, NF=2, indicating a FinFET layout structure with 3 channels and 2 gates.

[0051] pass Figure 2It can be seen that in addition to transistors with single gate (single finger) and dual Fin structures, FinFETs with multiple gate fingers and multiple fin structures can also be involved. In actual application, the advanced process of the wafer factory can customize the number of gates and fins according to the needs. The embodiment of the present disclosure introduces a multi-gate finger structure here to simulate the simulation situation under different gate numbers. At the same time, in order to meet the selection of different simulation threshold voltages (Vt), the simulation threshold voltage Vt can be designed to be an ultra-low threshold voltage (Ultra Low Voltage Threshold, ULVT), a standard threshold voltage (Standard Voltage Threshold, SVT), a low threshold voltage (Low Voltage Threshold, LVT), an extra-low threshold voltage (extra-low threshold voltage, ELVT), a low leakage (Low leakage, LL) low threshold voltage LVTLL, a low leakage ultra-low threshold voltage ULVTLL, etc. It should be understood that the simulation threshold voltage Vt can also include more types, which can be set according to actual needs, and the embodiment of the present disclosure does not make specific limitations.

[0052] Exemplarily, the device required for the process node to be processed may be at least one of the following devices: Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET), Bipolar Transistor (BJT), Junction Field-Effect Transistor (JFET). It should be understood that the specific type of device required for the process node can be determined according to actual needs, and the embodiments of the present disclosure do not specifically limit it.

[0053] In step S11, the simulation parameters of the device may include, for example, at least one of the following items: device material, size, doping concentration, etc. These parameters may be provided by a process plant or obtained by dissecting the device, and are not specifically limited in the embodiments of the present disclosure.

[0054] Through the above steps S11-S12, TCAD simulation of the device can be implemented based on the device structure information and simulation parameters.

[0055] In some embodiments, in the above step S110, based on the model simulation parameters of the device extracted during the simulation process, a device simplified model is constructed, and the corresponding standard unit circuit is generated according to the device simplified model. Specifically, the steps may include: S21, in the process of simulating the device, extracting the electrical performance characteristics and material characteristics of the device; S22, generating a device simplified model based on the extracted electrical performance characteristics and material characteristics of the device; S23, simulating the back-end process of the device using electronic design automation simulation software; S24, generating a standard unit circuit based on the generated device simplified model and the simulated back-end process.

[0056] Exemplarily, the electrical performance characteristics in step S21 include, but are not limited to, characteristics such as voltage, current, resistance, and power; material characteristics may include, for example, characteristics such as strength, ductility, malleability, and hardness.

[0057] The design method based on standard cells may include: arranging pre-designed logic units called standard cells, such as AND gates, OR gates, multi-way switches, triggers, etc., according to certain specific rules, and combining them with pre-designed large units to form an integrated circuit (Application Specific Integrated Circuit, ASIC) for special applications.

[0058] In an embodiment, a simplified standard unit circuit design is provided, the electrical performance characteristics and material properties of the transistor are extracted and a simplified model is generated, and TCAD can be used to simulate the back-end process, such as changing the metal layer 1 (M1), the through hole 1 (V1), and the contact layer (CT), so as to design a set of simple standard unit circuits, which may include, for example, an inverter (INV), a NAND gate (NAND gate) circuit, a NOR gate (NOR gate) circuit or other circuits.

[0059] In step S23, the back-end process is a stage of the integrated circuit manufacturing process. The back-end process mainly refers to the formation of interconnects that can transmit electrical signals to various devices on the chip, mainly including the deposition of dielectrics between interconnects, the formation of metal lines, the formation of lead pads, etc. In short, the back-end process can be used to form metal wiring.

[0060] Through the above steps S21-S24, the electrical performance characteristics and material properties of the device are extracted based on the TCAD simulation of the device for generating a simplified model. TCAD can be used to simulate the back-end process, and a standard unit circuit is obtained according to the simplified model and the back-end process design.

[0061] In some embodiments, step S120 may specifically include the following steps S31, extracting parasitic parameters of the corresponding standard unit circuit generated by the device simplified model through electronic design automation simulation software; S32, using a simulation circuit simulator to build a simulation test circuit based on the extracted parasitic parameters and the standard unit circuit; S33, performing circuit simulation on the built simulation test circuit based on the pre-acquired circuit netlist.

[0062] Exemplarily, the reasons for extracting parasitic parameters in step S31 include: the resistance of the wire itself, the mutual inductance between adjacent wires, and the coupling capacitance, which will generate signal noise, crosstalk and reflection inside the chip, resulting in signal voltage fluctuations and changes, so it is necessary to extract parasitic parameters and perform another analysis and verification. It can include at least one of parasitic resistance (R), parasitic capacitance (C), and parasitic inductance (L). It can be determined specifically according to the actual situation of the circuit.

[0063] Taking the RC parameters as an example, RC stands for the abbreviation of resistor and capacitor. The RC circuit parameters mainly refer to the values ​​of resistor and capacitor. In electronic circuits, the RC circuit is one of the most important basic circuits, and its parameters can be used to analyze and design many circuits.

[0064] In this embodiment, the simulation of netlist is combined with the generated TCAD model and the SPICE model, and the simulation under the hybrid mode is realized. The simulation of the hybrid mode is carried out by adopting TCAD software, compared with the shortcomings that the SPICE device model in the previous method can not fully describe the structure of the designed device and the large error of the calculation result, the TCAD device model can be directly inserted into the SPICE circuit, so that the device can be processed under the more realistic conditions. TCAD calculation, it is conducive to reducing the error brought by the parameter extraction process, and the situation (such as electric field distribution, potential distribution, carrier distribution and temperature field distribution) of the device is displayed in real time. At the same time, compared with the current hybrid simulation, the present disclosure designs the device as a basic unit circuit and extracts RC parameters, and the extraction results are attached to the SPICE circuit analysis, and can be used for estimating circuit delay, realizing signal integrity and power integrity analysis by parasitic parameter extraction, so as to verify the various performance indicators of the whole circuit design. The RC parameters of the basic unit circuit are extracted by TCAD, and preparations can be made for subsequent SPICE circuit simulation, and the extraction results are attached to the subsequent SPICE circuit analysis, so that the simulation is more convincing.

[0065] Figure 3 Schematic diagram of the process of extracting device parasitic parameters provided by the embodiment of the present disclosure. Figure 3As shown, the arrow can represent the RC parameter extraction, the left side of the arrow represents the schematic diagram of the standard unit circuit, and the right side of the arrow represents the extracted parasitic parameters. Figure 3 It can be seen that the extracted parasitic parameters are RC parameters. For the generated devices and the standard unit circuits composed of their back-end processes, their RC parameters can be extracted through TCAD to prepare for subsequent SPICE circuit simulation. In some embodiments, the extracted parasitic data can be used to create a parasitic database for subsequent research on the impact of design rule changes.

[0066] In step S32, SPICE can be used to build a simulation test circuit based on the extracted parasitic parameters and standard unit circuits, so that in the TCAD software, the generated TCAD model and the SPICE model can be combined to simulate the netlist to achieve simulation in a mixed mode.

[0067] Figure 4 Schematic diagram of the simulation circuit structure in the hybrid mode of the embodiment of the present disclosure. Figure 4 In the simulation, the circuit model is a model built based on SPICE, referred to as SPICE model, which can be extracted from the PDK file provided by the process factory; in the simulation circuit under the hybrid model, the device-level TCAD simulation model can be inserted into the circuit simulation to better simulate the impact of the circuit on the device.

[0068] In step S33, in circuit design, a netlist is used to describe the connection relationship between circuit elements, referred to as a circuit netlist. The netlist circuit can be designed as different types of multi-stage ring oscillators (RO).

[0069] In the disclosed embodiments, the circuits of the logic devices involved in the design of the digital circuits can be simulated. For example, TCAD simulation can be performed on all transistors in the netlist and connected using a SPICE model so that the devices can be subjected to TCAD calculations under more realistic conditions, which helps to reduce errors caused by the parameter extraction process.

[0070] Figure 5 A block diagram of a ring circuit oscillator provided in an embodiment of the present disclosure.

[0071] like Figure 5As shown, a type of ring circuit oscillator includes an input pin, an oscillator link, and an output pin, wherein the link is composed of multiple levels (odd number, such as 101 levels) of NAND gates, and each level of gate circuits includes equivalent interconnection resistance and capacitance, and its SPICE model is extracted from the PDK provided by the process factory. In order to cover as many situations as possible, the NAND gate can be changed to INV, NOR gate or others, and considering the asymmetry of NAND gates and NOR gates in actual processes, different scenarios can be covered by swapping input ports, so a variety of ring oscillator links can be designed.

[0072] It should be noted that compared with the related art of using TCAD to generate the structure of the metal interconnect layer capacitor, extracting the capacitance value required by the SPICE model, and simulating the back-end metal interconnect layer capacitor, the embodiment of the present disclosure uses TCAD to perform device-level simulation. The ring oscillator circuit constructed by SPICE is not an optimization of the capacitance model, but an optimization of the device simulation and process library.

[0073] In some embodiments, the type of simulation test circuit may also include at least one of the following items: analog circuit, memory circuit. In this embodiment, it is not limited to the process library simulation of digital logic circuits, and the process library of analog circuits, SRAM and other memory devices may also be taken into consideration, which improves the applicability of the embodiment of the present disclosure.

[0074] In some embodiments, the actual circuit test result is a circuit hardware test based on the actual chip after the device streamlined model is taped out to obtain the actual chip of the corresponding device; in this embodiment, step S130 may specifically include: obtaining a first indicator value and a second indicator value, the first indicator value is an indicator value of a predetermined analysis indicator obtained by performing data analysis on the netlist simulation result, and the second indicator value is an indicator value of a predetermined analysis indicator obtained by performing data analysis on the circuit hardware test performed on the actual chip; based on the difference between the first indicator value and the second indicator value, adjusting the model simulation parameters to obtain the adjusted model simulation parameters.

[0075] In this embodiment, by comparing the TCAD simulation results and the test results of the physical key test points, data analysis can be performed, and the data analysis result is: when the error between the model simulation result and the actual circuit test result is greater than a threshold, the device model is improved by adjusting the model parameters until the error between the model simulation result and the actual test result is less than a set value. At this time, it is considered that the designed standard unit circuit model and ring oscillator model have achieved the expected goals under the actual advanced process. When the expected goals are achieved, it is considered that the designed standard unit circuit model and ring oscillator model have achieved the expected goals under the actual advanced process. An updated device model is obtained according to the adjusted model parameters, that is, an optimized device model, and can be applied to actual production.

[0076] In some embodiments, after the simulation test circuit including the standard unit circuit is constructed using the simulation circuit simulator in step S120, the method further includes: obtaining process parameters in the construction process of the simulation test circuit, generating a corresponding process library according to the process parameters, the process library being used to record the process parameters; calculating an evaluation index value of the simulation test circuit for at least one preset evaluation index; if the evaluation index value does not meet the predetermined evaluation index condition, adjusting the process parameters corresponding to the process library according to the evaluation index value, and generating an updated process library according to the adjusted process parameters.

[0077] As an example, the circuit can be evaluated by four dimensions of performance, power, area, and cost (referred to as PPAC) to see whether it meets the expected indicators. The PPAC evaluation scheme includes but is not limited to the ring oscillator (RO) model simulation scheme described in the above embodiment.

[0078] In the disclosed embodiments, by analyzing the difference between the model simulation results and the actual circuit test results, on the one hand, the device simulation parameters can be corrected, the process library model can be optimized, and the process library can be customized; on the other hand, the simulation results can be used to guide the process. If a certain process parameter is changed, it will have a positive effect on the PPAC of the oscillator. This can achieve the purpose of optimizing the process flow and realize the improvement of process parameters based on TCAD device-level simulation and the optimization of PDK.

[0079] According to the device model updating method of the embodiment of the present disclosure, compared with the traditional PDK development process, the device modeling, standard unit circuit design and parasitic parameter extraction can be carried out through TCAD software, and the required compact model can be generated relatively quickly to generate a streamlined version of PDK, which greatly shortens the R&D cycle and improves the model update efficiency.

[0080] Figure 6 FIG. 1 is a detailed flow chart showing a device model updating method according to an exemplary embodiment of the present disclosure. Figure 6 As shown, the method includes the following steps.

[0081] S601, determine the device structure and process parameters of the process node required for the design.

[0082] Exemplarily, the transistor structure required for the process node to be optimized is determined, including device type, number of Fins, number of fingers, Vt type and other information; the process parameters of the device may include, for example, device material, size, doping concentration, etc. These parameters may be provided by the process factory or obtained by dissecting the device.

[0083] S602, using electronic design automation simulation software (TCAD) to simulate the device model, extract electrical performance parameters to generate a compact model, and design a standard unit circuit based on the model.

[0084] Exemplarily, the device is simulated using TCAD simulation software, which may include three-dimensional modeling of the device process simulation; meshing it using a meshing tool, and refining the mesh at the channel, source / drain, and interface; and finally, characterizing the device electrical performance based on the mesh and the selected model.

[0085] In this step, a simplified model can be generated based on the results of the transistor electrical performance characterization, and standard unit circuits can be designed: such as INV, NOR gate, NAND gate, etc., and a simplified customized PDK can be generated from this.

[0086] S603, extracting parasitic parameters of the generated standard cells, the parasitic parameters are used for circuit simulation performed by a simulation circuit simulator (SPICE).

[0087] S604, in the TCAD software, using a hybrid mode to combine the generated TCAD model and the SPICE model to perform netlist simulation.

[0088] In this step, the netlist is used to indicate the netlist circuit. As an example, the netlist circuit can be designed as different types of multi-stage ring oscillators, and simulation results such as oscillation frequency, power consumption and other parameters can be obtained. The model is continuously optimized based on the simulation results to improve device performance.

[0089] S605, based on the simulation results, analysis indicators in four dimensions of performance, power, area and cost are calculated to optimize the performance of the model.

[0090] S606, tape out based on the device model to obtain an actual chip, and perform hardware testing to obtain hardware test results.

[0091] For example, the file in the GDSII format generated by the design may be handed over to a process factory for tape-out processing; GDSII is a standard format for electronic design automation.

[0092] In this step, tape-out can be understood as the step of manufacturing chips through a series of process steps like an assembly line. The netlist of the above design is physically implemented on the chip layout, and then simulated. If the simulation fails, the design is modified again.

[0093] Among them, post-simulation is the abbreviation of post-simulation, which is also called timing simulation or gate-level simulation. When the chip is placed and routed at the back end, the netlist with timing information is simulated, which is called post-simulation.

[0094] S607, iteratively optimize the device model based on the hardware test results.

[0095] For example, hardware tests can be performed on the chip after it is taped out. For example, for a ring oscillator circuit, one ring oscillator can be powered on by an external power supply, the power supply can be set to the design value of the corresponding ring oscillator, the output current and frequency can be read through the output port, and other ring oscillators can be replaced to perform the same operation.

[0096] Through the above steps S601-S607, the device under the process node to be processed can be simulated, the device simplified model can be constructed and the standard unit circuit can be designed. Therefore, in the electronic design automation simulation software, the simulation test circuit can be quickly built and the netlist simulation can be performed according to the device simplified model and the standard unit circuit, and the device model can be updated according to the difference between the simulation result and the actual circuit test result to achieve device model optimization or calibration, which is conducive to quickly evaluating the design effect of the device model, shortening the processing cycle of the performance evaluation of the device model, saving development costs and improving the efficiency of device model update.

[0097] In some embodiments of the present disclosure, TCAD simulation can be performed on a variety of transistors in combination with the transistor characteristics of the required process node to generate a simplified model, and the generated simplified model can be designed as a standard unit circuit, and a simple process library customization can be performed. Finally, the design of the device and the basic unit circuit can be optimized through the actual tape-out results and simulation results, thereby achieving the purpose of customized process library and optimized design.

[0098] In the disclosed embodiment, the actual situation of the device in the circuit can be accurately simulated by simulating the test circuit netlist, and the circuit PPA characteristics of the new device can be evaluated through the simulation results to determine whether the device has gain for the circuit and the size of the gain, thereby correcting the device parameters. After the optimization iteration, the test circuit is physically implemented on the chip layout and the circuit netlist is post-simulated; the chip that passes the post-simulation is taped out and tested. By comparing the simulation results with the actual tape-out test results, the causes of the errors are summarized, and the device model is continuously optimized and calibrated. This is a low-cost, high-precision multiple evaluation and model iteration optimization method.

[0099] In a second aspect, the present disclosure provides a device model updating apparatus. Figure 7 , the device model updating apparatus 700 provided by the embodiment of the present disclosure includes:

[0100] The device simulation module 710 is used to simulate the device required for the process node to be processed using electronic design automation simulation software, build a device simplified model based on the device model simulation parameters extracted during the simulation process, and generate a corresponding standard unit circuit according to the device simplified model;

[0101] The circuit simulation module 720 is used to use a simulation circuit simulator to build a simulation test circuit including a standard unit circuit in the electronic design automation simulation software, and perform a netlist simulation on the device;

[0102] The parameter adjustment module 730 is used to calculate the difference between the netlist simulation result and the actual circuit test result of the device, and adjust the model simulation parameters according to the difference;

[0103] The model updating module 740 is used to generate an updated device model of the device using the adjusted model simulation parameters.

[0104] In some embodiments, when the device simulation module 710 is used to simulate the device required for the process node to be processed using electronic design automation simulation software, it is specifically used to: obtain the device structure information and simulation parameters of the device required for the process node to be processed; and use the electronic design automation simulation software to simulate the device based on the device structure information and simulation parameters.

[0105] In some embodiments, when the device simulation module 710 is used to construct a device simplified model based on the model simulation parameters of the device extracted during the simulation process, and to generate a corresponding standard unit circuit based on the device simplified model, it is specifically used to: extract the electrical performance characteristics and material characteristics of the device during the simulation of the device; generate a device simplified model based on the extracted electrical performance characteristics and material characteristics of the device; simulate the back-end process of the device using electronic design automation simulation software; and generate a standard unit circuit based on the generated device simplified model and the simulated back-end process.

[0106] In some embodiments, the circuit simulation module 720 is specifically used to: extract parasitic parameters of the corresponding standard unit circuit generated by the device simplified model through electronic design automation simulation software; use a simulation circuit simulator to build a simulation test circuit based on the extracted parasitic parameters and the standard unit circuit; and perform circuit simulation on the built simulation test circuit based on a pre-acquired circuit netlist.

[0107] In some embodiments, the actual circuit test result is a circuit hardware test based on the actual chip after the device streamlined model is taped out to obtain the actual chip of the corresponding device; the parameter adjustment module 730 is specifically used to include: obtaining a first indicator value and a second indicator value, the first indicator value is an indicator value of a predetermined analysis indicator obtained by performing data analysis on the netlist simulation result, and the second indicator value is an indicator value of a predetermined analysis indicator obtained by performing data analysis on the circuit hardware test performed on the actual chip; based on the difference between the first indicator value and the second indicator value, adjusting the model simulation parameters to obtain the adjusted model simulation parameters.

[0108] In some embodiments, the device model updating apparatus further includes: a process library generation module, which is used to obtain process parameters in the construction process of a simulation test circuit after a simulation test circuit including a standard unit circuit is built using a simulation circuit simulator, and generate a corresponding process library based on the process parameters, wherein the process library is used to record the process parameters; an evaluation calculation module, which is used to calculate an evaluation index value of the simulation test circuit for at least one preset evaluation index; and a process parameter adjustment module, which is used to adjust the process parameters corresponding to the process library based on the evaluation index values ​​when the evaluation index values ​​do not meet predetermined evaluation index conditions, and generate an updated process library based on the adjusted process parameters.

[0109] In some embodiments, the device includes at least one of the following items: a metal oxide semiconductor field effect transistor, a bipolar transistor, and a junction field effect transistor; the type of the simulation test circuit includes at least one of the following items: a digital circuit, an analog circuit, and a memory circuit.

[0110] According to the device model updating device of the embodiment of the present disclosure, the electronic design automation simulation software can be used to simulate the device required for the process node to be processed, the model simulation parameters of the device can be extracted, the device simplified model can be constructed according to the extracted model simulation parameters, and the corresponding standard unit circuit can be generated according to the device simplified model; in the electronic design automation simulation software, a simulation test circuit containing a standard unit circuit can be constructed using a simulation circuit simulator, and the device can be simulated by a netlist, so that the model simulation parameters can be adjusted according to the difference between the calculated netlist simulation result and the actual circuit test result, and the updated device model can be generated by using the adjusted model simulation parameters. According to the method, the device under the process node to be processed can be simulated, the device simplified model can be constructed, and the standard unit circuit can be designed, so that the simulation test circuit can be quickly constructed and the netlist simulation can be performed according to the device simplified model and the standard unit circuit in the electronic design automation simulation software, and the device model can be updated according to the difference between the simulation result and the actual circuit test result, so as to achieve device model optimization or calibration, which is conducive to quickly evaluating the design effect of the device model, shortening the processing cycle of the performance evaluation of the device model, saving development costs and improving the efficiency of device model update.

[0111] According to the embodiment scheme of the present disclosure, a simplified standard cell library can be established relatively quickly by simulating devices at different process nodes and designing standard cell circuits. The process library model can also be simulated, and the model simulation results of the test circuit are compared and analyzed and verified with the actual tape-out test results, thereby achieving continuous iteration of the model and achieving model optimization or calibration.

[0112] It should be clear that the present disclosure is not limited to the specific configurations and processes described in the above embodiments and shown in the figures. For the convenience and brevity of description, a detailed description of the known methods is omitted here, and the specific working processes of the systems, modules and units described above can refer to the corresponding processes in the aforementioned method embodiments, which will not be repeated here.

[0113] In a third aspect, an embodiment of the present disclosure also provides an electronic device.

[0114] Figure 8 is a structural diagram showing an exemplary hardware architecture of a computing device capable of implementing the method and apparatus according to an embodiment of the present disclosure.

[0115] Reference Figure 8 The electronic device includes: at least one processor 801; at least one memory 802, and one or more I / O interfaces 803, connected between the processor 801 and the memory 802; wherein the memory 802 stores one or more computer programs that can be executed by at least one processor 801, and the one or more computer programs are executed by at least one processor 801 so that the at least one processor 801 can execute the above-mentioned device model updating method.

[0116] Among them, the processor is a device with data processing capabilities, including but not limited to the central processing unit (CPU); the memory is a device with data storage capabilities, including but not limited to random access memory (RAM, more specifically SDRAM, DDR, etc.), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory (FLASH); the I / O interface (read-write interface) is connected between the processor and the memory, and can realize information exchange between the memory and the processor, including but not limited to the data bus (Bus), etc.

[0117] The present disclosure also provides a computer-readable storage medium on which a computer program is stored, wherein the computer program implements the above-mentioned data method when executed by a processor / processing core. The computer-readable storage medium may be a volatile or non-volatile computer-readable storage medium.

[0118] Those skilled in the art will appreciate that all or some of the steps, systems, and functional modules / units in the apparatus disclosed above may be implemented as software, firmware, hardware, or a suitable combination thereof.

[0119] In hardware implementations, the division between functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component may have multiple functions, or one function or step may be performed by several physical components in cooperation.

[0120] Some physical components or all physical components may be implemented as software executed by a processor, such as a central processing unit (CPU), a digital signal processor or a microprocessor, or implemented as hardware, or implemented as an integrated circuit, such as an application-specific integrated circuit. Such software may be distributed on a computer-readable medium, which may include a computer storage medium (or non-temporary medium) and a communication medium (or temporary medium). As known to those of ordinary skill in the art, the term computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules or other data). Computer storage media include, but are not limited to, random access memory (RAM, more specifically SDRAM, DDR, etc.), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory (FLASH) or other disk storage; read-only compact disk (CD-ROM), digital versatile disk (DVD) or other optical disk storage; magnetic cassettes, magnetic tapes, disk storage or other magnetic storage; any other medium that can be used to store desired information and can be accessed by a computer. Furthermore, it is well known to those skilled in the art that communication media typically embodies computer readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.

[0121] The present disclosure has disclosed example embodiments, and although specific terms are employed, they are used and should be interpreted only in a general illustrative sense and not for limiting purposes. In some instances, it will be apparent to those skilled in the art that, unless otherwise expressly stated, features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments. Therefore, those skilled in the art will appreciate that various changes in form and detail may be made without departing from the scope of the present disclosure as set forth in the appended claims.

Claims

1. A device model updating method, characterized in that: The method comprises: Using electronic design automation simulation software to simulate the device required for the process node to be processed, constructing a device simplified model based on the model simulation parameters of the device extracted during the simulation process, and generating a corresponding standard unit circuit according to the device simplified model; In the electronic design automation simulation software, a simulation circuit simulator is used to build a simulation test circuit including the standard unit circuit, and a netlist simulation is performed on the simulation test circuit; Calculating the difference between the netlist simulation result and the actual circuit test result of the device, and adjusting the model simulation parameters according to the difference; An updated device model of the device is generated using the adjusted model simulation parameters.

2. The method according to claim 1, characterized in that: The use of electronic design automation simulation software to simulate the device required for the process node to be processed includes: Obtaining device structure information and simulation parameters of the device required for the process node to be processed; The electronic design automation simulation software is used to simulate the device based on the device structure information and the simulation parameters.

3. The method according to claim 1, wherein the device simplified model is constructed based on the model simulation parameters of the device extracted during the simulation process, and a corresponding standard unit circuit is generated according to the device simplified model, comprising: In the process of simulating the device, extracting electrical performance characteristics and material characteristics of the device; Generating a simplified model of the device according to the extracted electrical performance characteristics and material characteristics of the device; Using the electronic design automation simulation software to simulate the back-end process of the device; A standard unit circuit is generated according to the generated device simplified model and the simulated back-end process.

4. The method according to claim 1, characterized in that: In the electronic design automation simulation software, a simulation test circuit including the standard unit circuit is constructed using a simulation circuit simulator, and a netlist simulation is performed on the device, including: Extracting parasitic parameters of the corresponding standard unit circuit generated by the device simplified model through the electronic design automation simulation software; Using the simulation circuit simulator, building a simulation test circuit according to the extracted parasitic parameters and the standard unit circuit; Circuit simulation is performed on the constructed simulation test circuit according to the pre-acquired circuit netlist.

5. The method according to claim 1, characterized in that The actual circuit test result is a circuit hardware test performed on the actual chip after the device simplified model is taped out to obtain the actual chip of the corresponding device; The calculating a difference between a netlist simulation result and an actual circuit test result of the device, and adjusting the model simulation parameters according to the difference, comprises: Obtaining a first index value and a second index value, wherein the first index value is an index value of a predetermined analysis index obtained by performing data analysis on the netlist simulation result, and the second index value is an index value of a predetermined analysis index obtained by performing data analysis on a circuit hardware test performed on the actual chip; Based on the difference between the first index value and the second index value, the model simulation parameter is adjusted to obtain the adjusted model simulation parameter.

6. The method according to claim 3, after the simulation test circuit including the standard unit circuit is constructed by using the simulation circuit simulator, the method further comprises: Acquire process parameters in the construction process of the simulation test circuit, and generate a corresponding process library according to the process parameters, wherein the process library is used to record the process parameters; Calculating an evaluation index value of the simulation test circuit for at least one preset evaluation index; In the case that the evaluation index value does not satisfy a predetermined evaluation index condition, a process parameter corresponding to the process library is adjusted according to the evaluation index value, and an updated process library is generated according to the adjusted process parameter.

7. The method according to any one of claims 1 to 6, characterized in that The device includes at least one of the following: a metal oxide semiconductor field effect transistor, a bipolar transistor, a junction field effect transistor; The type of the simulation test circuit includes at least one of the following items: a digital circuit, an analog circuit, and a memory circuit.

8. A device updating apparatus, characterized in that: The device comprises: A device simulation module, used to simulate the device required for the process node to be processed using electronic design automation simulation software, build a device simplified model based on the model simulation parameters of the device extracted during the simulation process, and generate a corresponding standard unit circuit according to the device simplified model; A circuit simulation module, used to build a simulation test circuit including the standard unit circuit using a simulation circuit simulator in the electronic design automation simulation software, and perform netlist simulation on the simulation test circuit; A parameter adjustment module, used for calculating the difference between the netlist simulation result and the actual circuit test result of the device, and adjusting the model simulation parameters according to the difference; A model updating module is used to generate an updated device model of the device using the adjusted model simulation parameters.

9. An electronic device, comprising: one or more processors; A memory having one or more programs stored thereon, wherein when the one or more programs are executed by the one or more processors, the one or more processors implement the method according to any one of claims 1 to 7.

10. A storage medium, characterized in that: The storage medium stores a computer program, and when the computer program is executed by a processor, the method according to any one of claims 1 to 7 is implemented.

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