High-reliability VLD terminal

Abstract

The high-reliability VLD terminal is easy to implement, wide in voltage application range and capable of reducing the surface electric field, the reliability problem that the peak value of the surface electric field is too high due to wave-shaped impurity distribution of the VLD terminal is solved through one-time ion implantation and the floating composite field plate, the voltage withstanding performance of the VLD terminal is improved, and the high-reliability VLD terminal has good practical value.

Description

Technical Field

[0001] The invention belongs to the technical field of power semiconductor devices and relates to a high-reliability VLD terminal. Background Art

[0002] Power semiconductor devices are mainly composed of two parts: the cell region and the terminal region. The design of the terminal structure is crucial to the breakdown voltage characteristics of power devices. Field plate + field limiting ring is the most commonly used terminal structure, but with the increase of device withstand voltage, when the number of field limiting rings increases to a certain extent, the effect of improving the breakdown voltage is no longer obvious, and a large amount of chip area is wasted, increasing production costs. The Variable Lateral Doping (VLD) terminal structure proposed by the literature Stengl R, Gosele U. Variation of lateral doping-A new concept to avoid high voltage breakdown of planar junctions, Proceedings of International Electron Devices Meeting, 1985, etc., greatly reduces the terminal length and chip area, improves the withstand voltage efficiency, reduces the production cost, and is gradually widely used in devices such as power MOSFET. Variation of Lateral Doping (VLD) terminal is one of the most common terminal design methods in medium and high voltage power devices. By injecting a region with a gradient impurity concentration at the edge of the device, it can effectively expand the depletion region, alleviate the electric field concentration, and make the device show better blocking performance. VLD termination is a method of forming a lateral variable doping structure by setting appropriate mask window shapes and window parameter values, and performing ion implantation near the heavily doped main junction. The closer to the main junction, the greater the amount of implantation, and the farther away, the smaller the amount of implantation. The implanted impurities are connected through lateral diffusion of impurities. Compared with field limiting ring and field plate terminations, VLD has a smaller termination area; compared with JTE terminations, VLD has better blocking performance and is less sensitive to terminal impurity implantation dose deviation. The industry and academia have been committed to improving VLD terminations to achieve better blocking performance and reliability.

[0003] Although the traditional VLD terminal is simple in design, in the process of ion implantation to form the VLD terminal, the impurity concentration gradient distribution is achieved by controlling the size of the mask shielding area and the window area. If the mask layout, high temperature annealing process, implantation dose, etc. are not properly set, the impurity concentration distribution formed after high temperature annealing will be wavy, deviating from the smooth gradient impurity distribution, such as Figure 1This wavy distribution will produce an excessively high electric field peak at the low impurity concentration position J, reducing the performance of the VLD terminal and affecting the voltage withstand capability and reliability of the device. Summary of the invention

[0004] The present invention provides a high-reliability VLD terminal. The method is easy to implement and has a wide voltage application range. The high surface electric field peak value caused by the wavy impurity distribution of the VLD terminal is improved by a single ion implantation plus a floating composite field plate, thereby improving the reliability problem of the excessively high surface electric field peak value of the VLD terminal caused by the uneven impurity distribution and improving the withstand voltage performance of the VLD terminal, and having good practical value.

[0005] like Figure 2 The figure shows the overall structure of the power device layout. Figure 3 is a lateral variable doping terminal. Figure 2 The area indicated by the black dotted line ABCD has a structure like Figure 3 As shown, it includes: a drain electrode metal 1, a heavily doped first conductivity type semiconductor substrate 2 located on the drain electrode metal, a lightly doped first conductivity type semiconductor drift region 3 located on the heavily doped first conductivity type semiconductor substrate 2, a second conductivity type semiconductor main junction 4, a second conductivity type semiconductor variable doping region 5 and a heavily doped second conductivity type semiconductor cut-off ring 6 located on the upper surface of the first conductivity type semiconductor drift region 3, a source electrode metal 7 located on the second conductivity type semiconductor main junction 4, an oxide layer 8 located on the second conductivity type semiconductor variable doping region 5 and the second conductivity type semiconductor cut-off ring 6, a polysilicon field plate 9 located on the oxide layer 8, an Al metal field plate 10 located on the polysilicon field plate 9, and the Al metal field plate 10 and the polysilicon field plate 9 constitute a composite field plate. Definition: The direction from the oxide layer 8 vertically pointing to the lightly doped first conductivity type semiconductor drift region 3 is the y-axis direction, and the parallel direction from the oxide layer 8 to the junction of the second conductivity type semiconductor variable doping region 5 is the x-axis direction;

[0006] To achieve the above-mentioned purpose of the invention, the technical solution of the present invention is as follows:

[0007] A high-reliability VLD terminal improves the reliability problem of excessively high surface electric field peaks caused by the wavy impurity distribution of the VLD terminal through a single ion implantation plus a floating composite field plate, and improves the withstand voltage performance of the VLD terminal. Figure 4 shown.

[0008] (1) By setting a mask, etching the oxide layer 8 to open a window, and performing the first ion implantation;

[0009] (2) high temperature annealing to form a second conductivity type semiconductor doped region 5;

[0010] (3) depositing polysilicon and etching to form a polysilicon field plate 9;

[0011] (4) Metal Al is deposited and etched to form an Al metal field plate 10 , which together with the polysilicon field plate 9 constitutes a composite field plate.

[0012] The high temperature refers to greater than 1100 degrees Celsius.

[0013] As a preferred embodiment, step (1) is further:

[0014] Figure 5 Schematic diagram of the first ion implantation mask setting for the VLD terminal. The VLD terminal BC is divided into N segments, each with a length of L. VLD / N, where the length of the VLD terminal is L VLD The window width of the nth mask is a n , impurity injection is achieved in this area. The width of the shielding area is b n , both satisfy a n +b n =L VLD / N. The first ion implantation dose is dose1.

[0015] As a preferred embodiment, step (2) is further:

[0016] High temperature annealing is performed to connect the injected impurities into one piece through the diffusion of impurities, thereby forming a second conductive type semiconductor doped region 5. The high temperature is greater than 1100 degrees Celsius. n-1 and a n The impurity distribution of the two implants satisfies the Gaussian distribution function after high temperature annealing. n The impurity distribution under the window area a is approximately satisfied n-1 with a n The superposition of the implanted impurities, such as Figure 6 As shown, the mask shielding area b n The impurity distribution function C under (x) satisfy

[0017]

[0018] The first ion implantation dose is dose1, x n for a n The x-axis coordinate corresponding to the center position, x n-1 for a n-1 The x-axis coordinate corresponding to the center position, D is the impurity diffusion coefficient, which is related to factors such as annealing temperature, and t represents the high-temperature annealing time. According to the impurity distribution function C (x) , obviously in the mask shielding area b n Next x JAt position, there is a point J with the lowest impurity concentration.

[0019] As a preferred embodiment, step (3) is further:

[0020] A layer of polysilicon is deposited and etched, wherein the polysilicon layer mask is as follows: Figure 7 As shown, the width of the mask area of ​​the nth segment is d n The polysilicon in this area is not etched, but is retained to form a polysilicon field plate. The width of the shielding area of ​​the nth mask is d n Cover the first ion implantation mask shielding area b n . N is the number of segments of the VLD terminal BC;

[0021] For d n The value of satisfies

[0022] N≥n>1

[0023] 1.25b n ≥d n >b n .

[0024] As a preferred embodiment, step (4) is further:

[0025] A layer of metal Al is deposited and etched to form a composite field plate. The metal Al mask is as follows Figure 8 As shown, the width of the mask area of ​​the nth segment is f n , the metal Al in this area is not etched, but forms an Al metal field plate, and the mask shielding area width f of the nth mask n The width of the mask area covering the polysilicon layer is d n , that is, metal Al can cover polysilicon to form a composite field plate. The lowest impurity concentration point J is located below the composite field plate, and the high surface electric field peak generated by it is suppressed. The principle is as follows Fig. 9 As shown. A part of the electric lines of force emitted by the ionized donors in the first conductive type semiconductor drift region 3 terminates at the field plate through the surface, which is equivalent to the introduction of negative charges on the surface of the first conductive type semiconductor drift region 3 under the field plate. Another part of the electric lines of force terminates at the second conductive type semiconductor variable doping region 5 through the surface from the field plate, which is equivalent to the introduction of positive charges on the surface of the second conductive type semiconductor variable doping region 5 under the field plate. Because the field plate is floating, the electric flux entering the field plate and the electric flux emitted from the field plate are equal. The additional electric field generated by the introduction of positive or negative charges on the surface is opposite to the original electric field, which weakens the peak value of the original electric field.

[0026] For f n The value of satisfies

[0027] 1.25d n ≥f n >d n .

[0028] The principle of the present invention is:

[0029] The present invention is based on the mask setting method of the traditional VLD terminal. On the basis of a single ion implantation, a floating composite field plate is set, thereby improving the reliability problem of the VLD terminal having an excessively high surface electric field peak value caused by uneven impurity distribution and improving the withstand voltage performance of the VLD terminal.

[0030] The beneficial effects of the present invention are:

[0031] It is highly feasible and can effectively improve the reliability problem of the VLD terminal due to uneven impurity distribution and too low impurity concentration in some areas, which leads to excessively high surface electric field peak. A floating composite field plate is set up based on a single ion implantation. The electric flux entering the floating field plate and the electric flux emitted from the floating field plate are equal. The additional electric field generated by the introduction of positive or negative charges on the surface is opposite to the original electric field, so as to weaken the original electric field peak and improve the reliability and withstand voltage performance of the VLD terminal. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 A schematic diagram of the principle of a high-reliability VLD terminal.

[0033] Point J is the point with the lowest impurity concentration at the VLD terminal, and E max1 is the peak value of the surface electric field corresponding to point J of the actual wavy impurity distribution, E max2 is the peak value of the surface electric field corresponding to the J point of the smooth and gradual impurity distribution. n-1 with a n is the window area of ​​the first ion implantation mask, used for ion implantation, b n This is the shielding area of ​​the mask for the first ion implantation.

[0034] Figure 2 This is an overall structural diagram of a power device layout involved in the present invention.

[0035] AB represents the second conductivity type semiconductor main junction 4, BC represents the second conductivity type semiconductor variable doping region 5, and D represents the outermost edge of the layout.

[0036] Figure 3 The schematic cross-sectional view of the VLD terminal involved in the present invention is shown in FIG. Figure 2 ABCD corresponds in.

[0037] The invention comprises a drain electrode metal 1, a heavily doped first conductive type semiconductor substrate 2 located on the drain electrode metal, a lightly doped first conductive type semiconductor drift region 3 located on the heavily doped first conductive type semiconductor substrate 2, a second conductive type semiconductor main junction 4, a second conductive type semiconductor variable doping region 5 and a heavily doped second conductive type semiconductor cut-off ring 6 located on the upper surface of the first conductive type semiconductor drift region 3, a source electrode metal 7 located on the second conductive type semiconductor main junction 4, an oxide layer 8 located on the second conductive type semiconductor variable doping region 5 and the second conductive type semiconductor cut-off ring 6, a polysilicon field plate 9 located on the oxide layer 8, an Al metal field plate 10 located on the polysilicon field plate 9, and the Al metal field plate 10 and the polysilicon field plate 9 constitute a composite field plate. Definition: The direction from the oxide layer 8 vertically pointing to the lightly doped first conductive type semiconductor drift region 3 is the y-axis direction, and the parallel direction from the oxide layer 8 to the junction of the second conductive type semiconductor variable doping region 5 is the x-axis direction.

[0038] Figure 4 The present invention is a schematic diagram of a process implementation flow of a high-reliability VLD terminal.

[0039] Figure 5 It is a schematic diagram of the first ion implantation mask of the VLD terminal involved in the present invention.

[0040] Figure 6 The VLD terminal mask shielding area b of the present invention n Below the window area a n-1 with a n The impurity distribution formed by the high-temperature annealing of the injected impurities.

[0041] Figure 7 This is the polysilicon etching mask involved in the present invention.

[0042] Figure 8 This is the Al metal etching mask involved in the present invention.

[0043] Fig. 9 Schematic diagram of the principle of composite field plates suppressing high surface electric fields.

[0044] Fig.10 For example 3, only Figure 4 The process flow (1), (2) and implementation steps shown Figure 4 The breakdown voltage of the VLD terminal in the process flow (1)-(4) shown in the figure varies with the implantation dose dos e 1 Schematic diagram of changes.

[0045] Fig.11 Dose 1 in Example 3 is 1.4e13 cm -2 Only implemented when Figure 4The process flow (1), (2) and implementation steps shown Figure 4 Schematic diagram of the partial surface electric field of the VLD terminal in the process steps (1)-(4) shown. DETAILED DESCRIPTION

[0046] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0047] Example 1

[0048] A high-reliability VLD terminal improves the reliability problem of excessively high surface electric field peaks caused by the wavy impurity distribution of the VLD terminal through a single ion implantation plus a floating composite field plate, and improves the withstand voltage performance of the VLD terminal. Figure 4 shown.

[0049] (1) By setting a mask, etching the oxide layer 8 to open a window, and performing the first ion implantation;

[0050] (2) high temperature annealing to form a second conductivity type semiconductor doped region 5;

[0051] (3) depositing polysilicon and etching to form a polysilicon field plate 9;

[0052] (4) Metal Al is deposited and etched to form an Al metal field plate 10 , which together with the polysilicon field plate 9 constitutes a composite field plate.

[0053] The high temperature refers to greater than 1100 degrees Celsius.

[0054] Example 2

[0055] A high-reliability VLD terminal improves the reliability problem of excessively high surface electric field peaks caused by the wavy impurity distribution of the VLD terminal through a single ion implantation plus a floating composite field plate, and improves the withstand voltage performance of the VLD terminal. Figure 4 shown.

[0056] (1) By setting a mask, etching the oxide layer 8 to open a window, and performing the first ion implantation;

[0057] Step (1) is further: Figure 5 Schematic diagram of the first ion implantation mask setting for the VLD terminal. The VLD terminal BC is divided into N segments, each with a length of L. VLD / N, where the length of the VLD terminal is L VLDThe window width of the nth mask is a n , impurity injection is achieved in this area. The width of the shielding area is b n , both satisfy a n +b n =L VLD / N. The first ion implantation dose is dose1.

[0058] (2) high temperature annealing to form a second conductivity type semiconductor doped region 5;

[0059] Step (2) is further: high temperature annealing, so that the injected impurities are connected into one piece through the diffusion of impurities, so as to form a second conductive type semiconductor variable doping region 5. n-1 and a n The impurity distribution of the two implants satisfies the Gaussian distribution function after high temperature annealing. n The impurity distribution under the window area a is approximately satisfied n-1 with a n The superposition of the implanted impurities, such as Figure 6 As shown, the mask shielding area b n The impurity distribution function C under (x) satisfy

[0060]

[0061] The first ion implantation dose is dose1, x n for a n The x-axis coordinate corresponding to the center position, x n-1 for a n-1 The x-axis coordinate corresponding to the center position, D is the impurity diffusion coefficient, which is related to factors such as annealing temperature, and t represents the high-temperature annealing time. According to the impurity distribution function C (x) , obviously in the mask shielding area b n Next x J At position, there is a point J with the lowest impurity concentration.

[0062] (3) depositing polysilicon and etching to form a polysilicon field plate 9;

[0063] Step (3) further comprises: depositing a layer of polysilicon and etching, wherein the polysilicon layer mask is as follows: Figure 7 As shown, the width of the mask area of ​​the nth segment is d n The polysilicon in this area is not etched, but is retained to form a polysilicon field plate. The width of the shielding area of ​​the nth mask is d n Should cover the first ion implantation mask shielding area b n . N is the number of segments of the VLD terminal BC;

[0064] For dn The value of satisfies

[0065] N≥n>1

[0066] 1.25b n ≥d n >b n .

[0067] (4) Metal Al is deposited and etched to form an Al metal field plate 10 , which together with the polysilicon field plate 9 constitutes a composite field plate.

[0068] Step (4) further comprises: depositing a layer of metal Al and etching to form a composite field plate. The metal Al mask is as follows: Figure 8 As shown, the width of the mask area of ​​the nth segment is f n , the metal Al in this area is not etched, but forms an Al metal field plate, and the mask shielding area width f of the nth mask n The width d of the mask area of ​​the polysilicon layer should be covered n , that is, metal Al can cover polysilicon to form a composite field plate. The lowest impurity concentration point J is located below the composite field plate, and the high surface electric field peak generated by it is suppressed. The principle is as follows Fig. 9 As shown. A part of the electric lines of force emitted by the ionized donors in the first conductive type semiconductor drift region 3 terminates at the field plate through the surface, which is equivalent to the introduction of negative charges on the surface of the first conductive type semiconductor drift region 3 under the field plate. Another part of the electric lines of force terminates at the second conductive type semiconductor variable doping region 5 through the surface from the field plate, which is equivalent to the introduction of positive charges on the surface of the second conductive type semiconductor variable doping region 5 under the field plate. Because the field plate is floating, the electric flux entering the field plate and the electric flux emitted from the field plate are equal. The additional electric field generated by the introduction of positive or negative charges on the surface is opposite to the original electric field, which weakens the peak value of the original electric field.

[0069] For f n The value of satisfies

[0070] 1.25d n ≥f n >d n .

[0071] The high-reliability VLD terminal is used for the lateral variable doping terminal design of diodes, BJTs, MOSFETs, JFETs, and IGBT power semiconductor devices.

[0072] The power semiconductor device with the terminal is manufactured using semiconductor materials such as silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, indium phosphide and gallium nitride.

[0073] Example 3

[0074] This example applies a high-reliability VLD terminal proposed in the invention to a VDMOS with a withstand voltage of 1500V. The specific steps are as follows:

[0075] (1) The VDMOS cell is designed through simulation, and the designed cell withstand voltage is 1734V. The total length of the VLD terminal is set to 225μm, the number of mask segments n is 15 segments, and each segment is 15μm long. The length of the shielding area b n The variation of the number of segments n is shown in Table 1. Ion implantation is performed using the mask.

[0076] Table 1 Length b of the VLD terminal shielding area for the first ion implantation in Example 3 n

[0077] n 1 2 3 4 5 6 7 8 <![CDATA[b n / μm]]> 4.5 5 5.5 6 6.5 7 7.5 8 n 9 10 11 12 13 14 15 <![CDATA[b n / μm]]> 8.5 9 9.5 10 10.5 11 11.5

[0078] (2) The first ion implantation high temperature annealing, the annealing temperature is 1150°C, and the time is 500 minutes.

[0079] (3) Deposit polysilicon and etch to form a polysilicon field plate. The length of the shielding area is d n The changes with the number of segments n are shown in Table 2. The length of the shielded area d n Should cover the shielding area length b n .

[0080] Table 2 Length d of the polysilicon mask shielding area in Example 3 n

[0081] n 1 2 3 4 5 6 7 8 <![CDATA[d n / μm]]> 4.95 5.5 6.05 6.6 7.15 7.7 8.25 8.8 n 9 10 11 12 13 14 15 <![CDATA[d n / μm]]> 9.35 9.9 10.45 11 11.55 12.1 12.65

[0082] (4) Deposit metal Al and etch to form an Al metal field plate. Shielding area length f n The changes with the number of segments n are shown in Table 3. The length of the shielding area f n Should cover the shielding area length d n .

[0083] Table 3 Length f of metal Al shielding area in Example 3 n

[0084] n 1 2 3 4 5 6 7 8 <![CDATA[f n / μm]]> 5.445 6.05 6.655 7.26 7.865 8.47 9.075 9.68 n 9 10 11 12 13 14 15 <![CDATA[f n / μm]]> 10.285 10.89 11.495 12.1 12.705 13.31 13.915

[0085] (5) Carry out simulation experiments on the design scheme, such as Fig.10 The figure shows the breakdown voltage of the VLD terminal implemented by only performing steps (1) and (2) and the VLD terminal implemented by performing steps (1) to (4) with a composite field plate as a function of the implantation dose dose1. It can be seen that the VLD terminal with a composite field plate implemented by performing steps (1) to (4) has a better breakdown voltage. Fig. 9FIG. 5 is a schematic diagram of a portion of the surface electric field of a VLD terminal implemented by performing only steps (1) and (2) and a VLD terminal implemented by performing steps (1) to (4). It can be seen that the VLD terminal with a composite field plate that performs steps (1) to (4) completely has a lower surface electric field peak value. The surface electric field at the same x-axis position can be reduced from 1.5e5 V / cm to below 5e4 V / cm, which is a large reduction. This means that the VLD terminal implemented by this design method has better reliability, the improvement effect is very obvious, and the withstand voltage performance has also been effectively improved.

[0086] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical ideas disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A high-reliability VLD terminal, characterized in that: Through a single ion implantation plus a floating composite field plate, the reliability problem of the excessively high peak value of the surface electric field caused by the wavy impurity distribution of the VLD terminal is improved and the withstand voltage performance of the VLD terminal is improved. The process flow is as follows: (1) by setting a mask, etching the oxide layer (8) to open a window, and performing the first ion implantation; (2) high temperature annealing to form a second conductivity type semiconductor variable doping region (5); (3) depositing polysilicon and etching to form a polysilicon field plate (9); (4) depositing metal Al and etching to form an Al metal field plate (10) which forms a composite field plate with the polysilicon field plate (9).

2. A high-reliability VLD terminal according to claim 1, characterized in that: Step (1) is further as follows: setting a mask for the first ion implantation of the VLD terminal, dividing the VLD terminal BC into N segments, each segment having a length of L VLD / N, where the length of the VLD terminal is L VLD , using positive photoresist for photolithography, the window width of the nth mask is a n , impurities are injected into this area, and the width of the shielding area is b n , both satisfy a n +b n =L VLD / N, the first ion implantation dose is dose1.

3. A high-reliability VLD terminal according to claim 1, characterized in that: Step (2) is further: high temperature annealing, through the diffusion of impurities, the injected impurities are connected into one piece to form a second conductive type semiconductor variable doping region (5), for the window area a n-1 and a n The impurity distribution of the two implants satisfies the Gaussian distribution function after high temperature annealing. n The impurity distribution under the window area a is approximately satisfied n-1 with a n The superposition of the injected impurities, the mask shielding area b n The impurity distribution function C under (x) satisfy The first ion implantation dose is dose1, x n for a n The x-axis coordinate corresponding to the center position, x n-1 for a n-1 The x-axis coordinate corresponding to the center position, D is the impurity diffusion coefficient, which is related to factors such as annealing temperature, t represents the high temperature annealing time, according to the impurity distribution function C (x) , obviously in the mask shielding area b n Next x J At position, there is a point J with the lowest impurity concentration.

4. A high-reliability VLD terminal according to claim 1, characterized in that: Step (3) further comprises: depositing a layer of polysilicon and etching, wherein the width of the shielding area of ​​the nth segment of the polysilicon layer mask is d n The polysilicon in this area is not etched, but is retained to form a polysilicon field plate. The width of the shielding area of ​​the nth mask is d n Should cover the first ion implantation mask shielding area b n ; N is the number of segments of the VLD terminal BC; For d n The value of satisfies N≥n>1 1.25b n ≥d n >b n 。 5. A high-reliability VLD terminal according to claim 1, characterized in that: Step (4) further comprises: depositing a layer of metal Al and etching to form a composite field plate, wherein the width of the shielding area of ​​the metal Al mask plate nth section is f n , the metal Al in this area is not etched, but forms an Al metal field plate, and the mask shielding area width f of the nth mask n The width d of the mask area of ​​the polysilicon layer should be covered n That is, the metal Al can cover the polysilicon, thereby forming a composite field plate. The lowest impurity concentration point J is located below the composite field plate, reducing the peak value of the surface electric field. A part of the electric lines emitted by the ionized donors of the first conductive type semiconductor drift region (3) terminates at the field plate through the surface, which is equivalent to introducing negative charges on the surface of the first conductive type semiconductor drift region (3) under the field plate. Another part of the electric lines terminates at the second conductive type semiconductor variable doping region (5) through the surface from the field plate, which is equivalent to introducing positive charges on the surface of the second conductive type semiconductor variable doping region (5) under the field plate. Because the field plate is floating, the electric flux entering the field plate and the electric flux emitted from the field plate are equal. The additional electric field generated by the positive or negative charges introduced on the surface is opposite to the original electric field, thereby weakening the original electric field peak value. For f n The value of satisfies <h2 style=";text-align:left;direction:ltr">1.25d<h2 style=";text-align:left;direction:ltr"> n <h2 style=";text-align:left;direction:ltr"> ≥f<h2 style=";text-align:left;direction:ltr"> n <h2 style=";text-align:left;direction:ltr"> >d<h2 style=";text-align:left;direction:ltr"> n <h2 style=";text-align:left;direction:ltr"> 。 6. A high-reliability VLD terminal according to claim 1, characterized in that: The process flow is used for the design of lateral variable doping terminals of diode, BJT, MOSFET, JFET and IGBT power semiconductor devices.

7. A high-reliability VLD terminal according to claim 1, characterized in that: The power semiconductor device with the terminal is manufactured using semiconductor materials such as silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, indium phosphide and gallium nitride.

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