Ultra-wideband amplifier based on multi-inductor coupling

Abstract

The invention provides an ultra-wideband amplifier based on multi-inductor coupling. The ultra-wideband amplifier comprises a multi-inductor high-order coupling network and a multi-stage cascade network, the multi-inductor high-order coupling network comprises a multi-inductor high-order input matching network and a multi-inductor high-order inter-stage matching network; the multi-stage cascade network comprises a cascode amplification module, a common-source amplification module and a voltage bias module; the design freedom degree of the multi-order matching network is improved, meanwhile, gain planarization, a low noise coefficient and good matching are achieved, and the chip area is reduced; according to the invention, conjugate matching to 50 ohms can be realized in a very wide bandwidth, and broadband matching is realized; the quality factor of the grid inductor is improved, the loss caused by series resonant cavities is improved, and the noise coefficient is reduced; according to the invention, the bandwidth can be further improved, and a plurality of networks act together to present the final ultra-wideband; according to the invention, the input signal source admittance is changed, so that the source admittance is close to the optimal noise impedance, and the impedance required by conjugate matching and the optimal noise impedance are realized.

Description

Technical Field

[0001] The invention relates to the technical field of amplifiers, in particular to an ultra-wideband amplifier based on multi-inductor coupling. Background Art

[0002] With the rapid development of mobile communications, the development of communications is gradually moving towards higher speeds. In order to meet the demand for higher communication speeds, existing technologies have expanded the frequency to the millimeter wave band of 24GHz-40GHz. According to Shannon's theorem, high bandwidth means high communication speed. It is relatively easy to meet the high bandwidth requirements in the frequency band of 5G communications. It can be seen that the use of millimeter wave bands can not only alleviate the problem of spectrum tension, but also improve the communication rate of the system. Among them, the hot spots of millimeter wave applications are in three frequency bands, namely Ku band (12GHz-18GHz), K band (18GHz-27GHz) and Ka band (27GHz-40GHz).

[0003] The realization of cloud detection and near-Earth satellite communication in the millimeter wave band is inseparable from the radio frequency (RF) receiving front end, which consists of filters, low-noise amplifiers and mixers. The filter will filter the signal received by the antenna and transmit it to the low-noise amplifier. After the low-noise amplifier amplifies the useful signal, it is transmitted to the mixer and finally outputs the signal to the baseband for processing.

[0004] A low noise amplifier (LNA) is an amplifier used to amplify weak signals while minimizing the introduction of additional noise. It plays a vital role in wireless communication systems, RF transceivers, radar systems, antenna receiving systems, and other fields. With the continuous development of wireless communication and radar technology, the demand for LNA is also increasing. However, it is difficult for existing low noise amplifiers to maintain good input and output matching over a wider frequency band. Secondly, the noise performance of existing low noise amplifiers is affected by circuit parasitics and process noise; and the linearity, dynamic range, and power consumption of existing low noise amplifiers are still not well optimized. Summary of the invention

[0005] In view of the deficiencies in the prior art, the present invention provides an ultra-wideband amplifier based on multi-inductor coupling. The present invention achieves broadband matching and noise matching through a multi-inductor high-order coupling network.

[0006] The technical solution of the present invention is: an ultra-wideband amplifier based on multi-inductor coupling, comprising a multi-inductor high-order coupling network and a multi-stage cascade network;

[0007] The multi-inductor high-order coupling network includes a multi-inductor high-order input matching network and two multi-inductor high-order inter-order matching networks;

[0008] The multi-stage cascade network includes two common-source and common-gate amplifier modules, a common-source amplifier module, and a voltage bias module; the two common-source and common-gate amplifier modules and the common-source amplifier module are connected in sequence; and the two common-source and common-gate amplifier modules and the common-source amplifier module are both connected to the voltage bias module, and the transistor gate DC voltage and drain-source DC voltage of the common-source and common-gate amplifier modules and the common-source amplifier modules are controlled by the voltage bias module;

[0009] The front end of the first common-source and common-gate module is connected to a multi-inductor high-order input matching network; the first multi-inductor high-order inter-order matching network is connected between the two common-source and common-gate modules; and the second multi-inductor high-order input matching network is connected between the second common-source and common-gate module and the common-source amplifier module.

[0010] Preferably, the multi-inductor high-order input matching network and the multi-inductor high-order inter-order matching network are respectively a multi-inductor sixth-order input matching network and a multi-inductor sixth-order inter-order matching network.

[0011] Preferably, the common-source and common-gate amplifier module includes nmos transistors M1 and M2 connected in cascode form, the drain of the nmos transistor M1 is connected to the source of the nmos transistor M2, and the nmos transistors M1 and M2 are connected to a multi-inductor sixth-order input matching network; while obtaining a higher gain and improving reverse isolation through the common-source and common-gate amplifier module, the input signal is amplified and coupled to the next stage.

[0012] Preferably, the substrates of the nmos transistors M1 and M2 are connected to the ground through a high resistor R to reduce substrate noise current and substrate noise.

[0013] Preferably, the multi-inductor sixth-order input matching network includes an inductor L1, an inductor L2, an inductor L3, a capacitor C1, a capacitor C2 and a capacitor Cgs1; one end of the capacitor C1 is connected to the input interface IN and one end of the capacitor C2, and the other end of the capacitor C2 is grounded; the other end of the capacitor C1 is connected in parallel with the inductor L1 and the inductor L2; the other end of the inductor L1 is connected to the voltage bias module, and the voltage bias module provides a bias voltage VG1 for the inductor L1; the other end of the inductor L2 is connected to the gate of the nmos transistor M1; one end of the inductor L3 is connected to the source of the nmos transistor M1; the other end of the inductor L3 is grounded; the gate-source parasitic capacitor Cgs1 is connected between the source and the gate of the nmos transistor M1;

[0014] The gate of the nmos transistor M2 is also connected to the capacitor Cg1 and the voltage bias module, and the voltage bias module provides a bias voltage V1 for the gate of the nmos transistor M2; the inductor L1, the inductor L2, and the inductor L3 are coupled in pairs to form a sixth-order input matching network.

[0015] Preferably, the common-source and common-gate amplifier module includes nmos transistors M3 and M4 connected in cascode form; the drain of the nmos transistor M3 is connected to the source of the nmos transistor M4; and the nmos transistors M3 and M4 are connected to a multi-inductor six-stage inter-matching network.

[0016] Preferably, the substrates of the nmos transistors M3 and M4, and the nmos transistor M5 are connected to the ground through a high resistor R to reduce substrate noise current and substrate noise.

[0017] Preferably, the multi-inductor six-stage interstage matching network includes a previous stage interstage matching circuit and a current stage interstage matching circuit; the previous stage interstage matching circuit is connected to nmos transistors M3 and M4; and the current stage interstage matching circuit is connected to nmos transistor M5.

[0018] Preferably, the front-stage inter-stage matching circuit includes a front-stage inductor L5, a front-stage inductor L6, a front-stage inductor L4, a front-stage capacitor C3, and a front-stage capacitor Cgs2; one end of the front-stage capacitor C3 and the front-stage inductor L5 are connected in parallel to the gate of the nmos transistor M3; and the other end of the front-stage capacitor C3 and the front-stage inductor L5 is connected to a voltage bias module, and the voltage bias module provides a bias voltage VG2 for the front-stage capacitor C3 and the front-stage inductor L5;

[0019] The source of the nmos transistor M3 is connected to the front-stage inductor L6, and the other end of the front-stage inductor L6 is grounded;

[0020] A previous-stage gate-source parasitic capacitor Cgs2 is also connected between the source and gate of the nmos transistor M3;

[0021] One end of the front-stage inductor L4 is connected to the drain of the nmos transistor M2, and the other end of the front-stage inductor L4 is connected to the voltage bias module;

[0022] The gate of the nmos transistor M4 is connected to the front-stage capacitor Cg2 and the voltage bias module, and the voltage bias module provides a bias voltage V2 for the gate of the nmos transistor M4.

[0023] Preferably, the inter-stage matching circuit of this stage includes an inductor L8 of this stage, an inductor L9 of this stage, an inductor L7 of the previous stage, a capacitor C4 of this stage, a capacitor C5 of this stage, and a gate-source parasitic capacitor Cgs3 of this stage; one end of the inductor L8 of this stage and the capacitor C4 of this stage are connected in parallel to the gate of the nmos transistor M5; the other end of the inductor L8 of this stage and the capacitor C4 of this stage are connected to a voltage bias module, and the voltage bias module provides a bias voltage VG3 for the inductor L8 of this stage and the capacitor C4 of this stage;

[0024] The source of the nmos transistor M5 is connected in parallel with the inductor L9 and the capacitor C5 at the same level; the other ends of the inductor L9 and the capacitor C5 at the same level are grounded;

[0025] The drain of the nmos transistor M5 is connected in parallel with the capacitor C6 and the inductor L10 of the same level; the other ends of the capacitor C6 and the inductor L10 of the same level are connected to the voltage bias module;

[0026] The source and gate of the nmos transistor M5 are connected with a gate-source parasitic capacitor Cgs3 of this stage;

[0027] The inductor L10 of the current stage is also coupled with the inductor L11 of the current stage in a transformer coupling form, and both ends of the inductor L11 of the current stage are respectively connected to the capacitor C7 of the current stage; one end of the inductor L11 of the current stage and the capacitor C7 of the current stage are grounded, and the other end is connected to the output interface OUT;

[0028] The preceding stage inductor L7, the current stage inductor L8, and the current stage inductor L9 are coupled in pairs.

[0029] Preferably, the voltage bias module provides bias voltage for the gates of the nmos transistors M1, M2, M3, M4, and M5.

[0030] The beneficial effects of the present invention are:

[0031] 1. The present invention improves the design freedom of the multi-order matching network by designing a multi-inductor high-order input matching network and two multi-inductor high-order inter-order matching networks, while achieving gain flattening, low noise coefficient and good matching. At the same time, the high-order resonant cavity also helps to reduce the chip area;

[0032] 2. The multi-inductor high-order input matching network of the present invention couples the inductors to each other and can be conjugate matched to 50Ω within a wide bandwidth, thereby achieving broadband matching; and improving the quality factor of the gate inductor, improving the loss caused by the series resonant cavity, and reducing the noise coefficient; reducing the signal leakage of the parallel resonant cavity and reducing the noise factor;

[0033] 3. The multi-inductor coupling of the multi-inductor high-order inter-level matching network of the present invention can further improve the bandwidth, and multiple networks work together to present the final ultra-wideband;

[0034] 4. The present invention changes the input signal source admittance so that the source admittance is close to the optimal noise impedance, and simultaneously realizes the impedance required for conjugate matching and the optimal noise impedance. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 It is a schematic diagram of the framework of the amplifier of the present invention;

[0036] Figure 2 A schematic diagram of the connection between the multi-inductor high-order coupling network and the voltage bias module of the present invention;

[0037] Figure 3 It is a connection circuit diagram of the multi-inductor sixth-order input matching network and the common-source and common-gate amplifier module of the present invention;

[0038] Figure 4 A connection circuit diagram of a multi-inductor six-stage inter-matching network and a common source amplifier module of the present invention;

[0039] Figure 5 is a S11 parameter simulation curve diagram of the ultra-wideband amplifier according to an embodiment of the present invention;

[0040] Figure 6 is a S22 parameter simulation curve diagram of the ultra-wideband amplifier according to an embodiment of the present invention;

[0041] Figure 7 is a S21 parameter simulation curve diagram of the ultra-wideband amplifier according to an embodiment of the present invention;

[0042] Figure 8 is a noise coefficient simulation curve diagram of an ultra-wideband amplifier according to an embodiment of the present invention;

[0043] Fig. 9 4 is a simulation curve diagram of the K parameter stability factor of the ultra-wideband amplifier according to the embodiment of the present invention. DETAILED DESCRIPTION

[0044] The specific implementation of the present invention will be further described below in conjunction with the accompanying drawings:

[0045] like Figure 1 As shown, this embodiment provides an ultra-wideband amplifier based on multi-inductor coupling, including a multi-inductor high-order coupling network and a multi-stage cascade network; the multi-inductor high-order coupling network is used to achieve broadband maximum power transmission matching and noise coefficient matching at the input node, so as to increase the matching bandwidth, reduce the noise coefficient, and improve the gain to a certain extent, and the multi-stage cascade network is used to jointly cascade the overall circuit.

[0046] In this embodiment, the multi-inductor high-order coupling network includes a multi-inductor high-order input matching network and two multi-inductor high-order inter-stage matching networks; and the multi-stage cascade network includes two common-source and common-gate amplifier modules, a common-source amplifier module, and a voltage bias module; the two common-source and common-gate amplifier modules and the common-source amplifier module are connected in sequence; and the two common-source and common-gate amplifier modules and the common-source amplifier module are connected to the voltage bias module, and the transistor gate DC voltage and drain-source DC voltage of the common-source and common-gate amplifier module and the common-source amplifier module are controlled by the voltage bias module; the front end of the first common-source and common-gate module is connected to the multi-inductor high-order input matching network; the first multi-inductor high-order inter-stage matching network is connected between the two common-source and common-gate modules; and the second multi-inductor high-order input matching network is connected between the second common-source and common-gate module and the common-source amplifier module.

[0047] As a preferred embodiment of the present invention, the multi-inductor high-order input matching network and the multi-inductor high-order inter-order matching network are respectively a multi-inductor sixth-order input matching network and a multi-inductor sixth-order inter-order matching network. The multi-inductor high-order input matching network changes the input signal source admittance so that the source admittance is close to the optimal noise impedance, while achieving the impedance required for conjugate matching and the optimal noise impedance.

[0048] As preferred in this embodiment, Figure 2 and 3 As shown, the common-source common-gate amplifier module includes nmos transistors M1 and M2 connected in cascode form, the drain of the nmos transistor M1 is connected to the source of the nmos transistor M2, and the common-source common-gate amplifier module is used to obtain a higher gain and improve the reverse isolation, amplify the input signal and couple it to the next stage. The substrates of the nmos transistors M1 and M2 are connected to the ground with a high resistance R to reduce the substrate noise current and reduce the substrate noise.

[0049] As preferred in this embodiment, Figure 2 and 3 As shown, the multi-inductor sixth-order input matching network includes an inductor L1, an inductor L2, an inductor L3, a capacitor C1, a capacitor C2 and a capacitor Cgs1; one end of the capacitor C1 is connected to the input interface IN and one end of the capacitor C2, and the other end of the capacitor C2 is grounded; the other end of the capacitor C1 is connected in parallel with the inductor L1 and the inductor L2; the other end of the inductor L1 is connected to the voltage bias module, and the voltage bias module provides a bias voltage VG1 for the inductor L1; the other end of the inductor L2 is connected to the gate of the nmos transistor M1; one end of the inductor L3 is connected to the source of the nmos transistor M1; the other end of the inductor L3 is grounded;

[0050] The gate-source parasitic capacitor Cgs1 is connected between the source and the gate of the nmos transistor M1;

[0051] One end of the inductor L4 is connected to the drain of the nmos transistor M2; the other end of the inductor L4 is connected to the voltage bias module; the gate of the nmos transistor M2 is also connected to the capacitor Cg1 and the voltage bias module, and the voltage bias module provides a bias voltage V1 for the gate of the nmos transistor M2; the inductor L1, the inductor L2, and the inductor L3 are coupled in pairs to form a sixth-order input matching network.

[0052] In this embodiment, the coupling of the inductor L1, the inductor L2, and the inductor L3 improves the quality factor of the gate inductor, improves the loss caused by the series resonant cavity, and reduces the noise coefficient; the coupling of the inductor L1, the inductor L2, and the inductor L4 improves the quality factor, reduces the signal leakage of the parallel resonant cavity, and reduces the noise factor.

[0053] As preferred in this embodiment, Figure 2 and 4 As shown, the common-source and common-gate amplifier module includes nmos transistors M3 and M4 connected in cascode form; the drain of the nmos transistor M3 is connected to the source of the nmos transistor M4; the substrates of the nmos transistors M3 and M4 are connected to the ground through a high resistance R to reduce substrate noise current and substrate noise.

[0054] As preferred in this embodiment, Figure 2 and 4 As shown, the multi-inductor six-stage inter-stage matching network includes a previous stage inter-stage matching circuit and a current stage inter-stage matching circuit; the previous stage inter-stage matching circuit is connected to the nmos transistors M3 and M4; the current stage inter-stage matching circuit is connected to the nmos transistor M5.

[0055] Preferably, the front-stage inter-stage matching circuit includes a front-stage inductor L5, a front-stage inductor L6, a front-stage inductor L4, a front-stage capacitor C3, and a front-stage capacitor Cgs2; one end of the front-stage capacitor C3 and the front-stage inductor L5 are connected in parallel to the gate of the nmos transistor M3; and the other end of the front-stage capacitor C3 and the front-stage inductor L5 is connected to a voltage bias module, and the voltage bias module provides a bias voltage VG2 for the front-stage capacitor C3 and the front-stage inductor L5;

[0056] The source of the nmos transistor M3 is connected to the front-stage inductor L6, and the other end of the front-stage inductor L6 is grounded;

[0057] A previous-stage gate-source parasitic capacitor Cgs2 is also connected between the source and gate of the nmos transistor M3;

[0058] One end of the front-stage inductor L4 is connected to the drain of the nmos transistor M2, and the other end of the front-stage inductor L4 is connected to the voltage bias module;

[0059] The gate of the nmos transistor M4 is connected to the front-stage capacitor Cgs2 and the voltage bias module, and the voltage bias module provides a bias voltage V2 for the gate of the nmos transistor M4.

[0060] The inter-stage matching circuit of this stage includes an inductor L8 of this stage, an inductor L9 of this stage, an inductor L7 of the previous stage, a capacitor C4 of this stage, a capacitor C5 of this stage, and a gate-source parasitic capacitor Cgs3 of this stage; one end of the inductor L8 of this stage and the capacitor C4 of this stage are connected in parallel to the gate of the nmos transistor M5; the other end of the inductor L8 of this stage and the capacitor C4 of this stage are connected to a voltage bias module, and the voltage bias module provides a bias voltage VG3 for the inductor L8 of this stage and the capacitor C4 of this stage;

[0061] The source of the nmos transistor M5 is connected in parallel with the inductor L9 and the capacitor C5 at the same level; the other ends of the inductor L9 and the capacitor C5 at the same level are grounded;

[0062] The source and gate of the nmos transistor M5 are connected with the gate-source parasitic capacitor Cgs3 of this stage.

[0063] The drain of the nmos transistor M5 is connected in parallel with a capacitor C6 and an inductor L10 at the same level; the other ends of the capacitor C6 and the inductor L10 at the same level are connected to a voltage bias module.

[0064] The inductor L10 of this stage is also coupled with the inductor L11 of this stage in the form of a transformer, and both ends of the inductor L11 of this stage are respectively connected to the capacitor C7 of this stage; one end of the inductor L11 of this stage and the capacitor C7 of this stage are grounded, and the other end is connected to the output interface OUT.

[0065] The preceding stage inductor L7, the current stage inductor L8, and the current stage inductor L9 are coupled in pairs.

[0066] As a preferred embodiment of the present invention, the voltage bias module provides a bias voltage for the gates of the nmos transistors M1, M2, M3, M4, and M5.

[0067] like Figure 5 As shown, the S11 input matching curve is below -10 dB in the frequency range of 10 GHz-35 GHz. The results show that the ultra-wideband amplifier provided in this embodiment has good input matching in the frequency range of 10 GHz-35 GHz.

[0068] refer to Figure 6It can be seen that the S22 input matching curve is below -10 dB in the frequency range of 10 GHz-35 GHz. The results show that the ultra-wideband amplifier provided in this embodiment has good output matching in the frequency range of 10 GHz-35 GHz.

[0069] refer to Figure 7 It can be seen that the S21 gain curve has only 2 dB ripple in the frequency range of 10 GHz-35 GHz. The results show that the ultra-wideband amplifier provided in this embodiment has a flat gain curve in the frequency range of 10 GHz-35 GHz.

[0070] refer to Figure 8 It can be seen that the noise figure simulation curve is below 3.1 dB in the frequency range of 10 GHz-35 GHz. The results show that the ultra-wideband amplifier provided in this embodiment has good noise figure matching and low noise figure in the frequency range of 10 GHz-35 GHz.

[0071] refer to Fig. 9 It can be seen that the K parameter stability factor simulation curve is basically above 10 in the frequency range of 10 GHz-35 GHz, which is much greater than 1. The results show that the ultra-wideband amplifier provided in this embodiment has good stability in the frequency range of 10 GHz-35 GHz.

[0072] The above embodiments and descriptions are only for illustrating the principles and best embodiments of the present invention. Without departing from the spirit and scope of the present invention, the present invention may be subject to various changes and improvements, all of which fall within the scope of the present invention to be protected.

Claims

1. An ultra-wideband amplifier based on multi-inductor coupling, characterized in that: It includes multi-inductor high-order coupling network and multi-stage cascade network; among them, The multi-inductor high-order coupling network includes a multi-inductor high-order input matching network and two multi-inductor high-order inter-order matching networks; The multi-stage cascade network includes two common-source and common-gate amplifier modules, a common-source amplifier module, and a voltage bias module; The two common-source and common-gate amplifier modules and the common-source amplifier module are connected in sequence; and the two common-source and common-gate amplifier modules and the common-source amplifier module are both connected to a voltage bias module, and the voltage bias module is used to control the transistor gate DC voltage and drain-source DC voltage of the common-source and common-gate amplifier module and the common-source amplifier module; The front end of the first common-source and common-gate module is connected to a multi-inductor high-order input matching network; the first multi-inductor high-order inter-order matching network is connected between the two common-source and common-gate modules; and the second multi-inductor high-order input matching network is connected between the second common-source and common-gate module and the common-source amplifier module.

2. The ultra-wideband amplifier based on multi-inductor coupling according to claim 1, characterized in that: The multi-inductor high-order input matching network and the multi-inductor high-order inter-order matching network are respectively a multi-inductor sixth-order input matching network and a multi-inductor sixth-order inter-order matching network.

3. The ultra-wideband amplifier based on multi-inductor coupling according to claim 2, characterized in that: The common-source and common-gate amplifier module includes nmos transistors M1 and M2 connected in cascode form, the drain of the nmos transistor M1 is connected to the source of the nmos transistor M2, and the nmos transistors M1 and M2 are also connected to a multi-inductor sixth-order input matching network.

4. The ultra-wideband amplifier based on multi-inductor coupling according to claim 3, characterized in that: The substrates of the nmos transistors M1 and M2 are connected to the ground via a high resistance R.

5. The ultra-wideband amplifier based on multi-inductor coupling according to claim 3, characterized in that: The multi-inductor sixth-order input matching network includes an inductor L1, an inductor L2, an inductor L3, a capacitor C1, a capacitor C2 and a gate-source parasitic capacitor Cgs1; one end of the capacitor C1 is connected to the input interface IN and one end of the capacitor C2, and the other end of the capacitor C2 is grounded; The other end of the capacitor C1 is connected in parallel with the inductor L1 and the inductor L2; the other end of the inductor L1 is connected to the voltage bias module, and the voltage bias module provides a bias voltage VG1 for the inductor L1; The other end of the inductor L2 is connected to the gate of the nmos transistor M1; One end of the inductor L3 is connected to the source of the nmos transistor M1; the other end of the inductor L3 is grounded; The gate-source parasitic capacitor Cgs1 is connected between the source and the gate of the nmos transistor M1; The gate of the nmos transistor M2 is also connected to the capacitor Cg1 and the voltage bias module, and the voltage bias module provides a bias voltage V1 for the gate of the nmos transistor M2; The inductors L1, L2 and L3 are coupled in pairs to form a sixth-order input matching network.

6. The ultra-wideband amplifier based on multi-inductor coupling according to claim 1, characterized in that: The common-source and common-gate amplifier module includes nmos transistors M3 and M4 connected in cascode form; the drain of the nmos transistor M3 is connected to the source of the nmos transistor M4, and the nmos transistors M3 and M4 are also connected to a multi-inductor six-stage inter-matching network.

7. The ultra-wideband amplifier based on multi-inductor coupling according to claim 6, characterized in that: The substrates of the nmos transistors M3 and M4 and the nmos transistor M5 are connected to the ground through a high resistor R to reduce substrate noise current and substrate noise.

8. The ultra-wideband amplifier based on multi-inductor coupling according to claim 6, characterized in that: The multi-inductor six-stage inter-stage matching network includes a previous stage inter-stage matching circuit and a current stage inter-stage matching circuit; the previous stage inter-stage matching circuit is connected to the nmos transistors M3 and M4; the current stage inter-stage matching circuit is connected to the nmos transistor M5.

9. The ultra-wideband amplifier based on multi-inductor coupling according to claim 8, characterized in that: The front-stage inter-stage matching circuit includes a front-stage inductor L5, a front-stage inductor L6, a front-stage inductor L4, a front-stage capacitor C3, and a front-stage gate-source parasitic capacitor Cgs2; one end of the front-stage capacitor C3 and the front-stage inductor L5 are connected in parallel to the gate of the nmos transistor M3; and the other end of the front-stage capacitor C3 and the front-stage inductor L5 is connected to a voltage bias module, and the voltage bias module provides a bias voltage VG2 for the front-stage capacitor C3 and the front-stage inductor L5; The source of the nmos transistor M3 is connected to the front-stage inductor L6, and the other end of the front-stage inductor L6 is grounded; A previous-stage gate-source parasitic capacitor Cgs2 is also connected between the source and gate of the nmos transistor M3; One end of the front-stage inductor L4 is connected to the drain of the nmos transistor M2, and the other end of the front-stage inductor L4 is connected to the voltage bias module; The gate of the nmos transistor M4 is connected to the capacitor Cg2 and the voltage bias module, and the voltage bias module provides a bias voltage V2 for the gate of the nmos transistor M4.

10. The ultra-wideband amplifier based on multi-inductor coupling according to claim 9, characterized in that: The inter-stage matching circuit of this stage includes an inductor L8 of this stage, an inductor L9 of this stage, an inductor L7 of the previous stage, a capacitor C4 of this stage, a capacitor C5 of this stage, and a gate-source parasitic capacitor Cgs3 of this stage; one end of the inductor L8 of this stage and the capacitor C4 of this stage are connected in parallel to the gate of the nmos transistor M5; the other end of the inductor L8 of this stage and the capacitor C4 of this stage are connected to a voltage bias module, and the voltage bias module provides a bias voltage VG3 for the inductor L8 of this stage and the capacitor C4 of this stage; The source of the nmos transistor M5 is connected in parallel with the inductor L9 and the capacitor C5 at the same level; the other ends of the inductor L9 and the capacitor C5 at the same level are grounded; The source and gate of the nmos transistor M5 are connected with a gate-source parasitic capacitor Cgs3 of this stage; The drain of the nmos transistor M5 is connected in parallel with the capacitor C6 and the inductor L10 of the same level; the other ends of the capacitor C6 and the inductor L10 of the same level are connected to the voltage bias module; The inductor L10 of the current stage is also coupled with the inductor L11 of the current stage in the form of a transformer, and both ends of the inductor L11 of the current stage are respectively connected to the capacitor C7 of the current stage; one end of the inductor L11 of the current stage and the capacitor C7 of the current stage are grounded, and the other end is connected to the output interface OUT; The preceding stage inductor L7, the current stage inductor L8, and the current stage inductor L9 are coupled in pairs.

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