High-speed radio frequency analog-to-digital converter correction method based on reference channel

Abstract

The invention discloses a high-speed radio frequency analog-to-digital converter correction method based on a reference channel. The method comprises the following steps: performing gain error correction on the reference channel; the output channel samples an input signal, the reference channel samples an inverse signal of the input signal, pseudo-random signals are injected into MDACs of the two channels, a first output code and a second output code are obtained, and gain error correction is carried out according to the first output code and the second output code; constant differential voltage is injected into the input end of the reference channel, so that the rest transmission curve translates transversely; and simultaneously sampling an input signal by using the output channel and the reference channel to obtain a third output code and a fourth output code, and carrying out capacitor mismatch correction according to the third output code and the fourth output code. According to the invention, the inter-stage gain error of the output channel is rapidly corrected by using the reference channel, and the capacitor mismatch correction object does not contain the capacitor mismatch of the reference channel, so that the area and power consumption of the correction circuit can be reduced.

Description

Technical Field

[0001] The invention belongs to the technical field of integrated circuits, and in particular relates to a high-speed radio frequency analog-to-digital converter calibration method based on a reference channel. Background Art

[0002] High-speed and high-precision analog-to-digital converters (ADCs) are widely used in communication base stations, satellite remote sensing, and other fields, and play a vital role in aerospace, national defense, and military industries. However, factors such as capacitor mismatch and inter-stage gain error caused by process deviations during the manufacturing process seriously affect the performance indicators of the ADC and worsen the nonlinearity of the ADC quantization process. Therefore, the ADC needs to be calibrated.

[0003] In the related art, the ADC can be corrected by using a pseudo-random signal correction method, which is to add a PN*V dither The pseudo-random signal PN is a sequence of 1 and -1, and its mathematical expectation is 0, V dither is a constant value, and the signal is allowed to follow the sampling signal through the same quantization path to extract the error value. It has become a hot topic in academia because of its small changes to the original ADC and good correction effect. However, there is natural digital noise in the PN-based correction method, which reduces its correction speed and accuracy. The digital noise mainly comes from the limited number of bits of the averager. Specifically, in the pseudo-random signal correction algorithm, the estimation of the gain error ε is achieved by the following formula:

[0004]

[0005] In the above formula, D is the output of the averager, G is the ideal gain of the MDAC (multiplying digital-to-analog converter), ε is the gain error, and V res is the residual signal, N is the number of sampling points, LSB BE is the minimum quantization step size of the subsequent ADC. PN(i) represents the i-th bit of the pseudo-random signal PN. Since the mathematical expectation of PN is 0, the first term on the right side of the above formula should be 0, but since N cannot approach ∞ in practice, the first term is not 0, resulting in the estimated value ε calculated by the circuit. e ≠ε, so the correction effect is not ideal.

[0006] In the related art, the ADC calibration can also refer to the ADC method, such as Figure 1 As shown, this method completes the correction of the main ADC by adding a low-speed high-precision reference ADC. This method has the effect of fast correction, but this method has high requirements on the accuracy of the ADC. If there is a capacitor mismatch in it, it will affect the capacitor mismatch calibration, and the ADC itself also has non-ideal factors. Summary of the invention

[0007] In order to solve the above problems existing in the prior art, the present invention provides a high-speed radio frequency analog-to-digital converter calibration method based on a reference channel.

[0008] The technical problem to be solved by the present invention is achieved through the following technical solutions:

[0009] A high-speed radio frequency analog-to-digital converter calibration method based on a reference channel, wherein the output channel of the analog-to-digital converter includes a pre-stage ADC, an MDAC and a post-stage ADC which are cascaded in sequence; the method includes:

[0010] Providing a reference channel and performing gain error correction on the reference channel; the reference channel and the output channel have the same structure and synchronized clocks;

[0011] Performing output channel gain error correction, including: using the output channel to sample an input signal, and using the reference channel to sample an inverse signal of the input signal, injecting the same pseudo-random signal into the input ends of the two MDACs during the sampling process, and obtaining a first output code and a second output code at the output ends of the two subsequent ADCs respectively; performing gain error correction on the output channel according to the first output code and the second output code;

[0012] The method comprises: injecting a constant differential voltage into the input end of the reference channel so that the margin transfer curve of the reference channel is laterally shifted; sampling the input signal simultaneously by using the output channel and the reference channel to obtain a third output code and a fourth output code at the output ends of the two subsequent ADCs respectively; and performing capacitance mismatch correction on the output channel according to the third output code and the fourth output code.

[0013] Optionally, performing gain error correction on the reference channel includes:

[0014] Injecting a constant voltage into the input end of the MDAC of the reference channel, sampling the constant voltage using the MDAC of the reference channel and a subsequent ADC, and obtaining a fifth output code at the output end of the subsequent ADC of the reference channel;

[0015] A gain error correction is performed on the reference channel according to the fifth output code.

[0016] Optionally, performing gain error correction on the reference channel according to the fifth output code includes:

[0017] Subtract each bit of the fifth output code from the corresponding expected value, and divide the difference by the corresponding first attenuation factor to obtain the gain error coefficient of the reference channel at that bit; wherein the first attenuation factor is equal to the expected value minus 2N-1 , N is the number of quantization bits of the subsequent ADC;

[0018] Gain error correction is performed on the reference channel according to the gain error coefficient of each bit of the reference channel.

[0019] Optionally, the constant voltage is greater than 0V and less than or equal to 1*LSB volt; LSB is the minimum quantization step size of the subsequent ADC.

[0020] Optionally, the amplitude of the constant differential voltage is -0.5*LSB volts; LSB is the minimum quantization step size of the subsequent ADC.

[0021] Optionally, performing gain error correction on the output channel according to the first output code and the second output code includes:

[0022] Adding the first output code and the second output code to obtain an added code;

[0023] Multiplying the added code by the pseudo-random signal at the corresponding time to obtain a multiplied code;

[0024] Accumulating a plurality of the multiplied codes, and averaging the accumulated codes when the accumulated codes reach a preset number to obtain a cumulative average code;

[0025] Divide each bit of the accumulated average code by the corresponding second attenuation factor and then subtract 2 to obtain the gain error coefficient of the output channel at the bit; wherein the second attenuation factor is obtained from the digital code obtained by amplifying the pseudo-random signal by an ideal amplifier and then quantizing it by an ideal quantizer;

[0026] Gain error correction is performed on the output channel according to the gain error coefficient of each bit of the output channel.

[0027] Optionally, the third output code and the fourth output code are both composed of a pre-stage code and a post-stage code; the pre-stage code is output by the pre-stage ADC, each pre-stage code corresponds to an MSB region, and multiple MSB regions are sorted according to the pre-stage code; the post-stage code is a code after the pre-stage code;

[0028] The performing capacitance mismatch correction on the output channel according to the third output code and the fourth output code comprises:

[0029] Obtaining third output codes corresponding to various MSB regions, and obtaining fourth output codes corresponding to various MSB regions;

[0030] Subtracting the post-stage codes of the third output code and the fourth output code corresponding to the same MSB region to obtain a plurality of error codes, each error code corresponding to an MSB region;

[0031] The error codes corresponding to the same MSB region are averaged to obtain multiple average error codes, each of which corresponds to an MSB region;

[0032] Subtracting the average error codes of adjacent MSB regions to obtain a first shift value of a subsequent MSB region relative to a previous MSB region;

[0033] Determine the second translation value of the 2nd to nth MSB regions relative to the margin transfer curve according to each of the first translation values; wherein the first MSB region has no corresponding second translation value; n=2 N1 , N1 is the number of bits of the previous ADC;

[0034] Capacitance mismatch correction is performed on the output channels according to each of the second translation values.

[0035] Optionally, after performing output channel gain error correction and before performing output channel capacitance mismatch correction, the method further includes:

[0036] Determine whether output channel capacitance mismatch correction has been performed;

[0037] If the output channel capacitance mismatch correction has been performed, then obtaining each second translation value obtained when the output channel capacitance mismatch correction is performed, and directly performing capacitance mismatch correction on the output channel according to each second translation value;

[0038] If the output channel capacitance mismatch correction has not been performed, the step of performing the output channel capacitance mismatch correction is continued, and each obtained second shift value is stored for later use.

[0039] The high-speed radio frequency analog-to-digital converter calibration method based on the reference channel provided by the present invention uses the reference channel to quickly calibrate the inter-stage gain error of the output channel, so that the calibration speed of the ADC is greatly improved. Afterwards, a constant differential voltage is injected into the input end of the reference channel to cause the margin transfer curve of the reference channel to shift horizontally, so that it can not only provide a calibration reference for the transfer curve of the output channel, but also make the capacitance mismatch of the reference channel have no effect on the calibration effect, so that the capacitance mismatch calibration object does not include the capacitance mismatch of the reference channel, and the area and power consumption of the digital calibration circuit are reduced.

[0040] The present invention will be further described in detail below with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 It is a schematic diagram of the existing reference ADC method for calibrating the ADC;

[0042] Figure 2is a flow chart of a high-speed RF analog-to-digital converter calibration method based on a reference channel provided in an embodiment of the present invention;

[0043] Figure 3 yes Figure 2 A schematic diagram of performing gain error correction on a reference channel in the method shown;

[0044] Figure 4 yes Figure 2 A schematic diagram of output channel gain error correction in the method shown;

[0045] Figure 5 yes Figure 2 A schematic diagram of output channel capacitance mismatch correction in the method shown;

[0046] Figure 6 The margin transfer curve between the output channel and the reference channel under ideal conditions is shown as an example.

[0047] Figure 7 The input transfer curves of the output channel and the reference channel are shown exemplarily;

[0048] Figure 8 The input transfer curves of the output channel and the reference channel under capacitance mismatch are shown as an example. DETAILED DESCRIPTION

[0049] The present invention is further described in detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.

[0050] In order to effectively improve the correction effect of ADC, the embodiment of the present invention provides a high-speed RF analog-to-digital converter correction method based on a reference channel, which can quickly correct the inter-stage gain error and capacitor mismatch in the pipeline analog-to-digital converter, such as Figure 2 As shown, the method comprises the following steps:

[0051] S10, providing a reference channel and performing gain error correction on the reference channel, wherein the reference channel and the output channel of the analog-to-digital converter have the same structure and are clock synchronized.

[0052] See also Figure 3 As shown, the output channel includes a pre-stage ADC, an MDAC and a post-stage ADC which are cascaded in sequence. The reference channel and the output channel have the same structure and are clock synchronized. Figure 3 The entire circuit structure of the reference channel is not shown.

[0053] In step S10, gain error correction is performed on the reference channel, including:

[0054] (1) To the MDAC of the reference channel ( Figure 3A constant voltage is injected into the input terminal of the MDAC2 in the reference channel, and the constant voltage is sampled by using the MDAC of the reference channel and the subsequent ADC, so as to obtain a fifth output code Dout5 at the output terminal of the subsequent ADC of the reference channel.

[0055] The constant voltage is greater than 0V and less than or equal to 1*LSB volt, for example, the constant voltage may be 0.5*LSB volt; here, LSB is the minimum quantization step size of the subsequent ADC.

[0056] In addition, while the MDAC of the reference channel and the subsequent ADC are sampling the constant voltage, the output channel can sample the input signal normally. Figure 3 As shown in the figure, the positive input terminal of the front-stage ADC of the output channel is connected to the positive voltage VIP of the input signal, and the negative input terminal is connected to the negative voltage VIN of the input signal, so that the input signal is sampled by the output channel; at the same time, the MDAC ( Figure 3 The input end of MDAC1 in the circuit is injected with a pseudo-random signal PN to keep the output channel in normal quantization output. Figure 3 As shown, an adder is used to add the residual signal output by the front-stage ADC of the output channel to the pseudo-random signal PN to realize the injection of the pseudo-random signal.

[0057] (2) Perform gain error correction on the reference channel according to the fifth output code.

[0058] Specifically, performing gain error correction on the reference channel according to the fifth output code includes:

[0059] (2-a) Subtract each bit of the fifth output code from the corresponding expected value, and divide the difference by the corresponding first attenuation factor to obtain the gain error coefficient of the reference channel at that bit; wherein the first attenuation factor is equal to the expected value minus 2 N-1 , N is the number of quantization bits of the subsequent ADC;

[0060] (2-b) Gain error correction is performed on the reference channel according to the gain error coefficient of each bit of the reference channel.

[0061] Specifically, the output code of the reference channel is subtracted by 2 through a subtractor. N-1 , and then divided by (1+ε e ), and then add 2 through the adder N-1 The gain error correction can be completed. Here, ε e This is the gain error coefficient obtained in step S10.

[0062] In addition, in order to ensure the accuracy of the error estimation value obtained, the operation step of performing gain error correction on the reference channel can be repeated multiple times, so that the gain error coefficients obtained in multiple operation cycles are averaged as the gain error coefficients finally obtained in step S10. Then, the reference channel is subjected to gain error correction according to the finally obtained gain error coefficients.

[0063] In actual calibration, the above-mentioned operation steps of performing gain error correction on the reference channel can be implemented in a GEC (Gain Error Correction) circuit. The gain error correction circuit has built-in modules such as a subtractor, a divider, and a shift operation unit, so that operations such as subtraction and division can be easily implemented. In addition, the first attenuation factor and the expected value can also be pre-stored in the GEC circuit.

[0064] In step S10, by injecting a deterministic input into the reference channel, and then comparing the difference between the actual output and the ideal output to obtain the actual error of the circuit, the gain error correction of the reference channel can be completed quickly.

[0065] S20, performing output channel gain error correction, including: using the output channel to sample the input signal, and using the reference channel to sample the inverse signal of the input signal, injecting the same pseudo-random signal into the input ends of the MDACs of the two channels during the sampling process, thereby obtaining a first output code and a second output code at the output ends of the post-stage ADCs of the two channels respectively; and performing gain error correction on the output channel according to the first output code and the second output code.

[0066] See also Figure 4 , the positive input terminal of the front-stage ADC of the output channel is connected to the positive voltage VIP of the input signal, and the negative input terminal is connected to the negative voltage VIN of the input signal; at the same time, the positive input terminal of the front-stage ADC of the reference channel is connected to the negative voltage VIN of the input signal, and the negative input terminal is connected to the positive voltage VIPN of the input signal; the residual signals output by the front-stage ADC of the two channels are respectively added to the same pseudo-random signal PN by using an adder, so as to inject the same pseudo-random signal PN into the input terminals of the MDACs of the two channels, thereby obtaining the first output code Dout1 and the second output code Dout2 at the output terminals of the back-stage ADCs of the two channels respectively.

[0067] Then, the output channel is subjected to gain error correction according to the first output code and the second output code, specifically comprising:

[0068] (1) adding the first output code and the second output code to obtain an added code;

[0069] (2) multiplying the added code by the pseudo-random signal at the corresponding time to obtain a multiplied code;

[0070] (3) accumulating the multiple multiplication codes, and averaging them when the accumulation reaches a preset number to obtain a cumulative average code; the number of the multiplication codes to be accumulated can be preset and determined, and the embodiment of the present invention does not limit this;

[0071] (4) dividing each bit of the accumulated average code by the corresponding second attenuation factor and then subtracting 2 to obtain a gain error coefficient of the output channel at that bit; wherein the second attenuation factor is derived from a digital code obtained by amplifying the pseudo-random signal by an ideal amplifier and then quantizing it by an ideal quantizer;

[0072] (5) Perform gain error correction on the output channel according to the gain error coefficient of each bit of the output channel.

[0073] Specifically, the output code of the output channel is subtracted by 2 through the subtractor N-1 , then divided by (1+ε) through the divider, and then added by 2 through the adder N-1 Here, ε is the gain error coefficient obtained in step S20.

[0074] In addition, in order to ensure the accuracy of the error estimation value obtained, the operation step of performing gain error correction on the output channel can be repeated multiple times, so that the gain error coefficients obtained in multiple operation cycles are averaged as the final gain error coefficient. Then, the output channel is subjected to gain error correction according to the final gain error coefficient.

[0075] It can be understood that, since the quantization objects of the output channel and the reference channel are analog signals of the same magnitude and opposite directions, the step S20 can quickly reduce the amount irrelevant to PN in the pseudo-random signal algorithm to 0, greatly accelerating the correction speed of the PN algorithm. The principle can be expressed by the following formula:

[0076]

[0077] In the above formula, PN(i) represents the i-th bit of the pseudo-random signal, D is the output of the averager used to calculate the cumulative average code in step (4), G is the ideal gain of the MDAC of the output channel, and V res is the margin signal of the output channel, which is output by the front-end ADC of the output channel. dither It is a constant voltage superimposed on the pseudo-random signals 1 and -1. The meanings of the remaining parameters refer to the above.

[0078] Based on the above formula, it can be seen that although there is still an inter-stage gain error in the output channel, after adding the corresponding term of the reference channel, the numerator in the first term on the right side of the above formula decreases, so the first term is much smaller than the existing pseudo-random signal correction method, thereby improving the correction accuracy and correction speed.

[0079] In actual calibration, the above-mentioned operation steps of performing gain error correction on the output channel can also be implemented in a GEC (Gain Error Correction) circuit. The gain error correction circuit has built-in modules such as adders, multipliers, accumulators, dividers, averagers, subtractors, and shift operation units, so that various operations required for the correction operation can be easily realized. The second attenuation factor can also be pre-stored in the GEC circuit.

[0080] S30, performing output channel capacitance mismatch correction, including: injecting a constant differential voltage into the input end of the reference channel, so that the margin transfer curve of the reference channel is laterally shifted; using the output channel and the reference channel to sample the input signal simultaneously, so as to obtain a third output code and a fourth output code at the output end of the subsequent ADC of the two channels respectively; and performing capacitance mismatch correction on the output channel according to the third output code and the fourth output code.

[0081] After the gain calibration of the two channels is completed, the capacitance mismatch of the output channel is corrected. When the sampling clock becomes low, the sampling of the output channel and the reference channel ends. At the same time, see Figure 5 As shown, a constant differential voltage is additionally injected into the reference channel input terminal, and its amplitude is preferably set to -0.5*LSB volt (but not limited to this), thereby causing the margin transfer curve of the reference channel to shift horizontally. Among them, since the constant differential voltage is a differential voltage, Figure 5 The voltages added to the positive and negative input terminals of the reference channel are 0.25*LSB volts and -0.25*LSB volts respectively.

[0082] Figure 6 The margin transfer curve between the output channel and the reference channel under ideal conditions is shown as an example, and the corresponding ADC quantization curve is shown as follows: Figure 7 When there is a capacitor mismatch in the channel, for a multi-stage pipeline ADC, its quantization curve will shift up and down in each MSB (big endian) and LSB (little endian) area corresponding to the previous ADC. The direction and size of the shift are determined by the capacitor mismatch encountered when the previous ADC generates the margin. The corresponding quantization curve is shown in Figure 8 Therefore, this feature can be used to correct the capacitor mismatch in the output channel.

[0083] Specifically, in practice, the third output code Dout3 and the fourth output code Dout4 obtained from the output ends of the two post-stage ADCs are both composed of a previous-stage code and a post-stage code; the previous-stage code is output by the previous-stage ADC, each previous-stage code corresponds to an MSB area, and multiple MSB areas are sorted according to the previous-stage code; the post-stage code is the code after the previous-stage code.

[0084] Therefore, the capacitance mismatch correction is performed on the output channel according to the third output code and the fourth output code, specifically including:

[0085] (1) obtaining a third output code corresponding to various MSB regions, and obtaining a fourth output code corresponding to various MSB regions;

[0086] (2) subtracting the subsequent codes of the third output code and the fourth output code corresponding to the same MSB region to obtain a plurality of error codes, each error code corresponding to an MSB region;

[0087] (3) averaging the error codes corresponding to the same MSB region to obtain a plurality of average error codes, each of which corresponds to an MSB region; the number of average error codes may be preset;

[0088] (4) subtracting the average error codes of adjacent MSB regions to obtain a first shift value of the subsequent MSB region relative to the preceding MSB region;

[0089] (5) Determine the second shift values ​​of the 2nd to nth MSB regions relative to the margin transfer curve according to each first shift value; wherein the first MSB region has no corresponding second shift value; n is the number of MSB regions, n=2 N1 , N1 is the number of bits of the previous ADC;

[0090] Specifically, the operation in step (5) can be expressed by the following formula:

[0091]

[0092] In the above formula, error i～i-1 represents the first translation value of the i-th MSB region relative to the i-1-th MSB region, E i represents the second translation value of the i-th MSB region relative to the margin transfer curve.

[0093] (6) Performing capacitance mismatch correction on the output channel according to each second shift value.

[0094] Specifically, the corresponding MSB region is determined according to the previous code in the output code of the output channel, and then the second translation value of the MSB region relative to the margin transfer curve is subtracted from the subsequent code of the output channel to complete the capacitance mismatch correction of the output channel.

[0095] from Figure 8 It can also be seen that even if there is a capacitor mismatch in the reference channel, it will not affect the correction of the output channel.

[0096] In one embodiment, after performing output channel gain error correction and before performing output channel capacitance mismatch correction, the method of the embodiment of the present invention may further include the following steps:

[0097] (a) Determine whether output channel capacitance mismatch correction has been performed;

[0098] (b) If the output channel capacitance mismatch correction has been performed, then the respective second shift values ​​obtained when the output channel capacitance mismatch correction is performed are acquired, and the capacitance mismatch correction is performed on the output channel directly according to the respective second shift values; and if the output channel capacitance mismatch correction has not been performed, then the step of performing the output channel capacitance mismatch correction is continued, and the respective second shift values ​​obtained are stored for future use.

[0099] In practice, since the capacitance mismatch is only determined by the process mismatch, when the capacitance mismatch correction of the output channel is completed for the first time, it is only necessary to record the second translation value of each MSB area relative to the margin transfer curve. When the capacitance mismatch correction of the ADC is performed later, the capacitance mismatch correction of the output channel can be performed directly according to each second translation value, thereby realizing the rapid correction of capacitance mismatch. At the same time, since the capacitance mismatch of the reference channel does not need to be corrected, a large amount of area and power consumption of the capacitance mismatch correction circuit can be saved.

[0100] In summary, the high-speed RF analog-to-digital converter calibration method based on the reference channel provided by the embodiment of the present invention uses the reference channel to quickly calibrate the inter-stage gain error of the output channel, so that the calibration speed of the ADC is greatly improved. Then, by injecting a constant differential voltage at the input end of the reference channel, the margin transfer curve of the reference channel is horizontally shifted, which not only enables it to provide a calibration reference for the transfer curve of the output channel, but also ensures that the capacitance mismatch of the reference channel will not have any effect on the calibration effect, so that the calibration object of the correction circuit does not include the capacitance mismatch of the reference channel, reducing the area and power consumption of the digital correction circuit.

[0101] It should be noted that the terms "first", "second", etc. are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present disclosure described herein can be implemented in an order other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present disclosure. Instead, they are merely examples of devices and methods consistent with some aspects of the present disclosure.

[0102] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification.

[0103] Although the present application is described herein in conjunction with various embodiments, in the process of implementing the claimed application, those skilled in the art can understand and implement other changes to the disclosed embodiments by viewing the drawings and the disclosed content. In the description of the present invention, the term "comprising" does not exclude other components or steps, "one" or "an" does not exclude multiple situations, and the meaning of "multiple" is two or more, unless otherwise clearly and specifically limited. In addition, certain measures are recorded in different embodiments, but this does not mean that these measures cannot be combined to produce good results.

[0104] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the protection scope of the present invention.

Claims

1. A high-speed radio frequency analog-to-digital converter calibration method based on a reference channel, characterized in that: The output channel of the analog-to-digital converter includes a pre-stage ADC, an MDAC and a post-stage ADC which are cascaded in sequence; the method includes: Providing a reference channel and performing gain error correction on the reference channel; the reference channel and the output channel have the same structure and synchronized clocks; Performing output channel gain error correction, including: using the output channel to sample an input signal, and using the reference channel to sample an inverse signal of the input signal, injecting the same pseudo-random signal into the input ends of the two MDACs during the sampling process, and obtaining a first output code and a second output code at the output ends of the two subsequent ADCs respectively; performing gain error correction on the output channel according to the first output code and the second output code; The method comprises: injecting a constant differential voltage into the input end of the reference channel so that the margin transfer curve of the reference channel is laterally shifted; sampling the input signal simultaneously by using the output channel and the reference channel to obtain a third output code and a fourth output code at the output ends of the two subsequent ADCs respectively; and performing capacitance mismatch correction on the output channel according to the third output code and the fourth output code.

2. The method according to claim 1, characterized in that The performing gain error correction on the reference channel comprises: Injecting a constant voltage into the input end of the MDAC of the reference channel, sampling the constant voltage using the MDAC of the reference channel and a subsequent ADC, and obtaining a fifth output code at the output end of the subsequent ADC of the reference channel; A gain error correction is performed on the reference channel according to the fifth output code.

3. The method according to claim 2, characterized in that The performing gain error correction on the reference channel according to the fifth output code comprises: Subtract each bit of the fifth output code from the corresponding expected value, and divide the difference by the corresponding first attenuation factor to obtain the gain error coefficient of the reference channel at that bit; wherein the first attenuation factor is equal to the expected value minus 2 N-1 , N is the number of quantization bits of the subsequent ADC; Gain error correction is performed on the reference channel according to the gain error coefficient of each bit of the reference channel.

4. The method according to claim 2, characterized in that: The constant voltage is greater than 0V and less than or equal to 1*LSB volt; LSB is the minimum quantization step size of the subsequent ADC.

5. The method according to claim 1, characterized in that The amplitude of the constant differential voltage is -0.5*LSB volts; LSB is the minimum quantization step size of the subsequent ADC.

6. The method according to claim 1, characterized in that The performing gain error correction on the output channel according to the first output code and the second output code comprises: Adding the first output code and the second output code to obtain an added code; Multiplying the added code by the pseudo-random signal at the corresponding time to obtain a multiplied code; Accumulating a plurality of the multiplied codes, and averaging the accumulated codes when the accumulated codes reach a preset number to obtain a cumulative average code; Divide each bit of the accumulated average code by the corresponding second attenuation factor and then subtract 2 to obtain the gain error coefficient of the output channel at the bit; wherein the second attenuation factor is taken from the digital code obtained by amplifying the pseudo-random signal by an ideal amplifier and then quantizing it by an ideal quantizer; Gain error correction is performed on the output channel according to the gain error coefficient of each bit of the output channel.

7. The method according to claim 1, characterized in that The third output code and the fourth output code are both composed of a pre-stage code and a post-stage code; the pre-stage code is output by the pre-stage ADC, each pre-stage code corresponds to an MSB area, and multiple MSB areas are sorted according to the pre-stage code; The latter code is the code after the former code; The performing capacitance mismatch correction on the output channel according to the third output code and the fourth output code comprises: Obtaining third output codes corresponding to various MSB regions, and obtaining fourth output codes corresponding to various MSB regions; Subtracting the post-stage codes of the third output code and the fourth output code corresponding to the same MSB region to obtain a plurality of error codes, each error code corresponding to an MSB region; The error codes corresponding to the same MSB region are averaged to obtain multiple average error codes, each of which corresponds to an MSB region; Subtracting the average error codes of adjacent MSB regions to obtain a first shift value of a subsequent MSB region relative to a previous MSB region; Determine the second translation value of the 2nd to nth MSB regions relative to the margin transfer curve according to each of the first translation values; wherein the first MSB region has no corresponding second translation value; n=2 N1 , N1 is the number of bits of the previous ADC; Capacitance mismatch correction is performed on the output channels according to each of the second translation values.

8. The method according to claim 7, characterized in that After performing output channel gain error correction and before performing output channel capacitance mismatch correction, the method further includes: Determine whether output channel capacitance mismatch correction has been performed; If the output channel capacitance mismatch correction has been performed, then obtaining each second translation value obtained when the output channel capacitance mismatch correction is performed, and directly performing capacitance mismatch correction on the output channel according to each second translation value; If the output channel capacitance mismatch correction has not been performed, the step of performing the output channel capacitance mismatch correction is continued, and each obtained second shift value is stored for later use.

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