Single-line return-to-zero code LED drive control chip circuit

Abstract

The invention discloses a single-line return-to-zero code LED drive control chip circuit which comprises a power management circuit, a start reset circuit, an oscillator circuit, a bias current circuit, a digital circuit and a light emitting diode drive circuit. The light emitting diode driving circuit comprises a driving channel of a white light emitting diode chip, a driving channel of a red light emitting diode chip, a driving channel of a green light emitting diode chip and a driving channel of a blue light emitting diode chip, and the power management circuit is used for ensuring that the power supply is turned off when all-zero data or no data is input by analyzing the states of the previous data and the next data in the power management signal. The single-line return-to-zero code LED driving control chip solves the problems that the current single-line return-to-zero code LED driving control chip with a three-channel design does not have a sleep mode, so that effective power consumption management is lacked when the brightness and the color of an LED are controlled, and the whole LED device still has static power consumption waste in a non-light-emitting state.

Description

Technical Field

[0001] The invention relates to the field of circuit design, and in particular to a single-line return-to-zero code LED drive control chip circuit board. Background Art

[0002] Today's single-line return-to-zero LED driver control chips are mostly designed with three channels, usually configured as red, green, and blue (RGB) outputs. This type of chip lacks effective power management when controlling LED brightness and color, especially without a sleep mode, so that the overall LED device still wastes static power when it is not emitting light. This problem of static power waste limits its application in mobile device applications.

[0003] Therefore, a new technical solution for a single-line return-to-zero code LED driver control chip circuit is currently needed to solve the problem that the current three-channel single-line return-to-zero code LED driver control chip has no sleep mode, resulting in a lack of effective power consumption management when controlling LED brightness and color, and the overall LED device still has static power consumption waste when it is not emitting light. Summary of the invention

[0004] The present application provides a single-line return-to-zero code LED driver control chip circuit, which solves the problem that the current three-channel single-line return-to-zero code LED driver control chip has no sleep mode, resulting in a lack of effective power consumption management when controlling LED brightness and color, so that the overall LED device still has static power consumption waste when not emitting light.

[0005] In order to solve the above problems, the present application provides a single-line return-to-zero code LED drive control chip circuit, including: a power management circuit, a startup reset circuit, an oscillator circuit, a bias current circuit, a digital circuit and a light-emitting diode drive circuit, the light-emitting diode drive circuit including a drive channel for a white light-emitting diode chip, a drive channel for a red light-emitting diode chip, a drive channel for a green light-emitting diode chip and a drive channel for a blue light-emitting diode chip, wherein the power management circuit is used to ensure that the power is turned off when all zero data or no data is input by analyzing the state of the previous data and the next data in the power management signal; the startup reset circuit is used to generate a reset signal after the system is powered on, and transmit the reset signal to the oscillator circuit The circuit is used to connect the bias current circuit and the digital circuit to ensure that all circuits are started synchronously and complete the operation of entering a stable working state; the oscillator circuit is used to send the generated system clock signal to the digital circuit and the light-emitting diode drive circuit to drive the timing control of the subsequent logic and ensure the synchronization of data processing and control of each light-emitting diode chip; the bias current circuit is used to provide a stable bias current for each light-emitting diode drive circuit to ensure that a consistent current input can be obtained under different working conditions and ensure the stability of the brightness of each light-emitting diode chip; the digital circuit is used to receive and process the input data and transmit the generated control signal to the light-emitting diode drive circuit to adjust the brightness of each light-emitting diode chip and the control of the color output.

[0006] Furthermore, the above circuit may also include: the power management circuit is used to ensure that the power is turned off when all zero data or no data is input by analyzing the state of the previous data and the next data in the power management signal, specifically: the power management circuit realizes the transmission of the reset signal, logic control and the generation of the final enable signal through the mutual cooperation of the combination logic gate and the trigger, and controls the switching state of the bias current circuit and the oscillator circuit of the whole system by analyzing the serial input data DIN;

[0007] Among them, the serial input data DIN includes the following four cases:

[0008] The serial input data DIN is 32 bits of all-zero data, and the next data after reset is non-zero 32 bits of data;

[0009] The serial input data DIN is non-all-zero 32-bit data, and the next data after reset is non-zero 32-bit data;

[0010] The serial input data DIN is 32 bits of all-zero data, and no data arrives after reset;

[0011] The serial input data DIN is non-all-zero 32-bit data, and no data arrives after reset.

[0012] Furthermore, the above-mentioned circuit may also include: the startup reset circuit includes an analog reset circuit and a digital reset circuit, the analog reset circuit is used to output an analog reset signal to realize the reset control of the system; the digital reset circuit is used to output a digital reset signal to realize a delay, ensure the output of a reliable reset signal, and realize the reset control of the system.

[0013] Furthermore, the above circuit may also include: the oscillator circuit includes: an osc_data unit and an osc_pwm unit, wherein the osc_data unit is used for data sampling to generate a frequency signal of 3.5MHz, and its enable signal EN_OSC is generated by a digital unit; the osc_pwm unit is used for power consumption control of the system, and when the system enters a zero power consumption state, the osc_pwm unit is turned off to reduce system power consumption; when the system is in a normal working state, the osc_pwm unit is turned on to generate a corresponding PWM signal to control the brightness of each light-emitting diode chip and the signal modulation operation.

[0014] Furthermore, the above-mentioned circuit may also include: the bias current circuit includes multiple P-type and N-type metal oxide semiconductor transistors and resistors, and controls and adjusts the bias current according to the control of the current mirror and the reference current generation strategy, generates a stable bias current for the light-emitting diode driving circuit, and controls the brightness adjustment of each light-emitting diode.

[0015] Furthermore, the above circuit may also include: the light-emitting diode driving circuit is also used to convert the signal from the serial data input into parallel grayscale data for controlling the LED display, the serial data is input from the external DIN port, and is converted into parallel data through the data clock signal OSC_data_DIV_4, and the generated parallel data is stored in the register to control the brightness change of each light-emitting diode chip, wherein by comparing the PWM signal and the grayscale data, a system with a fixed DC voltage is obtained, and the current flows through the LED driver at a preset frequency. Assuming that the maximum current passing through the light-emitting diode chip is Imax, and the off time of each cycle is t, the average current is calculated by the following duty cycle formula:

[0016] Id=Imax*Duty cycle,

[0017] Duty cycle = 100*((1 / (2^8))(2^7*B7+2^6*B6+2^5*B5+2^4*B4+2^3*B3+2^2*B2+2^1*B1+2^0*B0)), where B0, B1, B2, B3, B4, B5, B6 and B7 are the grayscale data displayed by the light-emitting diode chip.

[0018] According to the OSC_PWM counter, the maximum on and off time t of LED_LATCH is equal to OSC_PWM_DIV_256. By controlling the duty cycle of the PWM signal, the average current of each LED chip is accurately adjusted to achieve brightness control.

[0019] Furthermore, the above-mentioned circuit may also include: the digital circuit includes a data sampling circuit and a data conversion circuit, wherein the data sampling circuit is used to realize sampling of input data, recovery of clock signals, and generation of reset control signals synchronized with the input data, and the data sampling circuit includes a counter, a numerically controlled oscillator NCO, a differential frequency detector DFD, multiple logic gates and multiple triggers; the data conversion circuit is used to convert serial data based on the microcontroller MCU into parallel data for driving the light-emitting diode chip, and after the system power-on reset POR, the data conversion circuit receives data through the DIN port, controls its data conversion process based on multiple 32-bit input signals, and generates a signal for driving the light-emitting diode chip output.

[0020] Through the above scheme, the present application is applied, and the power management circuit determines whether there is a valid working demand by analyzing the input data. When the input data is all zero, the system determines it as an invalid state, and the power consumption module enters the sleep mode; when valid data is detected, the system immediately wakes up the relevant modules to resume normal operation. The power management signal POWER_EN is jointly determined by the state of the previous data and the next data, ensuring that the power consumption circuit is turned on only when needed, thereby reducing unnecessary energy consumption, especially turning off the power consumption circuit when all zero data or no data is input. Through the combination of NAND gates, inverters and triggers, the automatic enabling and disabling of analog circuits such as current bias and OSC is realized, thereby improving the efficiency of the system. This dynamic control mechanism based on data state enables the circuit to respond quickly to actual working needs while reducing energy consumption, ensuring that system performance is not affected. This power management mechanism significantly reduces the energy consumption of the chip when the LED is not emitting light, thereby greatly improving the efficiency and practicality of the overall system. Among them, the single-line return-to-zero code LED driver control chip architecture uses 4 independent LED chip drive channels. In addition to supporting the traditional red, green, and blue (RGB) three-color LED chip drive channels, it also adds a separate LED drive channel for white light, which is used in situations where white light is needed, without the need to use RGB to mix colors to produce white light. Compared with the traditional RGB mixing method, the direct generation of white light through a separate white light channel reduces power consumption and improves the consistency of light effect, especially in scenes where white light needs to be used for a long time. In addition, the addition of white light sources in scenes with various colors of light can better achieve color temperature control, significantly reduce overall power consumption, and broaden the application scenarios of single-line return-to-zero code LED driver control chips. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0022] Figure 1 The figure shows a schematic diagram of the structure of the single-line return-to-zero code LED drive control chip circuit of the present application;

[0023] Figure 2 Shown is a schematic diagram of the structure of the startup reset circuit of the present application. DETAILED DESCRIPTION

[0024] In order to make the purpose, technical solution and advantages of the present application clearer, the technical solution of the present application will be clearly and completely described below in combination with the specific embodiments of the present application and the corresponding drawings. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present application.

[0025] The technical solutions provided by various embodiments of the present application are described in detail below in conjunction with the accompanying drawings.

[0026] The main idea of ​​the present application is that the power management circuit determines whether there is a valid working demand by analyzing the input data. When the input data is all zero, the system determines it as an invalid state, and the power consumption module enters the sleep mode; when valid data is detected, the system immediately wakes up the relevant circuit to resume normal operation. The power management signal POWER_EN is determined by the state of the previous data and the next data, ensuring that the power consumption circuit is turned on only when needed, thereby reducing unnecessary energy consumption, especially turning off the power consumption circuit when all zero data or no data is input. Through the combination of NAND gates, inverters and triggers, the automatic enabling and disabling of analog circuits such as current bias and OSC is realized, thereby improving the efficiency of the system. This dynamic control mechanism based on data state enables the circuit to respond quickly to actual working needs while reducing energy consumption, ensuring that system performance is not affected. This power management mechanism significantly reduces the energy consumption of the chip when the LED is not emitting light, thereby greatly improving the efficiency and practicality of the overall system. Among them, the single-line return-to-zero code LED driver control chip architecture uses 4 independent LED chip drive channels. In addition to supporting the traditional red, green, and blue (RGB) three-color LED chip drive channels, it also adds a separate LED drive channel for white light, which is used in situations where white light is needed, without the need to use RGB to mix colors to produce white light. Compared with the traditional RGB mixing method, the direct generation of white light through a separate white light channel reduces power consumption and improves the consistency of light effect, especially in scenes where white light needs to be used for a long time. In addition, the addition of white light sources in scenes with various colors of light can better achieve color temperature control, significantly reduce overall power consumption, and broaden the application scenarios of single-line return-to-zero code LED driver control chips.

[0027] like Figure 1The structural schematic diagram of the single-line return-to-zero code LED drive control chip circuit of the present application is shown. A single-line return-to-zero code LED drive control chip circuit of the present application may include: a power management circuit 0, a start-up reset circuit 1, an oscillator circuit 2, a bias current circuit 3, a digital circuit 4 and a light-emitting diode drive circuit 5. The light-emitting diode drive circuit includes a drive channel for a white light-emitting diode chip, a drive channel for a red light-emitting diode chip, a drive channel for a green light-emitting diode chip and a drive channel for a blue light-emitting diode chip. The power management circuit is used to ensure that the power is turned off when all zero data or no data is input by analyzing the state of the previous data and the next data in the power management signal; the start-up reset circuit is used to generate a reset signal after the system is powered on, and the reset signal is It is passed to the oscillator circuit, bias current circuit and digital circuit to ensure that all circuits start synchronously and complete the operation of entering a stable working state; the oscillator circuit is used to send the generated system clock signal to the digital circuit and the LED drive circuit to drive the timing control of the subsequent logic and ensure the synchronization of data processing and control of each LED chip; the bias current circuit is used to provide a stable bias current for each LED drive circuit to ensure that a consistent current input can be obtained under different working conditions and to ensure the stability of the brightness of each LED chip; the digital circuit is used to receive and process the input data and pass the generated control signal to the LED drive circuit to adjust the brightness and color output of each LED chip to achieve refined control of each channel.

[0028] The above setting determines whether there is a valid working demand through the analysis of the input data by the power management circuit. When the input data is all zero, the system determines it as an invalid state, and the power module enters the sleep mode; when valid data is detected, the system immediately wakes up the relevant circuit to resume normal operation. The power management signal POWER_EN is determined by the state of the previous data and the next data, ensuring that the power circuit is turned on only when needed, thereby reducing unnecessary energy consumption, especially turning off the power circuit when all zero data or no data is input. Through the combination of NAND gates, inverters and triggers, the automatic enabling and disabling of analog circuits such as current bias and OSC is realized, thereby improving the power efficiency of the system. This dynamic control mechanism based on data status enables the circuit to respond quickly to actual working needs while reducing energy consumption, ensuring that system performance is not affected. This power management mechanism significantly reduces the energy consumption of the chip when the LED is not emitting light, thereby greatly improving the efficiency and practicality of the overall system. Among them, the single-line return-to-zero code LED driver control chip architecture uses 4 independent LED chip drive channels. In addition to supporting the traditional red, green, and blue (RGB) three-color LED chip drive channels, it also adds a separate LED drive channel for white light, which is used in situations where white light is needed, without the need to use RGB to mix colors to produce white light. Compared with the traditional RGB mixing method, the direct generation of white light through a separate white light channel reduces power consumption and improves the consistency of light effect, especially in scenes where white light needs to be used for a long time. In addition, the addition of white light sources in scenes with various colors of light can better achieve color temperature control, significantly reduce overall power consumption, and broaden the application scenarios of single-line return-to-zero code LED driver control chips.

[0029] The startup reset circuit includes an analog reset circuit and a digital reset circuit. The analog reset circuit is used to output an analog reset signal to achieve system reset control; the digital reset circuit is used to output a digital reset signal to achieve a delay, ensuring reliable reset signal output and achieving system reset control. Figure 2As shown, the startup reset circuit 1 is composed of an analog reset circuit 101 and a digital reset circuit 102. The analog reset circuit 101 is composed of a P-type metal oxide semiconductor PM13, a P-type metal oxide semiconductor PM12, a P-type metal oxide semiconductor PM18, a P-type metal oxide semiconductor PM17, a P-type metal oxide semiconductor PM19, a P-type metal oxide semiconductor PM20, a P-type metal oxide semiconductor PM23, a P-type metal oxide semiconductor PM22, a P-type metal oxide semiconductor PM25, a P-type metal oxide semiconductor PM24, an N-type metal oxide semiconductor NM2, an N-type metal oxide semiconductor NM0, an N-type metal oxide semiconductor NM1, a Schmitt trigger SMIT_POR, an inverter INV_1p2_0p6, and an inverter INV_2p4_1p2. The source of the P-type metal oxide semiconductor PM13 is connected to the power supply VDD, and the drain is connected to the source of the next P-type metal oxide semiconductor PM12, forming a cascade relationship. The source of P-type metal oxide semiconductor PM12 is connected to the drain of P-type metal oxide semiconductor PM13, and the drain is connected to the source of the next P-type metal oxide semiconductor PM18. The source of P-type metal oxide semiconductor PM18 is connected to the drain of P-type metal oxide semiconductor PM12, and the drain is connected to the source of the next P-type metal oxide semiconductor PM17. The source of P-type metal oxide semiconductor PM17 is connected to the drain of P-type metal oxide semiconductor PM18, and the drain is connected to the source of the next P-type metal oxide semiconductor PM19. The source of P-type metal oxide semiconductor PM19 is connected to the drain of P-type metal oxide semiconductor PM17, and the drain is connected to the source of the next P-type metal oxide semiconductor PM20. The source of P-type metal oxide semiconductor PM20 is connected to the drain of P-type metal oxide semiconductor PM19, and the drain is connected to the source of the next P-type metal oxide semiconductor PM23. The source of P-type metal oxide semiconductor PM23 is connected to the drain of P-type metal oxide semiconductor PM20, and the drain is connected to the source of the next P-type metal oxide semiconductor PM22. The source of the P-type metal oxide semiconductor PM22 is connected to the drain of the P-type metal oxide semiconductor PM23, and the drain is connected to the source of the next P-type metal oxide semiconductor PM25. The source of the P-type metal oxide semiconductor PM25 is connected to the drain of the P-type metal oxide semiconductor PM22, and the drain is connected to the source of the next P-type metal oxide semiconductor PM24. The source of the P-type metal oxide semiconductor PM24 is connected to the drain of the P-type metal oxide semiconductor PM25, and the drain is connected to the source of the middle NMOS transistor network through a connecting line. The source of the N-type metal oxide semiconductor NM2 is connected to the ground (GND), and the drain is connected to the drain of the last stage P-type metal oxide semiconductor PM24 from the P-type metal oxide semiconductor PMOS series network.The source of the N-type metal oxide semiconductor NM0 is connected to the ground (GND), and the drain is connected together with the drain of NM2 to receive the output signal of the P-type metal oxide semiconductor PMOS network. The source of the N-type metal oxide semiconductor NM1 is connected to the ground (GND), and the drain is connected together with the drains of NM2 and NM0 to form a common connection node for transmitting the voltage signal to the Schmitt trigger. The input terminal A of the Schmitt trigger SMIT_POR is connected to the drain of the P-type metal oxide semiconductor PM24. The output terminal Y is connected to the input terminal of the first inverter INV_1p2_0p6 for transmitting a stable reset signal. The input terminal of the inverter INV_1p2_0p6 is connected to the output terminal Y of the Schmitt trigger. The output of the inverter is connected to the input terminal of the next inverter INV_2p4_1p2 to provide the first signal buffer. The input terminal of the inverter INV_2p4_1p2 is connected to the output terminal of INV_1p2_0p6. The output end of the inverter outputs the final reset signal por, which is transmitted to other circuits of the chip to ensure the stability of the reset signal. The digital reset circuit 102 is composed of a NAND gate nand2, an inverter INV_8P6_6P6, an inverter INV_6P6_6P6, an inverter INV_8P6_6P7, a D flip-flop Q1, a D flip-flop Q2, a D flip-flop Q3, a D flip-flop Q4, a D flip-flop Q5, a D flip-flop Q6, a three-input NAND gate I29, a four-input NAND gate I30, a NAND gate I28, and an inverter I34. The input end `A` of the NAND gate nand2 is connected to the `ad_osc_pwm` signal, the input end `B` is connected to the `dig_por` signal, and the output of nand2 is connected to the input end of the next-stage inverter INV_8P6_6P6. The input of inverter INV_8P6_6P6 is connected to the output of nand2 for inverting the output signal of nand2, and the output of INV_8P6_6P6 is connected to the clock input of the first D flip-flop Q1, `CKB`. The input of inverter INV_6P6_6P6INV_6P6_6P6 is connected to the output signal of Q3 for inverting the D flip-flop signal, and the output of INV_6P6_6P6 is connected to one input of NAND gate I30. The input of inverter INV_8P6_6P7INV_8P6_6P7 is connected to the output of NAND gate I30, and the output of the inverter is connected to the subsequent circuit or other logic control part. The `CKB` input of D flip-flop Q1 is connected to the output of INV_8P6_6P6 for receiving the inverted signal, and the output signal of Q1 is connected to the clock input of the next D flip-flop Q2, `CKB`. The `CKB` input of the D flip-flop Q2 is connected to the output of Q1, and the output signal of Q2 is connected to the clock input terminal `CKB` of the next D flip-flop Q3.The `CKB` input of D flip-flop Q3 is connected to the output of Q2, and the output signal of Q3 is connected to the clock input terminal `CKB` of the next D flip-flop Q4, and is connected to the input terminal of INV_6P6_6P6. The `CKB` input of D flip-flop Q4 is connected to the output of Q3, and the output signal of Q4 is connected to the clock input terminal `CKB` of the next D flip-flop Q5. The `CKB` input of D flip-flop Q5 is connected to the output of Q4, and the output signal of Q5 is connected to the clock input terminal `CKB` of the next D flip-flop Q6. The `CKB` input of D flip-flop Q6 is connected to the output of Q5, and the output signal of Q6 is connected to one input terminal of NAND gate I29. The input terminals of three-input NAND gate I29I29 are connected to the output signals of Q6, Q5 and Q4 respectively, and the output of I29 is connected to the input terminal of NAND gate I30, which participates in the generation of reset logic. The input of the four-input NAND gate I30 is connected to the output of I29, receiving the signal from the three-input NAND gate, and the other inputs are connected to the output signals of Q3 and other D flip-flops. The output of I30 is connected to the input of the inverter INV_8P6_6P7. The input of the NAND gate I28 is connected to some control signals in the flip-flop and counting chain, participating in the generation of the `dig_por` logic. The output of I28 is connected to the input of the inverter I34, which is used to further stabilize the reset signal. The input of the inverter I34 is connected to the output of the NAND gate I28, and the output of I34 is the final `dig_por` signal, which is used to reset the control output and provided to other circuits to ensure the stable reset of the system.

[0030] The por circuit consists of two parts: an analog reset circuit and a digital reset circuit. Based on the analog reset circuit, a delay is implemented by adding a digital reset circuit to ensure the reliability of the reset signal. The analog reset signal por and the digital reset signal dig_por jointly participate in the reset control of the system.

[0031] The analog reset circuit 101 is mainly composed of an RC circuit and a Schmitt trigger SMIT_POR. When the capacitor is charged to the flip voltage of the Schmitt trigger in the RC circuit, the output terminal Y of the Schmitt trigger is reversed, thereby generating a reset signal por. The rising flip voltage of the Schmitt trigger is 0.85VDD, and the falling flip voltage is 0.3VDD. It has a large hysteresis interval. This design can enhance the anti-interference ability of the reset signal, thereby ensuring that a stable reset signal is provided when the circuit is started. The input terminal A of the Schmitt trigger SMIT_POR is connected to the drain of the P-type metal oxide semiconductor PM24. When the capacitor is charged to a sufficient voltage, the trigger is reversed, and the output terminal Y is connected to the input terminal of the inverter INV_1p2_0p6 for transmitting a stable reset signal. Subsequently, the output of the inverter INV_1p2_0p6 is connected to the input terminal of the inverter INV_2p4_1p2. After being buffered by two stages of inverters, the reset signal por finally generated is used for other circuits to ensure the stability and reliability of the entire system.

[0032] The digital reset circuit 102 includes components such as a NAND gate, an inverter, a D flip-flop, a three-input NAND gate, and a four-input NAND gate. Its core function is to generate a delayed reset signal dig_por through logic counting based on the analog reset signal por to ensure the reliability of the reset action. The NAND gate nand2 receives the signals ad_osc_pwm and dig_por, and its output is connected to the input of the inverter INV_8P6_6P6 to invert the signal. Subsequently, the inverted signal is passed to the clock input CKB of the first D flip-flop Q1, and the signal is passed in sequence through the cascaded D flip-flops (Q2, Q3, Q4, Q5, Q6) to form a reliable counting chain. In the counting chain, the output of the D flip-flop Q3 is connected to the input of the inverter INV_6P6_6P6, which is used to invert the signal and pass it to the NAND gate I30, further participating in the generation of the reset logic. When the output signal of the last stage D flip-flop Q6 in the counting chain reaches a predetermined state, the three-input NAND gate I29 receives signals from Q6, Q5 and Q4, generates a logic control signal, and passes it to the four-input NAND gate I30. The output of I30 is connected to the inverter INV_8P6_6P7, and the inverted signal is used to drive the subsequent logic circuit to finally generate the digital reset signal dig_por. The NAND gate I28 receives some control signals in the counting chain, and its output is connected to the input of the inverter I34. After inversion, the final digital reset signal dig_por is generated to ensure that the system can be smoothly reset after the power is turned on. In the entire circuit, osc_pwm is a frequency generation module that generates a frequency value of 1MHz, drives the NAND gate nand2 and the subsequent counting chain, and ensures that the generation of the dig_por signal has a predetermined delay time. This design allows the reset signal to be fully stable after the circuit is powered on, avoiding the continuous flipping of the reset signal caused by the fluctuation of the frequency signal, thereby ensuring the reliability and anti-interference ability of the system startup.

[0033] The oscillator circuit includes: an osc_data unit and an osc_pwm unit, wherein the osc_data unit is used for data sampling to generate a frequency signal of 3.5MHz, and its enable signal EN_OSC is generated by a digital unit; the osc_pwm unit is used for power consumption control of the system, and when the system enters a zero power consumption state, the osc_pwm unit is turned off to reduce the power consumption of the system; when the system is in a normal working state, the osc_pwm unit is turned on to generate a corresponding PWM signal to control the brightness of each light-emitting diode chip and the signal modulation operation.

[0034] Specifically, the oscillator circuit is composed of a NOR gate NOR2BBBN_13_7_1, an inverter INVBNL_13_7D4_1, a P-type metal oxide semiconductor PM1, a P-type metal oxide semiconductor PM0, a NAND gate NAND2BN_13_7_1, a buffer BUFBN_13_7D4_1, a resistor R4, a resistor R0, a resistor R1, an N-type metal oxide semiconductor NM0, a Schmitt trigger SMTINVB_13_7_1, an inverter INVBN_13_7_1, an inverter INVBN_13_7D2_1, and a buffer BUFBN_13_7D4_1_1. The input terminal `A` of the NOR gate NOR2BBBN_13_7_1 is connected to the control signal `enn`, the input terminal `B` is connected to the ground (GND), and the output terminal `Y` is connected to the input terminal of the inverter INVBNL_13_7D4_1. The input terminal of the inverter INVBNL_13_7D4_1 is connected to the output terminal `Y` of NOR2BBBN_13_7_1, and the output terminal `Y` is connected to the gate of the P-type metal oxide semiconductor PM1, and is also connected to the input terminal `B` of the NAND gate NAND2BN_13_7_1. The source of the P-type metal oxide semiconductor PM1 is connected to the power supply `VDD`, and the drain is connected to the source of another P-type metal oxide semiconductor PM0 through a horizontal connection line, and is also connected to the input terminal `A` of the NAND gate NAND2BN_13_7_1, and the gate is connected to the output terminal of the inverter INVBNL_13_7D4_1. The source of the P-type metal oxide semiconductor PM0 is connected to the drain of PM1, and the drain is connected to the input terminal of the buffer BUFBN_13_7D4_1, and the gate is connected to the control signal through a connection line to control its conduction state. The input terminal `A` of the NAND gate NAND2BN_13_7_1 is connected to the drain of PM1, the input terminal `B` is connected to the output terminal of the inverter INVBNL_13_7D4_1, and the output terminal `Y` is connected to the input terminal of the buffer BUFBN_13_7D4_1. The input terminal of the buffer BUFBN_13_7D4_1 is connected to the output terminal `Y` of the NAND2BN_13_7_1, and the output terminal is connected to the resistor R4, and continues to be connected to the resistor network. One end of the resistor R4 is connected to the output terminal of the buffer BUFBN_13_7D4_1, and the other end is connected to one end of the resistor R0 to form a series connection. One end of the resistor R0 is connected to the resistor R4. The other end is connected to one end of the resistor R1 to continue to form a series connection. One end of the resistor R1 is connected to the resistor R0, and the other end is connected to the drain of the N-type metal oxide semiconductor NM0. The drain of the N-type metal oxide semiconductor NM0 is connected to the resistor R1, the source is connected to the ground (GND), forming a discharge path for the current, and the gate is connected to the output end of the buffer to control the on and off of NM0.The input terminal `A` of the Schmitt trigger SMTINVB_13_7_1 is connected to the common node of the resistor network and the NMOS, and the output terminal `Y` is connected to the input terminal of the inverter INVBN_13_7_1. The input terminal of the inverter INVBN_13_7_1 is connected to the output terminal `Y` of the Schmitt trigger SMTINVB_13_7_1, and the output terminal is connected to the input terminal of the inverter INVBN_13_7D2_1. The input terminal of the inverter INVBN_13_7D2_1 is connected to the output terminal of the inverter INVBN_13_7_1, and the output terminal is connected to the input terminal of the buffer BUFBN_13_7D4_1_1. The input terminal of the buffer BUFBN_13_7D4_1_1 is connected to the output terminal of the inverter INVBN_13_7D2_1, and the output terminal is marked as `osc_3p5M`, which is the final oscillator output signal, which is provided to other circuits for use.

[0035] Oscillator circuits are divided into two types: osc_data and osc_pwm, which are responsible for generating signals of different frequencies, which are used for data sampling and system power consumption control respectively. The osc_data oscillator is used to generate a 3.5MHz frequency signal, and its enable signal EN_OSC is generated by the digital unit. The osc_data oscillator will only start working when the signal t_start of the digital unit is high, thereby ensuring the reliability of signal sampling. The osc_data circuit generates frequency through an RC loop, and generates an oscillation signal by charging and discharging the capacitor. The charging and discharging processes control the rise and fall of the output frequency respectively. When the capacitor is charged to a certain voltage threshold, the Schmitt trigger SMTINVB_13_7_1 begins to flip, causing the oscillation output to change. Since the Schmitt trigger has a large hysteresis characteristic, the trigger voltages for rising and falling are different. This design enhances the frequency stability and anti-interference ability. The oscillation signal is shaped by the buffer and inverter chain (INVBN_13_7_1, INVBN_13_7D2_1, etc.), and is finally output by the buffer BUFBN_13_7D4_1_1, marked as osc_3p5M, and provided to other circuits as the final oscillation output signal. The enable signal of the osc_pwm oscillator is determined by the zero-power circuit. When the system enters the zero-power state, the osc_pwm oscillator will be turned off to reduce the power consumption of the system. When the system is in normal working state, the osc_pwm oscillator is turned on to generate the corresponding PWM signal for controlling LED brightness, signal modulation and other applications. The frequency of the osc_pwm circuit is also generated by the RC loop, and the rise and fall of the output frequency are controlled by charging and discharging the capacitor. The oscillator also has good PVT tolerance, and the deviation range is controlled within 50%, ensuring the stability of the system under different processes, temperatures and voltage changes. In the oscillator circuit, the input terminal A of the NOR gate NOR2BBBN_13_7_1 is connected to the control signal enn, and the input terminal B is connected to the ground (GND). When the control signal enn is low, the output of the NOR gate is high, driving the subsequent circuit. The inverter INVBNL_13_7D4_1 inverts the signal from NOR2BBBN_13_7_1, and its output is used to control the P-type metal oxide semiconductor PM1 and the NAND gate NAND2BN_13_7_1. PM1 and PM0 are cascaded to form a current path and control their on and off states at the same time. The two inputs of the NAND gate NAND2BN_13_7_1 come from PM1 and the inverter INVBNL_13_7D4_1 respectively. When the input conditions are met, the NAND gate outputs a low level to control the buffer BUFBN_13_7D4_1. The buffer BUFBN_13_7D4_1 shapes the signal from the NAND gate and the output is connected to the resistor network to form a stable RC oscillation structure.The resistor network is composed of R4, R0, and R1 in series, and is finally connected to the drain of the N-type metal oxide semiconductor NM0. The source of NM0 is grounded to form a discharge path for the current. Its gate is controlled by the output of the buffer to switch the path and ensure the normal operation of the RC loop. The Schmitt trigger SMTINVB_13_7_1 receives the signal from the RC network. Its rising and falling flip voltages are different, forming a hysteresis characteristic, thereby stabilizing the output. The output of the Schmitt trigger is shaped by multiple inverters (INVBN_13_7_1, INVBN_13_7D2_1) and buffers (BUFBN_13_7D4_1_1), and finally forms the oscillating output signal of osc_3p5M. osc_data and osc_pwm are controlled to be turned on and off by different enable signals, thereby realizing different functional requirements of the system. The enable signal of osc_data comes from the digital unit, which ensures good synchronization during data sampling; while osc_pwm is controlled by a low-power circuit, which turns off the oscillator when the system does not need to work, thereby reducing power consumption. The generation of the oscillation signal is based on an RC loop, and the hysteresis characteristics of the Schmitt trigger ensure the signal's anti-interference ability and frequency stability. The signal is shaped through different logic gates and inverters, and finally a stable oscillation signal is output and provided to other circuits for further processing or control.

[0036] The bias current circuit includes a plurality of P-type and N-type metal oxide semiconductor transistors and resistors, and controls and adjusts the bias current according to the control of the current mirror and the reference current generation strategy, generates a stable bias current for the light emitting diode driving circuit, and controls the brightness adjustment of each light emitting diode.

[0037] Specifically, the bias current circuit is composed of a P-type metal oxide semiconductor PM4, an N-type metal oxide semiconductor NM3, an N-type metal oxide semiconductor NM2, a P-type metal oxide semiconductor PM1, a P-type metal oxide semiconductor PM3, an N-type metal oxide semiconductor NM1, an N-type metal oxide semiconductor NM4, a resistor R1_56_4, and a resistor R2_18_8. The source of the P-type metal oxide semiconductor PM4 is connected to the power supply voltage `VDD`, the gate is connected to the control signal `enn`, which is used to control the conduction state of PM4, and the drain is connected to the node `vbp`, which is used to provide current for the startup circuit. The gate of the N-type metal oxide semiconductor NM3 is connected to the node `vbp`, which is used to control the conduction state of NM3, the drain is connected to the source of NM2, forming a series relationship, and the source is connected to the ground (GND) to provide a loop to return the current to the ground. The gate of the N-type metal oxide semiconductor NM2 is connected to the node `vbp`, the drain is connected to the common node of the main circuit, and the source is connected to the drain of NM3 to form a current path. The source of the P-type metal oxide semiconductor PM1 is connected to the power supply voltage `VDD`, the drain is connected to the drain of the N-type metal oxide semiconductor NM1, forming an initial current path of a current mirror structure, and the gate is connected to the gate of PM3 to ensure stable current control. The source of the P-type metal oxide semiconductor, PM3 is connected to the power supply voltage `VDD`, the drain is connected to the drain of the N-type metal oxide semiconductor NM4 to provide a bias current, and the gate is connected to the gate of PM1 to ensure that the currents of the two PMOS are proportional. The drain of the N-type metal oxide semiconductor, NM1 is connected to the drain of PM1 to form a bias current path, the gate is connected to the common node, and is used to form a current mirror with PM1, and the source is connected to the node between the resistors R1_56_4 and R2_18_8 to control the magnitude of the bias current. One end of the resistor R1_56_4 is connected to the source of NM1, and the other end is connected to the resistor R2_18_8 to form a voltage divider network to adjust the bias current. One end of the resistor R2_18_8 is connected to the resistor R1_56_4, and the other end is connected to the ground (GND) to form a voltage divider path. The gate of the N-type metal oxide semiconductor NM4 is connected to the node `vbp`, the drain is connected to the drain of PM3, which is used to stabilize the bias current, and the source is connected to the ground (GND) to provide a loop so that the current flows to the ground.

[0038] The bias current circuit is used to generate a stable bias current for the LED driver module and control the brightness adjustment of the LED. The circuit consists of multiple P-type and N-type metal oxide semiconductor transistors and resistors. The bias current is controlled and adjusted through the current mirror and reference current generation mechanism. The source of PM4 is connected to the power supply voltage VDD, and the gate is connected to the control signal enn, which is used to control the conduction state of PM4. The drain is connected to the node vbp, which is used to provide current for the startup circuit. In the initial state, the node vbp voltage is low, PM4 is turned on, and the current generated is used to put the circuit into working state. The gate of NM3 is connected to the node vbp, which is used to control the conduction state of NM3. The drain is connected to the source of NM2 to form a series relationship, and the source is connected to the ground (GND) to provide a current loop. In the startup stage, NM3 is cut off. When the vbp voltage rises to a sufficient level, NM3 is turned on, thereby closing the startup circuit and putting the circuit into a stable working state. The gate of NM2 is also connected to the node vbp, the drain is connected to the common node of the main circuit, and the startup current is provided for the bias current generating circuit. The source is connected to the drain of NM3 to form a current path. At startup, the vbp voltage rises, and NM2 is turned on to allow current to pass. The source of PM1 is connected to the power supply voltage VDD, and the drain is connected to the drain of NM1 to form an initial current path of a current mirror structure. The gate is connected to the gate of PM3 to ensure that the currents of the two PMOS are proportional. The source of PM3 is also connected to the power supply voltage VDD, the drain is connected to the drain of NM4 to provide a bias current, and the gate is connected to the gate of PM1 to ensure that their currents remain in a multiple relationship. The drain of NM1 is connected to the drain of PM1 to form a bias current path. The gate is connected to the common node to form a current mirror structure with PM1, and the source is connected to the node between resistors R1_56_4 and R2_18_8 to control the magnitude of the bias current. One end of R1_56_4 is connected to the source of NM1, and the other end is connected to resistor R2_18_8 to form a voltage divider network to adjust the bias current. One end of R2_18_8 is connected to R1_56_4, and the other end is connected to ground (GND) to form a voltage divider path. The gate of NM4 is connected to node vbp, the drain is connected to the drain of PM3, which is used to stabilize the bias current, and the source is connected to ground (GND) to provide a current loop to ensure that the current flows stably to the ground. This circuit is used to generate bias current and control the LED driver module. The led_pwm_in_r / g / b / w signal is generated by the digital unit by counting the osc_pwm signal. The maximum output current of the bias current (ibias) is 12mA. By adjusting the 8-bit time of the input signal, 256 PWM waveforms with different duty cycles can be generated, thereby adjusting the average output current and controlling the brightness level of the LED.The enable signal power_enn is determined by the zero power mode. When the system is in zero power mode, the bias current (ibias) will be turned off to reduce power consumption. In the bias current generation module, PM1 and PM2 ensure that the currents of I1 and I2 are equal, while PM3 and PM1 make I3 and I1 multiples. I2 flows through NM4, generating a voltage drop Vbp at its gate. The current flowing through R2 is the sum of I1 and I3, and the current flowing through R1 is I3, so the voltage balance relationship is satisfied: I3*R1+(I1+I3)*R2=Vbp. This relationship ensures the stable output of the bias current.

[0039] The light-emitting diode driving circuit is also used to convert the signal from the serial data input into parallel grayscale data for controlling the LED display. The serial data is input from the external DIN port and converted into parallel data through the data clock signal OSC_data_DIV_4. The generated parallel data is stored in the register to control the brightness change of each light-emitting diode chip. By comparing the PWM signal and the grayscale data, a system with a fixed DC voltage is obtained, and the current flows through the LED driver at a preset frequency. Assuming that the maximum current passing through the light-emitting diode chip is Imax and the off time of each cycle is t, the average current is calculated by the following duty cycle formula:

[0040] Id=Imax*Duty cycle,

[0041] Duty cycle = 100*((1 / (2^8))(2^7*B7+2^6*B6+2^5*B5+2^4*B4+2^3*B3+2^2*B2+2^1*B1+2^0*B0)), where B0, B1, B2, B3, B4, B5, B6 and B7 are the grayscale data displayed by the light-emitting diode chip.

[0042] According to the OSC_PWM counter, the maximum on and off time t of LED_LATCH is equal to OSC_PWM_DIV_256. By controlling the duty cycle of the PWM signal, the average current of each LED chip is accurately adjusted to achieve brightness control.

[0043] Specifically, the light emitting diode driving circuit is composed of a P-type metal oxide semiconductor M4, a P-type metal oxide semiconductor M1, an N-type metal oxide semiconductor NM30, an N-type metal oxide semiconductor NM31, an N-type metal oxide semiconductor NM7, an N-type metal oxide semiconductor NM8, an N-type metal oxide semiconductor NM9, an N-type metal oxide semiconductor NM10, an N-type metal oxide semiconductor NM11, an N-type metal oxide semiconductor NM12, an N-type metal oxide semiconductor NM13, an N-type metal oxide semiconductor NM14, an N-type metal oxide semiconductor NM15, an N-type metal oxide semiconductor NM16, an N-type metal oxide semiconductor M0, a P-type metal oxide semiconductor M3, an N-type metal oxide semiconductor NM35, an N-type metal oxide semiconductor NM33, a P-type metal oxide semiconductor PM0, a P-type metal oxide semiconductor M1, an N-type metal oxide semiconductor NM17, and an N-type metal oxide semiconductor NM18. The source of the P-type metal oxide semiconductor M4 is connected to the power supply voltage `VDD`, the gate is connected to the control signal, the specific source of the control signal is unknown, the drain is connected to the source of M1, and is also connected to the drain of the NMOS transistor NM30, providing a starting point for the bias current for the circuit. The source of the P-type metal oxide semiconductor M1 is connected to the drain of M4, the gate is connected to other control signals, which are used to control the conduction state of M1, and the drain is connected to the drain of NM31, which continues to pass the bias current to the next level circuit. The drain of the N-type metal oxide semiconductor NM30 is connected to the node between the source and drain of M4 and M1, the gate is connected to the control signal, which is used to adjust its conduction state, and the source is connected to the ground (GND) to provide a current loop. The drain of the N-type metal oxide semiconductor NM31 is connected to the drain of M1, the gate is connected to the PWM control signal, which is used to adjust the current flow, and the source is connected to the drain of the next level NMOS network as the control node of the current. The drain of N-type metal oxide semiconductor NM7 is connected to the source of NM31, the gate is connected to the control signal for switch control, and the source is connected to the drain of NM8 as one of the nodes for step-by-step transmission. The drain of N-type metal oxide semiconductor NM8 is connected to the source of NM7, the gate is connected to the control signal for step-by-step transmission of current, and the source is connected to the drain of NM9. The drain of N-type metal oxide semiconductor NM9 is connected to the source of NM8, the gate is connected to the control signal, and the source is connected to the drain of NM10. The drain of N-type metal oxide semiconductor NM10 is connected to the source of NM9, the gate is connected to the control signal, and the source is connected to the drain of NM11. The drain of N-type metal oxide semiconductor NM11 is connected to the source of NM10, the gate is connected to the control signal, and the source is connected to the drain of NM12. The drain of N-type metal oxide semiconductor NM12 is connected to the source of NM11, the gate is connected to the control signal, and the source is connected to the drain of NM13.The drain of N-type metal oxide semiconductor NM13 is connected to the source of NM12, the gate is connected to the bias current enable signal `ibiasen`, which is used to control the flow of bias current, and the source is connected to the drain of NM14. The drain of N-type metal oxide semiconductor NM14 is connected to the source of NM13, the gate is connected to the control signal `enn`, and the source is connected to the drain of NM15. The drain of N-type metal oxide semiconductor NM15 is connected to the source of NM14, the gate is connected to the control signal `enn`, and continues to transmit the control signal, and the source is connected to the drain of NM16. The drain of N-type metal oxide semiconductor NM16 is connected to the source of NM15, the gate is connected to the control signal `enn`, which controls the conduction state of NM16, and the source is connected to the drain of NMOS M0. The drain of N-type metal oxide semiconductor M0 is connected to the source of NM16, the gate is connected to the control signal for final switch control, and the source is connected to ground (GND) to provide a final return path for the current.

[0044] The digital circuit includes a data sampling circuit and a data conversion circuit, wherein the data sampling circuit is used to implement sampling of input data, recovery of clock signals, and generation of reset control signals synchronized with the input data, and the data sampling circuit includes a counter, a numerically controlled oscillator NCO, a differential frequency detector DFD, multiple logic gates, and multiple triggers; the data conversion circuit is used to convert serial data based on a microcontroller MCU into parallel data for driving a light-emitting diode chip. After a system power-on reset POR, the data conversion circuit receives data through a DIN port, controls its data conversion process based on multiple 32-bit input signals, and generates a signal for driving the light-emitting diode chip output.

[0045] Specifically, the data sampling circuit is composed of a counter COUNTER, a numerically controlled oscillator NCO, a differential frequency detector DFD, a sampling signal interface SAMPLING SIGNALS, a data input interface DIN, a start signal T_START, a D flip-flop 4021, a D flip-flop 4022, an inverter 4023, a NAND gate 4024, an AND gate 4025, a NAND gate 4026, a D flip-flop 4027, a NOR gate 4028, a NAND gate 4029, an SR latch 4020, a D flip-flop 40201, a three-input OR gate 40202, a NAND gate 40203, an inverter 40204, and an AND gate 40205. The sampling signal interface SAMPLING SIGNALS is connected to the counter COUNTER to provide a clock source or a trigger signal required for counting; the output of the counter COUNTER is connected to the numerically controlled oscillator NCO, and the numerically controlled oscillator adjusts the frequency of the output signal according to the count value and sends the signal to the differential frequency detector DFD. The differential frequency detector DFD simultaneously receives the output signal of the numerically controlled oscillator NCO and the signal of the data input interface DIN, and generates a synchronous start signal T_START by performing frequency detection or comparison on the two signals for subsequent operation or control of the system. The clock input terminal Clk of the D flip-flop 4021 is connected to the input signal OSC_DATA, the reset input terminal Reset is connected to the reset signal RST, and its output terminal Q generates the signal OSC_DATA_DIV2, and the inverting output terminal Generate signal OSC_DATA_DIV2_N. The clock input terminal Clk of D flip-flop 4022 is connected to the inverted output signal OSC_DATA_DIV2_N from D flip-flop 4021, and the reset input terminal Reset is also connected to the reset signal RST. The output terminal Q of D flip-flop 4022 generates signal OSC_DATA_DIV4. Therefore, D flip-flops 4021 and 4022 are cascaded through the inverted output signal OSC_DATA_DIV2_N to complete the step-by-step frequency division of the input signal. The input of inverter 4023 is connected to the system reset signal SYS_RST, and the output signal POR is connected to one input terminal of NAND gate 4024. The other input terminal of NAND gate 4024 receives the reset-related signal from other circuits, and the output is connected to one input terminal of NAND gate 4026. The two inputs of AND gate 4025 receive the clock signal OSC_DATA and the frequency division signal OSC_DATA_DIV_4 respectively, and its output is connected to the other input terminal of NAND gate 4026. The output of the NAND gate 4026 generates the final reset signal RESET. The overall logic realizes the logic control of the reset signal under different conditions through the combination of inverters, AND gates, NAND gates and NAND gates to generate the reset signal of the system. The input terminal D receives a fixed logic level signal, the clock input terminal Clk is connected to the clock signal OSC_DATA, and the reset input terminal Reset is connected to the reset signal RST. When the rising edge of the clock signal OSC_DATA arrives, the D flip-flop will pass the value of the input terminal D to the output terminal Q, thereby generating the output signal OSC_DATA_DIV2. When the reset signal RST is valid, the flip-flop will reset the output to the initial state. In addition, the inverting output terminal Generate an output signal OSC_DATA_DIV2_N to provide a logic state opposite to the Q output signal. The two inputs of the NOR gate 4028 receive the signals OSC_DATA_DIV2_N and OSC_DATA_N respectively, and the output signal OSC_DATA_DIV2 is passed to the input of the NAND gate 4029. After the NAND gate 4029 performs a NAND operation on the input signal, its output is passed to the SR latch 4020 as a control signal. The SR latch 4020 is composed of two cross-connected NAND gates, one of which receives a signal from the NAND gate 4029 and the other receives a reset signal BIT_RST. The output of the SR latch 4020 generates a latch signal SR_LATCH_Q to maintain or reset its state. The input D of the D flip-flop 40201 is connected to the signal DIN to provide input data to be stored. The clock input terminal Clk is connected to the signal OSC_DATA_DIV_4, marked as SP_CLK, which is used to control the D flip-flop to pass the input data to the output terminal at the rising edge or the falling edge. The reset input terminal Reset is connected to the reset signal BIT_RST, which is used to reset the state of the D flip-flop under the reset condition. When the trigger edge of the clock signal arrives, the D flip-flop passes the input value of the D terminal to the output terminal Q, and generates the output signal CODE_TRAC_SAMP_SDAT for the subsequent circuit. The three inputs of the three-input OR gate 40202 receive the signals SR_LATCH_Q (A), DIN (B) and CODE_TRAC_SAMP_SDAT (C) respectively, and generate the output signal by performing an "OR" operation on these signals and pass it to one input terminal of the NAND gate 40203. The other input terminal of the NAND gate 40203 receives the signal OSC_DATA_EN (D), and generates the output signal by performing a "NAND" operation on the two input signals and passes it to the inverter 40204. Inverter 40204 inverts the output signal of NAND gate 40203, generates signal GET_DATA and passes it to one input terminal of AND gate 40205. At the same time, the output signal of NAND gate 40203 is also directly connected to the other input terminal of AND gate 40205. AND gate 40205 performs an AND operation on the two input signals and finally generates an output signal DOUT.

[0046] The data sampling circuit contains multiple submodules and logic components, which are used to implement the sampling of input data, the recovery of clock signals, and the generation of reset control signals synchronized with the input data. The entire circuit consists of a counter, a numerically controlled oscillator (NCO), a differential frequency detector (DFD), and several logic gates and triggers. First, the input of the counter COUNTER is connected to the sampling signal interface SAMPLING SIGNALS to provide the clock source or trigger signal required for counting. The output of the counter is connected to the numerically controlled oscillator NCO to adjust the frequency of the output signal according to the count value. Subsequently, the NCO sends its output signal to the differential frequency detector DFD, and together with the signal from the data input interface DIN, the frequency is detected through the DFD to generate a synchronized start signal T_START. In order to effectively synchronize with the input data, D flip-flops 4021 and D flip-flops 4022 are used to achieve frequency division. The clock input Clk of the D flip-flop 4021 is connected to the input signal OSC_DATA, the reset input Reset is connected to the reset signal RST, the output Q generates the signal OSC_DATA_DIV2, and the inverting output Generate signal OSC_DATA_DIV2_N. Subsequently, the clock input terminal Clk of the D flip-flop 4022 is connected to the inverted output signal OSC_DATA_DIV2_N from the D flip-flop 4021, and the reset input terminal is also connected to the reset signal RST, and the output terminal generates the signal OSC_DATA_DIV4. In this way, the two flip-flops gradually realize the frequency division operation of the input signal. The system reset signal realizes combinational logic control through multiple logic components. First, the inverter 4023 inverts the system reset signal SYS_RST, and the output signal POR is connected to one input terminal of the NAND gate 4024. The other input terminal of the NAND gate receives the reset signal of other circuits, and the output is connected to one input terminal of the NAND gate 4026. The two inputs of the AND gate 4025 are respectively connected to the clock signal OSC_DATA and the frequency division signal OSC_DATA_DIV_4, and the output signal is connected to the other input terminal of the NAND gate 4026. The output of the NAND gate 4026 finally generates a reset signal RESET, which is used to reset the system. In order to realize the sampling and holding of input data, the input terminal D of D flip-flop 40201 receives the input signal DIN, and the clock input terminal Clk is connected to the frequency division signal OSC_DATA_DIV_4 to control the transmission of data. The reset input terminal Reset is connected to the reset signal BIT_RST, so that the flip-flop can reset the state under the reset condition. When the rising edge of the clock signal arrives, the flip-flop transfers the signal at the input terminal to the output terminal, and generates the CODE_TRAC_SAMP_SDAT signal for subsequent logic. The three input terminals of the three-input OR gate 40202 receive the signals SR_LATCH_Q (A), DIN (B) and CODE_TRAC_SAMP_SDAT (C) respectively, and generate the output signal through the "OR" operation, which is passed to one input terminal of the NAND gate 40203. The other input terminal of the NAND gate receives the signal OSC_DATA_EN (D), and the generated output signal is inverted by the inverter 40204 to form the signal GET_DATA, which is passed to one input terminal of the AND gate 40205. At the same time, the output of the NAND gate is also directly connected to the other input of the AND gate, and the output signal DOUT is finally generated after the "AND" operation. After the system power-on reset (POR), the data is input and sampled through the DIN interface. During the data sampling and clock recovery process, the differential frequency detector (DFD) and the numerically controlled oscillator (NCO) work together to ensure that the sampled clock is synchronized with the data. The signal OSC_DATA_EN is used as a key control signal for managing the system reset and data shaping signals. The entire system realizes the data sampling, frequency division and reset control functions through a combination of multi-level triggers and logic gates to ensure the stable operation of the system and correct data acquisition and processing.

[0047] The data conversion circuit is composed of an inverter 40301, a NAND gate 40302, a D flip-flop 40303, a D flip-flop 40304, a D flip-flop 40305, an AND gate 40306, a D flip-flop 40307, ​​an inverter 40308, an AND gate 40309, a D flip-flop 40310, an inverter 40311, and an AND gate 40312. The inverter 40301 receives the signal OSC_PWM_DIV_5 (31.25kHz) and performs an inversion process on it, and the output is used as the clock input of the D flip-flop 40303. The two inputs of the NAND gate 40302 receive the signal DIN and the reset signal POR respectively, and its output is connected to the D input terminal of the D flip-flop 40303 to control the data stored therein. The output terminal Q of the D flip-flop 40303 is connected to the D input terminal of the D flip-flop 40304, and the output terminal Q of the D flip-flop 40304 is connected to the D input terminal of the D flip-flop 40305, forming a cascade connection. The output signal A1 of the D flip-flop 40305 and the output signal A of the D flip-flop 40304 enter the AND gate 40306 together, and the output of the AND gate 40306 is connected to the D input of the D flip-flop 40307. The clock input of the D flip-flop 40307 is connected to the output of the AND gate 40306, and finally the output signal of the D flip-flop 40307 is the system reset signal SYS_RST. The entire circuit realizes the step-by-step conversion of data and the generation of the system reset signal through the combination of cascaded D flip-flops and logic gates. The input of the inverter 40308 receives the reset signal POR, and the output generates the system reset signal SYS_RST and passes it to one input of the AND gate 40309. The other input of the AND gate 40309 receives the clock signal CLK, and its output is connected to the clock input of the D flip-flop 40310. The D input of the D flip-flop 40310 receives the signal VDD for providing a logic high level. The output Q of the flip-flop generates the signal GET_DATA and passes it to the input of the inverter 40311. Inverter 40311 inverts the signal GET_DATA to generate a signal and passes it to one input end of AND gate 40312. At the same time, the other input end of AND gate 40312 receives the system reset signal SYS_RST. AND gate 40312 performs an AND operation on the two input signals and finally generates an output signal GET_DATA_EN. The overall circuit realizes the logic generation of data control and enable signals through the combination of reset signals, clock signals and logic gates.

[0048] The data conversion circuit is one of the most important parts in digital signal processing. It converts serial data based on the microcontroller (MCU) into parallel data for driving LEDs. After the system power-on reset (POR), the chip receives data through the DIN port. Each chip controls its data conversion process based on multiple 32-bit input signals and generates signals for driving LED outputs. The signal GET_DATA_EN within the circuit is very important, which ensures the synchronization and correctness of data acquisition and conversion. The data conversion circuit 403 consists of multiple logic components and D flip-flops. First, the inverter 40301 receives the signal OSC_PWM_DIV_5 (31.25kHz), inverts it, and outputs it as the clock input of the D flip-flop 40303. Next, the two inputs of the NAND gate 40302 receive the signal DIN and the reset signal POR respectively, and its output is connected to the input of the D flip-flop 40303 for controlling the stored data. The output of the D flip-flop 40303 is cascaded with the D flip-flop 40304, and then connected to the D flip-flop 40305, forming a cascade connection structure in sequence for step-by-step data conversion. Through the cascade connection, the output signal A1 (generated by the D flip-flop 40305) and the signal A (generated by the D flip-flop 40304) enter the AND gate 40306 together, and the output of the AND gate is connected to the input of the D flip-flop 40307. The D flip-flop 40307 receives the signal from the AND gate as its clock input, and outputs the signal SYS_RST as the reset signal of the system. The entire circuit realizes the step-by-step conversion of data and the generation of reset signals through the combination of cascaded D flip-flops and logic gates. The circuit also includes an inverter 40308, whose input receives the reset signal POR, and whose output generates the system reset signal SYS_RST, which is passed to one input of the AND gate 40309. The other input of the AND gate 40309 receives the clock signal CLK, and its output is connected to the clock input of the D flip-flop 40310. The input terminal D of the D flip-flop 40310 receives the signal VDD for providing a logic high level, and the output terminal Q generates the signal GET_DATA and passes it to the inverter 40311. Inverter 40311 inverts the signal GET_DATA, generates a new control signal and passes it to one input of AND gate 40312. At the same time, the other input of AND gate 40312 receives the system reset signal SYS_RST. By performing an AND operation on the two input signals, AND gate 40312 finally generates the signal GET_DATA_EN for subsequent data control and enable logic. During the data conversion process, the serial data input DIN is transmitted to each level of logic units in the circuit through the data bus. The goal of the system is to convert serial data into a parallel data format. To achieve this process, multiple D flip-flops and logic gates are used. The entire conversion process ensures the sampling, storage and synchronization of data with the system clock, thereby generating a parallel signal to control the LED output.The signal GET_DATA_EN is used to control the first chip data extracted from the serial data to ensure the synchronization and reliability of the data on the conversion line. The circuit manages the data conversion process based on the OSC_PWM clock signal to ensure the correct acquisition of the serial data DIN, and converts it into 8-bit parallel data through the shift register, thereby controlling the brightness level (0 to 255) of each LED channel.

[0049] The LED drive output control circuit is composed of D flip-flop 40401, D flip-flop 40402, D flip-flop 40403, D flip-flop 40404, D flip-flop 40405, D flip-flop 40406, D flip-flop 40407, and D flip-flop 40408. The input terminal D of D flip-flop 40401 is connected to the parallel data input signal PARALLEL_DATA <0> , the clock input Clk is connected to the clock signal CLOCK, the reset input Reset is connected to the reset signal POR, and the output Q generates the signal GS_DATA <0> , represents the sampling result of the 0th bit of the parallel input data. The input terminal D of the D flip-flop 40402 is connected to the parallel data input signal PARALLEL_DATA <1> , the clock input Clk is also connected to CLOCK, the reset input is connected to POR, and the output Q generates the signal GS_DATA <1> , indicating the sampling result of bit 1. By analogy, D flip-flops 40403 to 40408 receive PARALLEL_DATA <2> to PARALLEL_DATA <7> The clock input of each flip-flop is connected to the common clock signal CLOCK, the reset input is connected to the reset signal POR, and their output terminals Q generate signals GS_DATA respectively. <2> to GS_DATA <7> , representing the sampling results of the respective input data bits. Therefore, these flip-flops realize bit-by-bit sampling and latching of 8-bit parallel input data under the control of the clock signal, and pass the results to the next level circuit through the output signal GS_DATA.

[0050] The grayscale data conversion and comparison process consists of three modules: grayscale data counter GS_DATA_COUNTER, grayscale data counting memory GS_DATA_COUNTER_STORE, and PWM and grayscale array comparator PWM, GRAY SCALE ARRAYCOMPARISON. First, the grayscale data counter GS_DATA_COUNTER receives 8-bit parallel input data PARALLEL_DATA<7:0>, the selection signal LED_8-BIT_SELECT (CLK), and the reset signal POR (RESET), generates grayscale data output GS_DATA<7:0>, and passes it to the grayscale data counting memory GS_DATA_COUNTER_STORE. The grayscale data counting memory GS_DATA_COUNTER_STORE receives grayscale data GS_DATA<7:0> and the system reset signal SYS_RST (CLK), stores and outputs grayscale data as GS_DATA_ARRAY<7:0> and its inverted form GS_DATA_ARRAY_INV<7:0>. Subsequently, these output signals are passed to the PWM and grayscale array comparator PWM, GRAY SCALE ARRAYCOMPARISON module, which also receives multiple PWM frequency division signals (such as OSC_PWM_DIV_2, OSC_PWM_DIV_4, etc.), and finally generates the latch signal LED_LATCH for controlling the LED state by comparing the grayscale data and the PWM signal. The entire circuit realizes the grayscale counting, storage and PWM signal comparison of parallel input data to accurately control the brightness state of the LED.

[0051] The LED driver output control circuit is used to convert the signal from the serial data input into parallel grayscale data for controlling the LED display. The serial data is input from the external DIN port and converted into parallel data through the data clock signal OSC_data_DIV_4. The generated parallel data is stored in the register and used to control the brightness change of the LED. The parallel data is converted into grayscale data through eight D flip-flop circuits. The 8-bit data input DIN of each LED channel is converted by a clock signal connected to the respective 8-bit selection signal (such as RED_8-BIT_SELECT, GREEN_8-BIT_SELECT, BLUE_8-BIT_SELECT, and WHITE_8-BIT_SELECT). The parallel data signal is sampled on the rising edge of the clock signal and regarded as grayscale data. This enables the eight D flip-flops to generate 8-bit output data and represent the decimal of the input data from 0 to 255 as grayscale data. GS_DATA (grayscale data) is stored in the eight D flip-flop logic circuits as a grayscale array, and each flip-flop is responsible for the brightness control of one LED channel. The 4-channel LED driver chip contains four independent LED channels of LED driver output data lines, each data line is connected to the corresponding 8-BIT selection signal. The output of these data lines is latched as the signal LED_LATCH, which represents the grayscale state of the respective 8-bit DIN serial data. The entire grayscale data is sampled by the synchronous clock and latched in the output data to ensure the stable operation of the system. Next, the grayscale data is compared with the internally generated OSC_PWM signal to achieve precise control of the LED brightness. The PWM signal is divided into eight different frequency values, namely OSC_PWM_DIV_2, OSC_PWM_DIV_4, etc. The 8-bit grayscale data and its inverted value are compared with these eight different frequency PWM signals, and the LED on and off state is controlled by the comparison result. The comparison process is implemented through different levels of logic gate circuits to ensure that the grayscale data can be correctly matched with the PWM signal, thereby achieving precise brightness control. In order to prevent high-power interference caused by LED switching and reduce power supply voltage fluctuations, the system is designed with an interleaved output delay mechanism so that each LED channel works in a constant interval sequence. This mechanism plays an important role in improving the circuit's anti-interference ability. According to the 8-bit brightness level encoded data, the LED display has 2^8 gray levels. The LED driver needs to switch repeatedly 2^8 times and latch the gray data 2^8 times.

[0052] Duty cycle=100*((1 / (2^8))(2^7*B7+2^6*B6+2^5*B5+2^4*B4+2^3*B3+2^2*B2+2^1*B1+2^0*B0)),

[0053] By comparing the PWM signal and the grayscale data, a system with a fixed DC voltage can be obtained, and the current flows through the LED driver at a certain frequency. Assuming that the maximum current of the LED is Imax and the off time of each cycle is t, the average current can be calculated by the above duty cycle formula:

[0054] Id=Imax*Duty cycle,

[0055] According to the OSC_PWM counter, the maximum on and off time t of LED_LATCH is equal to OSC_PWM_DIV_256. In this way, the average current of each LED can be accurately adjusted through the duty cycle control of the PWM signal, thereby realizing brightness control.

[0056] The power management circuit is used to ensure that the power is turned off when all zero data or no data is input by analyzing the state of the previous data and the next data in the power management signal. Specifically, the power management circuit realizes the transmission of the reset signal, the logic control and the generation of the final enable signal through the cooperation of the combination logic gate and the trigger, and controls the switching state of the bias current circuit and the oscillator circuit of the whole system by analyzing the serial input data DIN;

[0057] Among them, the serial input data DIN includes the following four cases:

[0058] The serial input data DIN is 32 bits of all-zero data, and the next data after reset is non-zero 32 bits of data;

[0059] The serial input data DIN is non-all-zero 32-bit data, and the next data after reset is non-zero 32-bit data;

[0060] The serial input data DIN is 32 bits of all-zero data, and no data arrives after reset;

[0061] The serial input data DIN is non-all-zero 32-bit data, and no data arrives after reset.

[0062] Specifically, the power management circuit is composed of an inverter 40501, a NAND gate 40502, a D flip-flop 40503, an AND gate 40504, an inverter 40505, an inverter 40506, a NAND gate 40507, a D flip-flop 40508, and an AND gate 40509. Inverter 40501 receives the DATA_RST signal and inverts it, and the output is connected to one input end of the NAND gate 40502, and the other input end receives the reset signal POR. The output of the NAND gate 40502 is used as the clock input of the D flip-flop 40503. The D input of the D flip-flop 40503 is connected to VDD, Reset is connected to the reset signal POR, and the output end Q generates a signal A for controlling subsequent logical operations. Then, the signal A and POR are input to the AND gate 40504 together, and the generated output passes through the inverter 40505, and the final output signal is POWER_CIRL (PREVIOUS 32-BIT INFORMATION). In the lower part, inverter 40506 receives the SYS_RST signal and inverts it. The output is connected to one input of NAND gate 40507, and the other input receives the reset signal POR. The output of NAND gate 40507 is used as the clock input of D flip-flop 40508. The D input of D flip-flop 40508 is connected to VDD, Reset is connected to the reset signal POR, and the output Q generates signal B for controlling subsequent logic operations. Finally, signal B and POWER_CIRL are input to AND gate 40509 together, and the generated output signal is POWER_EN. The entire circuit realizes the transmission of reset signals, logic control, and the generation of enable signals through the cooperation of combinational logic gates and flip-flops.

[0063] The power management of the single-line return-to-zero code LED driver control chip circuit of the present application is mainly used to effectively control power consumption and avoid wasting unnecessary current when it is not needed. Especially in some cases, when the chip does not receive valid input data, but other circuits in the system are still running, this may cause power consumption waste. In order to solve these problems, the power management circuit controls the switching state of the bias current circuit and oscillator circuit of the entire system by analyzing the serial input data DIN.

[0064] Four cases of DIN input

[0065] There are four possible situations at the serial data input terminal DIN:

[0066] The serial input data DIN is 32 bits of all-zero data, and the next data after reset is non-zero 32 bits of data.

[0067] The serial input data DIN is non-all-zero 32-bit data, and the next data after reset is non-zero 32-bit data.

[0068] The serial input data DIN is 32 bits of all-zero data, and no data arrives after reset.

[0069] The serial input data DIN is non-all-zero 32-bit data, and no data arrives after reset.

[0070] In the above four cases, especially the case of all-zero 32-bit data, or the case where no data arrives after reset, the LED will not light up, but analog blocks such as current bias and OSC will still consume a lot of power. Therefore, the purpose of the power management circuit is to decide whether to turn off these power-consuming circuits through the data input by DIN, so as to effectively manage the power consumption of the system. The power management signal POWER_EN of the power management circuit is determined by the information of the previous and next serial input data. The system will compare the previous data (32 bits of chip-1 before reset) with the next data (32 bits of chip-2 after reset) and generate the power management signal through the NOR logic. Specifically, the power management signal controls whether the system turns on or off the power consumption circuit by identifying whether the serial input data is all zero.

[0071] When the serial input DIN is non-all-zero data, the data line output signal A must be high; when the input is all-zero data, the output is low. To achieve this condition, the circuit relies on the number of 1 codes and 0 codes in the input signal and generates an output signal at the rising edge. The signal CODE_TRAC_SAMP_SDAT is used to represent this data information, so that the serial input DIN can correctly identify 1 codes and 0 codes in the 32-bit data of the red channel. Signal B represents the next input data information. To achieve this condition, the DIN input signal is directly used as a clock signal so that at the rising edge of the first code chip of the DIN data, signal B becomes high. This means that whether the next data is valid can be judged by B. Since synchronization is a key issue in the circuit, signals A and B need to be reset to ensure that the power management signal line POWER_EN can work properly. Because signal B relies on the rising edge of the first code chip of DIN, the system uses the SYS_RST signal as a reset signal to ensure the synchronization of the signal. The SYS_RST signal is used to control the reset of A and B so that the reset signal can be correctly activated before comparing the previous and next input data. After SYS_RST, if new data is detected to have arrived, the system will activate the power management signal line to turn all power consumption circuits back on. In the process of generating the 8-bit selection signal, OSC_DATA_DIV_4_N is used as a reset signal. This signal triggers a reset at a low level to ensure the synchronism of the data input, and minimizes the delay through a stable buffer circuit to ensure the stability of the reset signal. The POR signal (power-on reset) is an important signal line used to prepare the chip after the system reaches a stable power state. There will be no activity in the system until the POR signal becomes a low level, and once the condition is met, the externally provided DIN input signal will become a valid state. In order not to interrupt the operation of the system, the POWER_EN signal actively controls these power consumption circuits after POR to ensure that the system is in energy-saving mode. When signal A represents the first 32 bits of input data and signal B represents the next 32 bits of input data, by comparing A and B, the POWER_EN signal can be generated synchronously to control the power consumption circuits in the system. For example, when the previous data is all zero and the next data is non-zero, after SYS_RST, all power circuits are turned off and wait for new data to arrive before being re-awakened; when the current and next data are all zero, the system will continue to remain off; and when the data is not all zero, the system will continue to work normally. The above mechanism ensures that the 4-channel LED driver chip can turn off unnecessary power circuits when there is no valid data input, effectively reducing system power consumption, and ensures normal operation when there is data input, driving and enabling the corresponding LED channels.

[0072] In the present application, each preferred scheme only focuses on describing the differences from other preferred schemes. As long as the preferred schemes do not conflict, they can be combined arbitrarily. The embodiments formed by the combination are also within the scope disclosed in this specification. Considering the simplicity of the text, this article will no longer separately describe the embodiments formed by the combination.

[0073] The above is only an embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the scope of the claims of the present application.

[0074] In this document, each preferred scheme only focuses on describing the differences from other preferred schemes. As long as the preferred schemes do not conflict, they can be combined arbitrarily. The embodiments formed by the combination are also within the scope disclosed in this specification. Considering the simplicity of the text, this document will no longer separately describe the embodiments formed by the combination.

[0075] The above is only an embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the scope of the claims of the present application.

Claims

1. A single-line return-to-zero code LED drive control chip circuit, It is characterized in that The system comprises: a power management circuit, a startup reset circuit, an oscillator circuit, a bias current circuit, a digital circuit and a light emitting diode driving circuit, wherein the light emitting diode driving circuit comprises a driving channel of a white light emitting diode chip, a driving channel of a red light emitting diode chip, a driving channel of a green light emitting diode chip and a driving channel of a blue light emitting diode chip, wherein the power management circuit is used to ensure that the power is turned off when all zero data or no data is input by analyzing the state of the previous data and the next data in the power management signal; the startup reset circuit is used to generate a reset signal after the system is powered on, and transmit the reset signal to the oscillator circuit, the bias current circuit and the digital circuit, so as to ensure that all The circuit is used to start synchronously and complete the operation of entering a stable working state; the oscillator circuit is used to send the generated system clock signal to the digital circuit and the light-emitting diode drive circuit, drive the timing control of the subsequent logic, and ensure the synchronization of data processing and control of each light-emitting diode chip; the bias current circuit is used to provide a stable bias current for each light-emitting diode drive circuit, ensure that a consistent current input can be obtained under different working conditions, and ensure the stability of the brightness of each light-emitting diode chip; the digital circuit is used to receive input data and process it, and pass the generated control signal to the light-emitting diode drive circuit to adjust the brightness of each light-emitting diode chip and the control of color output.

2. The single-line return-to-zero code LED drive control chip circuit according to claim 1, characterized in that: The power management circuit is used to ensure that the power is turned off when all zero data or no data is input by analyzing the state of the previous data and the next data in the power management signal. Specifically, the power management circuit realizes the transmission of the reset signal, the logic control and the generation of the final enable signal through the cooperation of the combination logic gate and the trigger, and controls the switching state of the bias current circuit and the oscillator circuit of the whole system by analyzing the serial input data DIN; Among them, the serial input data DIN includes the following four cases: The serial input data DIN is 32 bits of all-zero data, and the next data after reset is non-zero 32 bits of data; The serial input data DIN is non-all-zero 32-bit data, and the next data after reset is non-zero 32-bit data; The serial input data DIN is 32 bits of all-zero data, and no data arrives after reset; The serial input data DIN is non-all-zero 32-bit data, and no data arrives after reset.

3. The single-line return-to-zero code LED drive control chip circuit according to claim 2, characterized in that: It also includes: the startup reset circuit includes an analog reset circuit and a digital reset circuit, the analog reset circuit is used to output an analog reset signal to achieve system reset control; the digital reset circuit is used to output a digital reset signal to achieve a delay, ensure the output of a reliable reset signal, and achieve system reset control.

4. The single-line return-to-zero code LED drive control chip circuit according to claim 3, characterized in that: It also includes: the oscillator circuit includes: an osc_data unit and an osc_pwm unit, wherein the osc_data unit is used for data sampling to generate a 3.5MHz frequency signal, and its enable signal EN_OSC is generated by a digital unit; the osc_pwm unit is used for power consumption control of the system, when the system enters a zero power consumption state, the osc_pwm unit is turned off to reduce the power consumption of the system; when the system is in a normal working state, the osc_pwm unit is turned on to generate a corresponding PWM signal to control the brightness of each light-emitting diode chip and the signal modulation operation.

5. The single-line return-to-zero code LED drive control chip circuit according to claim 4, characterized in that: It also includes: the bias current circuit includes multiple P-type and N-type metal oxide semiconductor transistors and resistors, and controls and adjusts the bias current according to the control of the current mirror and the reference current generation strategy, generates a stable bias current for the light-emitting diode drive circuit, and controls the brightness adjustment of each light-emitting diode.

6. The single-line return-to-zero code LED drive control chip circuit according to claim 5, characterized in that: It also includes: the light-emitting diode drive circuit is also used to convert the signal from the serial data input into parallel grayscale data for controlling the LED display, the serial data is input from the external DIN port, and is converted into parallel data through the data clock signal OSC_data_DIV_4, and the generated parallel data is stored in the register to control the brightness change of each light-emitting diode chip, wherein by comparing the PWM signal and the grayscale data, a system with a fixed DC voltage is obtained, and the current flows through the LED driver at a preset frequency. Assuming that the maximum current passing through the light-emitting diode chip is Imax, and the off time of each cycle is t, the average current is calculated by the following duty cycle formula: Id=Imax*Duty cycle, Duty cycle = 100*((1 / (2^8))(2^7*B7+2^6*B6+2^5*B5+2^4*B4+2^3*B3+2^2*B2+2^1*B1+2^0*B0)), where B0, B1, B2, B3, B4, B5, B6 and B7 are the grayscale data displayed by the light-emitting diode chip. According to the OSC_PWM counter, the maximum on and off time t of LED_LATCH is equal to OSC_PWM_DIV_256. By controlling the duty cycle of the PWM signal, the average current of each LED chip is accurately adjusted to achieve brightness control.

7. The single-line return-to-zero code LED drive control chip circuit according to claim 6, characterized in that: It also includes: the digital circuit includes a data sampling circuit and a data conversion circuit, wherein the data sampling circuit is used to implement sampling of input data, recovery of clock signals, and generation of reset control signals synchronized with the input data, and the data sampling circuit includes a counter, a numerically controlled oscillator NCO, a differential frequency detector DFD, multiple logic gates and multiple triggers; the data conversion circuit is used to convert serial data based on the microcontroller MCU into parallel data for driving the light-emitting diode chip, after the system power-on reset POR, the data conversion circuit receives data through the DIN port, controls its data conversion process based on multiple 32-bit input signals, and generates a signal for driving the light-emitting diode chip output.

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