Semiconductor static memory and preparation method thereof

Abstract

The invention discloses a semiconductor static memory and a preparation method thereof, and relates to the field of semiconductors. The semiconductor static memory comprises a substrate, and an embedded power rail and a complementary field effect transistor which are arranged on the substrate; the first embedded power rail and the second embedded power rail are arranged at the two ends of the substrate in parallel; the first complementary field effect transistor is obtained by sequentially stacking a first pull-down transistor and a first pull-up transistor from bottom to top; the second complementary field effect transistor is obtained by sequentially stacking a first transmission transistor and a second transmission transistor from bottom to top; the first transmission transistor and the second transmission transistor are n-type; and the third complementary field effect transistor is obtained by sequentially stacking a second pull-down transistor and a second pull-up transistor from bottom to top. According to the invention, the area of the standard cell can be reduced, and the integration level of the SRAM is improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductors, and in particular to a semiconductor static memory and a preparation method thereof. Background Art

[0002] As integrated circuits continue to develop, the method of maintaining Moore's Law by continuously shrinking transistor size faces severe challenges such as reduced gate control capability and quantum confinement effects. Complementary Field Effect Transistors (CFETs) achieve a huge increase in integration by vertically stacking two transistors, thereby continuing Moore's Law.

[0003] Static Random Access Memory (SRAM) is widely used in mobile phones, computers, wearable devices, automotive electronics and other fields due to its advantages such as fast speed, no need for refresh, and low power consumption, and its share in the overall chip area is increasing.

[0004] For the existing 6T SRAM standard cell, the two n-type PG devices make the 6T SRAM as a whole not an N / P complementary metal oxide semiconductor (CMOS) structure, so the two cross-coupled inverters of the SRAM can only be implemented by two CFET structures, and the two PG devices are implemented by the top or bottom devices of the two CFET structures, and the unused devices in the two CFETs need to be removed or invalidated to not affect the normal use of the PG devices. Therefore, the existing 6T SRAM layout occupies the layout area of ​​4 CFETs as a whole, and it is impossible to reduce the area of ​​the standard cell. Summary of the invention

[0005] The purpose of the present application is to provide a semiconductor static memory and a preparation method thereof, which can reduce the area of ​​a standard unit and improve the integration of SRAM.

[0006] To achieve the above objectives, this application provides the following solutions:

[0007] In a first aspect, the present application provides a semiconductor static memory, comprising: a substrate, and an embedded power rail and a complementary field effect transistor arranged on the substrate;

[0008] The embedded power rail comprises a first embedded power rail and a second embedded power rail;

[0009] The first buried power rail and the second buried power rail are arranged in parallel at two ends of the substrate; one end of the complementary field effect transistor is connected to the first buried power rail; the other end of the complementary field effect transistor is connected to the second buried power rail;

[0010] The complementary field effect transistors include: a first complementary field effect transistor, a second complementary field effect transistor and a third complementary field effect transistor which are arranged at intervals;

[0011] The first complementary field effect transistor is obtained by stacking a first pull-down transistor and a first pull-up transistor in sequence from bottom to top;

[0012] The second complementary field effect transistor is obtained by stacking the first transmission transistor and the second transmission transistor in sequence from bottom to top; the first transmission transistor and the second transmission transistor are both of n-type;

[0013] The third complementary field effect transistor is obtained by stacking the second pull-down transistor and the second pull-up transistor in sequence from bottom to top.

[0014] Optionally, the semiconductor static memory further comprises: a metal connection line;

[0015] The metal connection line includes: a bottom metal line and a top metal line;

[0016] The gate of the first complementary field effect transistor adopts the bottom metal line and is respectively connected to the bottom drain of the second complementary field effect transistor and the drain of the third complementary field effect transistor; the bottom drain of the second complementary field effect transistor is the drain of the first transfer transistor; the drain of the third complementary field effect transistor is a common drain structure determined by the drain of the second pull-down transistor and the drain of the second pull-up transistor; the gate of the first complementary field effect transistor is a common gate structure determined by the gate of the first pull-down transistor and the gate of the first pull-up transistor;

[0017] The drain of the first complementary field effect transistor adopts the top metal line and is respectively connected to the top source of the second complementary field effect transistor and the gate of the third complementary field effect transistor; the top source of the second complementary field effect transistor is the source of the second transfer transistor; the gate of the third complementary field effect transistor is a common gate structure determined by the gate of the second pull-down transistor and the gate of the second pull-up transistor.

[0018] Optionally, the semiconductor static memory further comprises: a buried power rail through hole;

[0019] The buried power rail via is in contact with the buried power rail interconnect;

[0020] The buried power rail through hole comprises: a bottom through hole, a middle through hole and a top through hole;

[0021] The bottom metal line connects the bottom source of the first complementary field effect transistor and the bottom through hole; the bottom source of the first complementary field effect transistor is the source of the first pull-down transistor;

[0022] The middle through hole connects the top drain of the first complementary field effect transistor and the bottom drain of the first complementary field effect transistor to form a common drain structure; the middle through hole is also connected to the bottom metal line; the top drain of the first complementary field effect transistor is the drain of the first pull-up transistor; the bottom drain of the first complementary field effect transistor is the drain of the first pull-down transistor;

[0023] The top through-hole is respectively connected to the top drain of the second complementary field effect transistor and the top source of the first complementary field effect transistor; the top through-hole is also respectively connected to the middle through-hole and the bottom metal line to form an interconnection structure; the top source of the first complementary field effect transistor is the source of the first pull-up transistor.

[0024] Optionally, the material of the buried power rail through hole is tungsten or ruthenium.

[0025] In a second aspect, the present application provides a method for preparing a semiconductor static memory, wherein the method for preparing a semiconductor static memory is used to prepare the semiconductor static memory described above, and the method for preparing a semiconductor static memory comprises:

[0026] Alternately epitaxially growing silicon germanium and silicon on a substrate to obtain a silicon germanium stacked structure;

[0027] Using self-aligned double imaging technology, etching downward from the top surface of the silicon germanium stack structure to a set position inside the substrate based on a set interval to obtain a fin-type structure; the fin-type structure includes: a groove area and a convex area;

[0028] Performing photolithography deposition processing based on the fin-shaped structure to obtain a buried power rail structure; the buried power rail structure includes: a substrate, an buried power rail and a fin-shaped structure after photolithography processing; the buried power rail includes a first buried power rail and a second buried power rail; the first buried power rail and the second buried power rail are arranged in parallel at two ends of the substrate;

[0029] By using etching and deposition processes, a virtual gate pattern with a set thickness is deposited on the buried power rail structure perpendicular to the raised area to obtain a virtual gate structure; the virtual gate pattern extends from the top to the bottom of the raised area;

[0030] In a direction perpendicular to the raised area, depositing material on both sides of the virtual gate structure using a deposition process to obtain an outer sidewall;

[0031] Taking the outer side wall as a reference, etching the raised area to obtain a source-drain etching structure;

[0032] According to the source-drain etching structure, etching and deposition processing are performed in a set manner to obtain an inner sidewall structure;

[0033] On the inner sidewall structure, a drain-source epitaxial structure is obtained based on an epitaxial growth process; the drain-source epitaxial structure includes: a source and a drain of a first pull-up transistor, a source and a drain of a first pull-down transistor, a source and a drain of a first transmission transistor, a source and a drain of a second transmission transistor, a source and a drain of a second pull-down transistor, and a source and a drain of a second pull-up transistor that are interconnected;

[0034] Using an etching process, etching the virtual gate pattern based on the drain-source epitaxial structure, and performing gate metal deposition to obtain a metal gate structure;

[0035] The metal gate structure is etched and cut according to the set interval to obtain a gate cut structure; the gate cut structure includes a first complementary field effect transistor, a second complementary field effect transistor and a third complementary field effect transistor; the first complementary field effect transistor includes a first pull-down transistor and a first pull-up transistor stacked in sequence from bottom to top; the second complementary field effect transistor includes a first transmission transistor and a second transmission transistor stacked in sequence from bottom to top; the third complementary field effect transistor includes a second pull-down transistor and a second pull-up transistor stacked in sequence from bottom to top.

[0036] Optionally, performing photolithography deposition processing based on the fin-type structure to obtain a buried power rail structure specifically includes:

[0037] Filling the groove area of ​​the fin structure with an isolation oxide layer of a set thickness, defining a mask pattern based on photolithography, and etching the substrate to a set depth at both ends of the filled structure and perpendicular to the raised area to obtain a buried power rail groove;

[0038] A buried power rail structure is obtained by depositing a metal material in the buried power rail groove using a deposition process.

[0039] Optionally, according to the source-drain etching structure, etching and deposition processing are performed in a set manner to obtain an inner sidewall structure, specifically including:

[0040] Based on the source-drain etching structure, etching the silicon germanium on both sides of the outer side wall according to a set etching depth to obtain an inner side wall cavity structure;

[0041] Based on the inner sidewall cavity structure, a deposition and etching process is used to fill the material to obtain the inner sidewall structure.

[0042] Optionally, the gate metal is tungsten or aluminum.

[0043] Optionally, the method for preparing the semiconductor static memory further includes:

[0044] On the gate cut structure, photolithographically depositing buried power rail vias;

[0045] A photolithographic deposition method is adopted to determine the metal connection line based on the buried power rail through hole.

[0046] Optionally, a High-K gate technology is used to deposit gate metal to obtain a metal gate structure.

[0047] According to the specific embodiments provided in this application, this application discloses the following technical effects:

[0048] The present application provides a semiconductor static memory and a preparation method thereof, wherein a first embedded power rail and a second embedded power rail are arranged in parallel at both ends of a substrate, and then a first complementary field effect transistor, a second complementary field effect transistor and a third complementary field effect transistor are arranged at intervals; the first complementary field effect transistor is obtained by stacking a first pull-down transistor and a first pull-up transistor in sequence from bottom to top; the second complementary field effect transistor is obtained by stacking a first transmission transistor and a second transmission transistor in sequence from bottom to top; the first transmission transistor and the second transmission transistor are both of n-type; the third complementary field effect transistor is obtained by stacking a second pull-down transistor and a second pull-up transistor in sequence from bottom to top. Based on this structural setting, the standard unit area can be reduced and the integration of SRAM can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0050] Figure 1 It is the circuit diagram of SRAM standard unit;

[0051] Figure 2 Schematic diagram of the general structure of CFET;

[0052] Figure 3 Schematic diagram of silicon germanium stacking structure;

[0053] Figure 4 is a schematic diagram of the fin structure;

[0054] Figure 5 It is a schematic diagram of the STI filling structure;

[0055] Figure 6 Schematic diagram of the buried power rail trench structure;

[0056] Figure 7 This is a schematic diagram of the buried power rail structure;

[0057] Figure 8 is a schematic diagram of a virtual gate structure;

[0058] Fig. 9 Schematic diagram of the structure of the outer wall of the gate;

[0059] Fig.10 Schematic diagram of source and drain etching structure;

[0060] Fig.11 Schematic diagram of the inner wall cavity structure;

[0061] Fig.12 This is a schematic diagram of the inner wall structure;

[0062] Fig.13 It is a schematic diagram of the source-drain epitaxial structure and a viewing angle rotated 90° clockwise around the positive direction of the z-axis;

[0063] Fig.14 is a schematic diagram of a metal gate structure;

[0064] Fig.15 Schematic diagram of gate cutting structure;

[0065] Fig.16 A schematic diagram of the buried power rail through-hole structure and a perspective rotated 90° clockwise around the positive z-axis;

[0066] Fig.17 It is a schematic diagram of the bottom metal interconnect structure and the viewing angle rotated 120° clockwise around the positive z-axis;

[0067] Fig.18 It is a schematic diagram of the middle through-hole structure and the viewing angle rotated 120° clockwise around the positive direction of the z-axis;

[0068] Fig.19 is a schematic diagram of the top metal interconnect structure;

[0069] Fig. 20 It is a schematic diagram of the structure of a semiconductor static memory;

[0070] Fig.21 This is a schematic diagram of the viewing angle of the semiconductor static memory rotated 120° clockwise around the positive z-axis. DETAILED DESCRIPTION

[0071] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0072] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, the present application is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0073] The circuit diagram of the SRAM standard cell is as follows Figure 1 As shown in the figure, the SRAM standard cell as a whole is composed of 6 transistors (N1, N2, N3, N4, P1 and P2) connected by interconnection lines. P1 and P2 are PMOS, which are used as pull-up transistors in SRAM. N2 and N3 are NMOS, which are used as pull-down transistors in SRAM. N1 and N4 are also NMOS, which are used as transfer transistors in SRAM.

[0074] The top transistor of the first complementary field effect transistor CFET1 mentioned in this application corresponds to Figure 1 The N2 transistor in the bottom transistor of CFET1 corresponds to Figure 1 The top transistor of the second complementary field effect transistor CFET2 corresponds to Figure 1 The N4 transistor in the bottom transistor of CFET2 corresponds to Figure 1 The top transistor of the third complementary field effect transistor CFET3 corresponds to Figure 1 The N3 transistor in the bottom transistor of CFET3 corresponds to Figure 1 The P2 transistor in.

[0075] CFET is generally a structure in which NMOS and PMOS are stacked up and down to form an N / P complementary structure. The general structure of CFET is as follows Figure 2 As shown, it mainly includes a silicon substrate 201, a common metal gate 202, a channel 203 of a top transistor, a source epitaxy 204 of a top transistor, a drain epitaxy 205 of a top transistor, a channel 207 of a bottom transistor, a source epitaxy 208 of a bottom transistor, and a drain epitaxy 206 of a bottom transistor. The top transistor is generally NMOS, and the bottom transistor is PMOS, and the designer can also design it by himself. The vacant area of ​​the entire CFET structure 200 is filled with an interlayer dielectric. However, due to the asymmetric number of N / P transistors in the SRAM standard cell, the standard cell area reduction brought by the CFET structure is hindered.

[0076] In an exemplary embodiment, the present application provides a semiconductor static memory, which includes: a substrate, and an embedded power rail and a complementary field effect transistor disposed on the substrate.

[0077] The embedded power rail includes a first embedded power rail and a second embedded power rail; the first embedded power rail and the second embedded power rail are arranged in parallel at two ends of the substrate; one end of the complementary field effect transistor is connected to the first embedded power rail; the other end of the complementary field effect transistor is connected to the second embedded power rail.

[0078] The complementary field effect transistors include: a first complementary field effect transistor, a second complementary field effect transistor and a third complementary field effect transistor which are arranged at intervals.

[0079] The first complementary field effect transistor is obtained by stacking a first pull-down transistor and a first pull-up transistor in sequence from bottom to top.

[0080] The second complementary field effect transistor is obtained by stacking the first transmission transistor and the second transmission transistor in sequence from bottom to top; the first transmission transistor and the second transmission transistor are both of n-type.

[0081] The third complementary field effect transistor is obtained by stacking the second pull-down transistor and the second pull-up transistor in sequence from bottom to top.

[0082] In one embodiment, the semiconductor static memory further includes: a metal connection line.

[0083] The metal connection line includes: a bottom metal line and a top metal line; the gate of the first complementary field effect transistor adopts the bottom metal line, which is respectively connected to the bottom drain of the second complementary field effect transistor and the drain of the third complementary field effect transistor; the bottom drain of the second complementary field effect transistor is the drain of the first transmission transistor; the drain of the third complementary field effect transistor is a common drain structure determined by the drain of the second pull-down transistor and the drain of the second pull-up transistor. The gate of the first complementary field effect transistor is a common gate structure determined by the gate of the first pull-down transistor and the gate of the first pull-up transistor.

[0084] The drain of the first complementary field effect transistor adopts a top metal line, which is respectively connected to the top source of the second complementary field effect transistor and the gate of the third complementary field effect transistor; the top source of the second complementary field effect transistor is the source of the second transfer transistor; the gate of the third complementary field effect transistor is a common gate structure determined by the gate of the second pull-down transistor and the gate of the second pull-up transistor.

[0085] In one embodiment, the semiconductor static memory further includes: a buried power rail through hole; the material of the buried power rail through hole is tungsten or ruthenium.

[0086] The buried power rail vias are in contact with the buried power rail interconnect; the buried power rail vias include: a bottom via, a middle via, and a top via.

[0087] The bottom metal line connects the bottom source and the bottom through-hole of the first complementary field effect transistor; the bottom source of the first complementary field effect transistor is the source of the first pull-down transistor; the middle through-hole connects the top drain of the first complementary field effect transistor and the bottom drain of the first complementary field effect transistor to form a common drain structure; the middle through-hole is also connected to the bottom metal line; the top drain of the first complementary field effect transistor is the drain of the first pull-up transistor; the bottom drain of the first complementary field effect transistor is the drain of the first pull-down transistor.

[0088] The top through-hole is respectively connected to the top drain of the second complementary field effect transistor and the top source of the first complementary field effect transistor; the top through-hole is also respectively connected to the middle through-hole and the bottom metal line to form an interconnection structure; the top source of the first complementary field effect transistor is the source of the first pull-up transistor.

[0089] In an exemplary embodiment, a method for preparing a semiconductor static memory is provided. The method for preparing a semiconductor static memory is used to prepare a semiconductor static memory. The method for preparing a semiconductor static memory includes:

[0090] Silicon germanium and silicon are alternately epitaxially grown on a substrate to obtain a silicon germanium stacked structure.

[0091] The self-aligned double imaging technology is adopted to etch downwards from the top surface of the silicon germanium stack structure to a set position inside the substrate based on a set interval to obtain a fin-type structure; the fin-type structure includes: a groove area and a convex area.

[0092] A buried power rail structure is obtained by performing photolithography deposition processing based on a fin-type structure; the buried power rail structure includes: a substrate, an embedded power rail and a fin-type structure after photolithography processing; the embedded power rail includes a first embedded power rail and a second embedded power rail; the first embedded power rail and the second embedded power rail are arranged in parallel at two ends of the substrate.

[0093] By using etching and deposition processes, a virtual gate pattern with a set thickness is deposited on the buried power rail structure perpendicular to the raised area to obtain a virtual gate structure; the virtual gate pattern extends from the top to the bottom of the raised area.

[0094] In a direction perpendicular to the raised area, a deposition process is used to deposit material on both sides of the virtual gate structure to obtain an outer side wall.

[0095] Taking the outer wall as a reference, the raised area is etched to obtain a source-drain etching structure.

[0096] According to the source-drain etching structure, etching and deposition processing are performed in a set manner to obtain an inner sidewall structure.

[0097] On the inner sidewall structure, a drain-source epitaxial structure is obtained based on an epitaxial growth process; the drain-source epitaxial structure includes: an interconnected source and drain of a first pull-up transistor, a source and drain of a first pull-down transistor, a source and drain of a first transmission transistor, a source and drain of a second transmission transistor, a source and drain of a second pull-down transistor, and a source and drain of a second pull-up transistor.

[0098] The dummy gate pattern is etched based on the drain-source epitaxial structure by using an etching process, and gate metal is deposited to obtain a metal gate structure, wherein the gate metal is tungsten or aluminum.

[0099] As an optional implementation, High-K gate technology is used to deposit gate metal to obtain a metal gate structure.

[0100] The metal gate structure is etched and cut according to a set interval to obtain a gate cut structure; the gate cut structure includes a first complementary field effect transistor, a second complementary field effect transistor and a third complementary field effect transistor; the first complementary field effect transistor includes a first pull-down transistor and a first pull-up transistor stacked in sequence from bottom to top; the second complementary field effect transistor includes a first transmission transistor and a second transmission transistor stacked in sequence from bottom to top; the third complementary field effect transistor includes a second pull-down transistor and a second pull-up transistor stacked in sequence from bottom to top.

[0101] In one embodiment, a photolithography deposition process is performed based on a fin-type structure to obtain a buried power rail structure, specifically including:

[0102] An isolation oxide layer of a set thickness is filled in the groove area of ​​the fin structure, and a mask pattern is defined based on photolithography. A set depth is etched into the substrate at both ends of the filled structure and perpendicular to the raised area to obtain a buried power rail groove.

[0103] A buried power rail structure is obtained by depositing a metal material in the buried power rail groove using a deposition process.

[0104] In one embodiment, according to the source and drain etching structure, etching and deposition processing are performed in a set manner to obtain the inner sidewall structure, which specifically includes:

[0105] Based on the source-drain etching structure, the silicon germanium on both sides of the outer side wall is etched according to a set etching depth to obtain an inner side wall cavity structure.

[0106] Based on the inner side wall cavity structure, deposition and etching processes are used to fill the material to obtain the inner side wall structure.

[0107] In one embodiment, the method for preparing a semiconductor static memory further includes:

[0108] On the gate cutting structure, buried power rail vias are deposited by photolithography; and metal connection lines are determined based on the buried power rail vias by photolithography deposition.

[0109] In the present invention, based on the fact that the pull-up transistor and the pull-down transistor of the SRAM are composed of a CFET structure (CFET1 is composed of P1 and N2 stacked up and down, and CFET3 is composed of P2 and N3 stacked up and down), two NMOS transfer transistors (N1, N4) are also stacked up and down to obtain a CFET structure (CFET2), and the area of ​​the SRAM standard unit is reduced by designing metal interconnection.

[0110] The specific steps of the implementation method are as follows:

[0111] 1. Alternately epitaxially grow silicon germanium 2 and silicon 3 on a designated wafer substrate, that is, substrate 1, to form a silicon germanium stacked structure 100, such as Figure 3 The thickness and quantity of silicon germanium 2 and silicon 3 can be designed according to the requirements to obtain device designs with different performances.

[0112] 2. Based on the silicon germanium stacked structure 100, the silicon germanium stacked structure 100 is etched by using a self-aligned double imaging technique to obtain a fin-shaped structure 101, such as Figure 4 shown.

[0113] 3. On the basis of the fin structure 101, a shallow trench isolation oxide layer (STI) 4 is filled on the silicon substrate, that is, the substrate 1, to obtain an STI filling structure 102, such as Figure 5 As shown, the shallow trench isolation oxide layer 4 will surround the portion of the substrate 1 below the silicon germanium 2. The shallow trench isolation oxide layer 4 can be made of silicon nitride, silicon oxide, silicon oxynitride, etc., and can be deposited by a deposition process.

[0114] 3. Based on the fin structure 101, a mask pattern is defined by photolithography, and then the STI filling structure 102 is etched to a certain depth of the silicon substrate 1 to obtain a buried power rail trench structure 103, as shown in FIG. Figure 6 As shown, the depth can be designed by the designer according to the etching process capability.

[0115] 4. On the basis of the buried power rail groove structure 103, a first buried power rail 5 and a second buried power rail 6 are deposited by a deposition process to obtain a buried power rail structure 104, such as Figure 7 The first embedded power rail 5 and the second embedded power rail 6 are connected to the high level (VDD) wiring in the interconnection layout of the entire chip. The material of the first embedded power rail 5 and the second embedded power rail 6 can be metal tungsten, metal molybdenum, etc.

[0116] 5. On the basis of the buried power rail structure 104, the pattern of the virtual gate 7 is defined by photolithography, and the virtual gate 7 is deposited and covered around the substrate 1 of the buried power rail structure 104 and the fin-type stacked silicon germanium 2 and silicon 3 by etching and deposition processes to obtain a virtual gate structure 105, as shown in FIG. Figure 8 shown.

[0117] 6. On the basis of the virtual gate structure 105, an outer wall 8 is deposited on both sides of the virtual gate 7 by a deposition process to obtain a gate outer wall structure 106, such as Fig. 9 The material of the outer wall 8 can be silicon nitride, silicon oxide, etc.

[0118] 7. On the basis of the gate outer sidewall structure 106, the dummy gate 7 and the outer sidewall 8 are used as hard masks, and the substrate 1, silicon germanium 2 and silicon 3 not covered by the dummy gate 7 and the outer sidewall 8 are etched away through an etching process. The etching depth is designed by the designer, but the bottom silicon germanium 2 must be completely etched away, and can be etched to a position flush with the shallow trench isolation oxide layer 4, and finally a source-drain etching structure 107 is formed, as shown in FIG. Fig.10 shown.

[0119] 8. Based on the source-drain etching structure 107, a selective etching process is used to perform lateral etching in the y direction on all exposed silicon germanium 2 on both sides of the outer wall 8. The etching depth is designed by the designer and can be etched to the thickness of the outer wall to finally form an inner wall cavity structure 108, such as Fig.11 shown.

[0120] 9. On the basis of the inner wall cavity structure 108, the inner wall is filled in the inner wall cavity through deposition and etching processes to form an inner wall structure 109, such as Fig.12 The material of the inner wall can be silicon nitride, silicon oxide, etc. Note that it needs to be different from the material of the outer wall 8 to facilitate selective etching of the excess part.

[0121] 10. On the basis of the inner sidewall structure 109, epitaxially grow source and drain electrodes on the surface of all silicon 3 exposed on both sides of the outer sidewall 8 by a selective epitaxial growth process to obtain a source and drain epitaxial structure 110, as shown in FIG. Fig.13 As shown. All the sources and drains are epitaxially grown on the surface of silicon 3. They are: drain 10 and source 16 of the top transistor of CFET1, drain 13 and source 19 of the bottom transistor of CFET1, drain 11 and source 17 of the top transistor of CFET2, drain 14 and source 20 of the bottom transistor of CFET2, drain 18 and source 12 of the top transistor of CFET3, drain 21 and source 15 of the bottom transistor of CFET3.

[0122] 11. Based on the source-drain epitaxial structure 110, the dummy gate 7 is first etched away by an etching process, and then all exposed silicon germanium 2 is selectively etched, and then a metal gate 22 is deposited by using a High-K gate technology to obtain a metal gate structure 111, such as Fig.14 The gate metal can be tungsten, aluminum, etc., which is designed by the designer.

[0123] 12. Based on the metal gate structure 111, the metal gate 22 and the outer sidewall 8 are etched by an etching process to form a gate cutting structure 112, such as Fig.15 The metal gate 22 is cut into three parts, corresponding to the metal gate 22 - 1 of CFET1, the metal gate 22 - 2 of CFET2, and the metal gate 22 - 3 of CFET3 respectively.

[0124] 13. On the basis of the gate cutting structure 112, a buried power rail through hole and a mask of the buried power rail through hole are defined by photolithography, and then a first bottom through hole 23 and a second bottom through hole 24 are formed by etching and deposition processes to obtain a buried power rail through hole structure 113, wherein the first bottom through hole 23 forms an interconnection contact with the second buried power rail 6, and the second bottom through hole 24 forms an interconnection contact with the first buried power rail 5. Fig.16 The material of the buried power rail via can be tungsten, ruthenium, etc., which is designed by the designer.

[0125] 14. On the basis of the buried power rail via structure 113, a mask for defining the first bottom metal interconnection line 25, the second bottom metal interconnection line 26, the third bottom metal interconnection line 27 and the fourth bottom metal interconnection line 28 is defined by photolithography, and then the first bottom metal interconnection line 25, the second bottom metal interconnection line 26, the third bottom metal interconnection line 27 and the fourth bottom metal interconnection line 28 are formed by etching and deposition processes to obtain a bottom metal interconnection line structure 114, as shown in FIG. Fig.17As shown. The first bottom metal interconnection line 25 connects the drain 13 of the bottom transistor of CFET1, the drain 14 of the bottom transistor of CFET2 and the metal gate 22-3 of CFET3 in sequence. The second bottom metal interconnection line 26 connects the source 15 of the bottom transistor of CFET3 and the first bottom via 23, electrically connecting the source 15 of the bottom transistor of CFET3 with the second buried power rail 6. The third bottom metal interconnection line 27 connects the source 20 of the bottom transistor of CFET2 and extends a certain length along the positive direction of the coordinate axis y axis, and the length is set by the designer on the premise of meeting the setting rules. The fourth bottom metal interconnection line 28 connects the source 19 of the bottom transistor of CFET1 and the second bottom via 24, electrically connecting the source 19 of the bottom transistor of CFET1 with the buried power rail 5. The bottom metal lines include: the first bottom metal interconnection line 25, the second bottom metal interconnection line 26, the third bottom metal interconnection line 27 and the fourth bottom metal interconnection line 28.

[0126] 15. Based on the bottom metal interconnection structure 114, a mask pattern of the intermediate through hole is defined by photolithography; then, a first intermediate through hole 29, a second intermediate through hole 30 and a third intermediate through hole 31 are formed by etching and deposition processes to obtain an intermediate through hole structure 115. The intermediate through hole structure is as follows Fig.18 The intermediate through holes include: a first intermediate through hole 29 , a second intermediate through hole 30 and a third intermediate through hole 31 .

[0127] The first middle via 29 connects the drain 10 of the top transistor of CFET1 and the drain 13 of the bottom transistor of CFET1 to form a common drain structure of CFET1, and is connected to the first bottom metal interconnection line 25. The second middle via 30 connects the drain 18 of the top transistor of CFET3 and the drain 21 of the bottom transistor of CFET3 to form a common drain structure of CFET3. The third middle via 31 connects the third bottom metal interconnection line 27.

[0128] 16. On the basis of the intermediate through-hole structure 115, a mask of the top metal interconnection line 32 is defined by photolithography, and then the top metal interconnection line 32 is formed by photolithography and deposition process to obtain a top metal interconnection line structure 116, as shown in FIG. Fig.19 The top metal interconnection line 32 sequentially connects the metal gate 22 - 1 of CFET1 , the source 17 of the top transistor of CFET2 , the drain 18 of the top transistor of CFET3 , and the middle via 30 .

[0129] 17. On the basis of the top metal interconnection structure 116, a mask for defining top vias, i.e., a first top via 33, a second top via 34, a third top via 35, a fourth top via 36, ​​and a fifth top via 37, is defined by photolithography, and then the first top via 33, the second top via 34, the third top via 35, the fourth top via 36, ​​and the fifth top via 37 are formed by etching and deposition processes to obtain a top via structure 117, as shown in FIG. Fig. 20 and Fig.21 As shown. The first top via 33 is connected to the drain 11 of the top transistor of CFET2, and the second top via 34 is connected to the source 12 of the top transistor of CFET3. The third top via 35 is connected to the third middle via 31, and the third top via 35 forms an electrical interconnection structure with the third middle via 31 and the third bottom metal interconnection line 27. The fourth top via 36 is connected to the metal gate 22-2 of CFET2, and the fifth top via 37 is connected to the source 16 of the top transistor of CFET1.

[0130] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0131] This article uses specific examples to illustrate the principles and implementation methods of this application. The description of the above embodiments is only used to help understand the method and core ideas of this application. At the same time, for those skilled in the art, according to the ideas of this application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as limiting this application.

Claims

1. A semiconductor static memory, characterized in that: The semiconductor static memory comprises: a substrate and an embedded power rail and a complementary field effect transistor arranged on the substrate; The embedded power rail comprises a first embedded power rail and a second embedded power rail; The first buried power rail and the second buried power rail are arranged in parallel at two ends of the substrate; one end of the complementary field effect transistor is connected to the first buried power rail; the other end of the complementary field effect transistor is connected to the second buried power rail; The complementary field effect transistors include: a first complementary field effect transistor, a second complementary field effect transistor and a third complementary field effect transistor which are arranged at intervals; The first complementary field effect transistor is obtained by stacking a first pull-down transistor and a first pull-up transistor in sequence from bottom to top; The second complementary field effect transistor is obtained by stacking the first transmission transistor and the second transmission transistor in sequence from bottom to top; the first transmission transistor and the second transmission transistor are both of n-type; The third complementary field effect transistor is obtained by stacking the second pull-down transistor and the second pull-up transistor in sequence from bottom to top.

2. The semiconductor static memory according to claim 1, characterized in that: The semiconductor static memory further comprises: a metal connection line; The metal connection line includes: a bottom metal line and a top metal line; The gate of the first complementary field effect transistor adopts the bottom metal line and is respectively connected to the bottom drain of the second complementary field effect transistor and the drain of the third complementary field effect transistor; the bottom drain of the second complementary field effect transistor is the drain of the first transfer transistor; the drain of the third complementary field effect transistor is a common drain structure determined by the drain of the second pull-down transistor and the drain of the second pull-up transistor; the gate of the first complementary field effect transistor is a common gate structure determined by the gate of the first pull-down transistor and the gate of the first pull-up transistor; The drain of the first complementary field effect transistor adopts the top metal line and is respectively connected to the top source of the second complementary field effect transistor and the gate of the third complementary field effect transistor; the top source of the second complementary field effect transistor is the source of the second transfer transistor; the gate of the third complementary field effect transistor is a common gate structure determined by the gate of the second pull-down transistor and the gate of the second pull-up transistor.

3. The semiconductor static memory according to claim 2, characterized in that: The semiconductor static memory further comprises: a buried power rail through hole; The buried power rail via is in contact with the buried power rail interconnect; The buried power rail through hole comprises: a bottom through hole, a middle through hole and a top through hole; The bottom metal line connects the bottom source of the first complementary field effect transistor and the bottom through hole; the bottom source of the first complementary field effect transistor is the source of the first pull-down transistor; The middle through hole connects the top drain of the first complementary field effect transistor and the bottom drain of the first complementary field effect transistor to form a common drain structure; the middle through hole is also connected to the bottom metal line; the top drain of the first complementary field effect transistor is the drain of the first pull-up transistor; the bottom drain of the first complementary field effect transistor is the drain of the first pull-down transistor; The top through-hole is respectively connected to the top drain of the second complementary field effect transistor and the top source of the first complementary field effect transistor; the top through-hole is also respectively connected to the middle through-hole and the bottom metal line to form an interconnection structure; the top source of the first complementary field effect transistor is the source of the first pull-up transistor.

4. The semiconductor static memory according to claim 3, characterized in that: The material of the buried power rail through hole is tungsten or ruthenium.

5. A method for preparing a semiconductor static memory, characterized in that: The method for preparing the semiconductor static memory is used to prepare the semiconductor static memory according to any one of claims 1 to 4, and the method for preparing the semiconductor static memory comprises: Alternately epitaxially growing silicon germanium and silicon on a substrate to obtain a silicon germanium stacked structure; Using self-aligned double imaging technology, etching downward from the top surface of the silicon germanium stack structure to a set position inside the substrate based on a set interval to obtain a fin-type structure; the fin-type structure includes: a groove area and a convex area; Performing photolithography deposition processing based on the fin-shaped structure to obtain a buried power rail structure; the buried power rail structure includes: a substrate, an buried power rail and a fin-shaped structure after photolithography processing; the buried power rail includes a first buried power rail and a second buried power rail; the first buried power rail and the second buried power rail are arranged in parallel at two ends of the substrate; By using etching and deposition processes, a virtual gate pattern with a set thickness is deposited on the buried power rail structure perpendicular to the raised area to obtain a virtual gate structure; the virtual gate pattern extends from the top to the bottom of the raised area; In a direction perpendicular to the raised area, depositing material on both sides of the virtual gate structure using a deposition process to obtain an outer sidewall; Taking the outer side wall as a reference, etching the raised area to obtain a source-drain etching structure; According to the source-drain etching structure, etching and deposition processing are performed in a set manner to obtain an inner sidewall structure; On the inner sidewall structure, a drain-source epitaxial structure is obtained based on an epitaxial growth process; the drain-source epitaxial structure includes: a source and a drain of a first pull-up transistor, a source and a drain of a first pull-down transistor, a source and a drain of a first transmission transistor, a source and a drain of a second transmission transistor, a source and a drain of a second pull-down transistor, and a source and a drain of a second pull-up transistor that are interconnected; Using an etching process, etching the virtual gate pattern based on the drain-source epitaxial structure, and performing gate metal deposition to obtain a metal gate structure; The metal gate structure is etched and cut according to the set interval to obtain a gate cut structure; the gate cut structure includes a first complementary field effect transistor, a second complementary field effect transistor and a third complementary field effect transistor; the first complementary field effect transistor includes a first pull-down transistor and a first pull-up transistor stacked in sequence from bottom to top; the second complementary field effect transistor includes a first transmission transistor and a second transmission transistor stacked in sequence from bottom to top; the third complementary field effect transistor includes a second pull-down transistor and a second pull-up transistor stacked in sequence from bottom to top.

6. The method for preparing a semiconductor static memory according to claim 5, characterized in that: Based on the fin-type structure, a photolithography deposition process is performed to obtain a buried power rail structure, which specifically includes: Filling the groove area of ​​the fin structure with an isolation oxide layer of a set thickness, defining a mask pattern based on photolithography, and etching the substrate to a set depth at both ends of the filled structure and perpendicular to the raised area to obtain a buried power rail groove; A buried power rail structure is obtained by depositing a metal material in the buried power rail groove using a deposition process.

7. The method for preparing a semiconductor static memory according to claim 5, characterized in that: According to the source-drain etching structure, etching and deposition processing are performed in a set manner to obtain an inner sidewall structure, which specifically includes: Based on the source-drain etching structure, etching the silicon germanium on both sides of the outer side wall according to a set etching depth to obtain an inner side wall cavity structure; Based on the inner sidewall cavity structure, a deposition and etching process is used to fill the material to obtain the inner sidewall structure.

8. The method for preparing a semiconductor static memory according to claim 5, characterized in that: The gate metal is made of tungsten or aluminum.

9. The method for preparing a semiconductor static memory according to claim 5, characterized in that: The method for preparing the semiconductor static memory further includes: On the gate cut structure, photolithographically depositing buried power rail vias; A photolithographic deposition method is adopted to determine the metal connection line based on the buried power rail through hole.

10. The method for preparing a semiconductor static memory according to claim 5, characterized in that: The gate metal is deposited using High-K gate technology to obtain a metal gate structure.

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