Semiconductor device and preparation method thereof

Abstract

The invention provides a semiconductor device and a preparation method thereof, and relates to the technical field of semiconductors. The semiconductor device includes: a stack layer; the top selection gate layer is located on the stacking layer; the grid line isolation structure penetrates through the top selection grid layer and the stacking layer, the part, penetrating through the top selection grid layer, in the grid line isolation structure is a first isolation structure, and the first isolation structure comprises a contact layer channel structure making contact with the top selection grid layer and penetrates through the stacking layer; the first dielectric layer is located on the top selection gate layer, and the first dielectric layer and the contact layer comprise different insulating media; and the channel local contact penetrates through the first dielectric layer and is arranged corresponding to the channel structure. According to the technical scheme of the invention, the influence of the etching operation of the first dielectric layer on the contact layer of the grid line isolation structure can be reduced, and the yield of the semiconductor device is improved.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for preparing a semiconductor device. Background Art

[0002] Etching operation is one of the main steps in semiconductor manufacturing. In order to ensure the etching effect, sufficient etching window margin is required when etching the etch stop layer. This leads to the risk of damaging other isolation structures in adjacent areas that have the same dielectric as the etch stop layer, thereby affecting the electrical performance of the semiconductor device.

[0003] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0004] The purpose of the present disclosure is to provide a semiconductor device and a method for manufacturing the same, which can at least to some extent improve the problem of the etching process in the related art damaging the isolation structure and causing leakage.

[0005] Other features and advantages of the present disclosure will become apparent from the following detailed description, or may be learned in part by the practice of the present disclosure.

[0006] According to one aspect of the present disclosure, a semiconductor device is provided, comprising: a stacked layer; a top selection gate layer located on the stacked layer; a gate line isolation structure passing through the top selection gate layer and the stacked layer, wherein a portion of the gate line isolation structure passing through the top selection gate layer is a first isolation structure, wherein the first isolation structure comprises a contact layer channel structure in contact with the top selection gate layer and passing through the stacked layer; a first dielectric layer located on the top selection gate layer, wherein the first dielectric layer and the contact layer comprise different insulating media; and a channel local contact passing through the first dielectric layer and arranged corresponding to the channel structure.

[0007] In some embodiments, the method further includes: a connection structure penetrating the top selection gate layer, one end of the connection structure contacts the channel structure, and the other end of the connection structure contacts the channel local contact.

[0008] In some embodiments, the present invention further includes: a second dielectric layer located between the top selection gate layer and the first dielectric layer, wherein the connection structure contacts the channel local contact through the second dielectric layer.

[0009] In some embodiments, a portion of the gate line isolation structure that passes through the stacked layer is a second isolation structure, and along a direction parallel to the first dielectric layer, a width of the first isolation structure is greater than a width of the second isolation structure.

[0010] In some embodiments, the semiconductor device includes a core area CA and a stepped area SS, the top selection gate layer is arranged in the core area, and the semiconductor device also includes: a first contact structure, which is arranged in the core area, penetrates the first dielectric layer and the second dielectric layer, and extends to the top selection gate layer; a second contact structure, which is arranged in the stepped area, penetrates the first dielectric layer, and extends to the step of the stepped area.

[0011] In some embodiments, the first contact structure includes a first substructure passing through the first dielectric layer and a second substructure passing through the dielectric layer, and along a direction parallel to the first dielectric layer, at a position where the first substructure and the second substructure are connected, the width of the first substructure is greater than the width of the second substructure; the second contact structure includes a third substructure passing through the first dielectric layer and a fourth substructure extending to the steps of the step area, and along a direction parallel to the first dielectric layer, at a position where the third substructure and the fourth substructure are connected, the width of the third substructure is greater than the width of the fourth substructure.

[0012] In some embodiments, along a direction parallel to the first dielectric layer, a portion of the channel local contact passing through the first dielectric layer has a first width, a portion of the first contact structure passing through the first dielectric layer has a second width, and a portion of the second contact structure passing through the first dielectric layer has a third width; wherein the second width is greater than the first width, and the first width is greater than the third width.

[0013] In some embodiments, it also includes: a gap contact structure, which penetrates the first dielectric layer and is connected to the gate line isolation structure.

[0014] In some embodiments, the method further includes: a semiconductor layer disposed on a side of the stacked layer away from the top selection gate layer.

[0015] In some embodiments, the present invention further includes: a cap layer disposed on the first dielectric layer, wherein the channel local contact passes through the cap layer and the first dielectric layer and contacts the channel structure.

[0016] In some embodiments, the first dielectric layer and the capping layer include different insulating media; the first dielectric layer and the second dielectric layer include different insulating media.

[0017] In some embodiments, the method further includes: a top selection gate cut line located between the first dielectric layer and the stacked layer and penetrating the top selection gate layer, wherein the top selection gate cut line and the first dielectric layer include the same or different insulating medium.

[0018] In some embodiments, the different insulating medium includes at least two of silicon nitride, insulating oxide, and silicon oxynitride.

[0019] According to another aspect of the present disclosure, a semiconductor device is provided, including: a stacked layer; a top selection gate layer located on the stacked layer; a gate line isolation structure penetrating the top selection gate layer and the stacked layer; a channel structure penetrating the stacked layer; a first dielectric layer located on the top selection gate layer, and the first dielectric layer covers the gate line isolation structure; a channel local contact penetrating the first dielectric layer and arranged corresponding to the channel structure.

[0020] In some embodiments, the method further includes: a connection structure penetrating the top selection gate layer, one end of the connection structure contacts the channel structure, and the other end of the connection structure contacts the channel local contact.

[0021] In some embodiments, the present invention further includes: a second dielectric layer located between the top selection gate layer and the first dielectric layer, wherein the connection structure contacts the channel local contact through the second dielectric layer.

[0022] In some embodiments, the method further includes: a top selection gate cut line located between the first dielectric layer and the stacked layer and penetrating the top selection gate layer, wherein the top selection gate cut line and the first dielectric layer include the same or different insulating medium.

[0023] According to another aspect of the present disclosure, a method for preparing a semiconductor device is provided, comprising: providing a substrate, the substrate comprising a substrate, a stacked layer located on the substrate, a top selection gate layer located on the stacked layer, a channel structure extending through the stacked layer to the substrate, and a gate line isolation structure extending through the top selection gate layer and the stacked layer to the substrate to form a first dielectric layer, the first dielectric layer being located on the top selection gate layer; forming a channel local contact, the channel local contact passing through the first dielectric layer and being arranged corresponding to the channel structure.

[0024] In some embodiments, the forming of the first dielectric layer includes: forming a second dielectric layer on the top selection gate layer; planarizing the second dielectric layer; and forming the first dielectric layer on the second dielectric layer.

[0025] In some embodiments, the method further includes: forming a capping layer, wherein the capping layer is located on the first dielectric layer.

[0026] In some embodiments, the semiconductor device includes a core area CA and a stepped area SS, and the formation of a local channel contact includes: performing an etching operation on the cap layer and the first dielectric layer in the core area to form a local channel contact window; filling a conductive material in the local channel contact window to form the local channel contact.

[0027] In some embodiments, the etching operation is performed on the cap layer and the first dielectric layer in the core area, including: performing an etching operation on the cap layer in the core area to form a local opening of the channel; etching the first dielectric layer in the local channel opening to form a local contact window of the channel.

[0028] In some embodiments, the etching operation performed on the cap layer and the first dielectric layer in the core area also includes: forming a first contact opening in the core area synchronously with the local contact window of the channel, the opening size of the first contact opening is larger than the window size of the local contact window of the channel; and forming a second contact opening in the step area synchronously with the local contact window of the channel, the first contact opening and the second contact opening both pass through the cap layer and the first dielectric layer, and extend to the second dielectric layer.

[0029] In some embodiments, after etching the cap layer and the first dielectric layer in the core area to form a local contact window of the channel, the method further includes: etching the cap layer and the first dielectric layer in the core area to form a first contact opening, wherein the opening size of the first contact opening is larger than the window size of the local contact window of the channel; etching the cap layer and the first dielectric layer in the step area to form a second contact opening.

[0030] In some embodiments, it also includes: performing an etching operation on the second dielectric layer and the top selection gate layer in the first contact opening to form a first sub-hole; performing an etching operation on the second dielectric layer and the stacked layer in the second contact opening to form a second sub-hole extending to the step of the step area.

[0031] In some embodiments, filling the local contact window of the channel with a conductive material further includes: filling the first contact opening and the first sub-hole with the conductive material to form a first contact structure; and filling the second contact opening and the second sub-hole with the conductive material to form a second contact structure.

[0032] In some embodiments, the method further includes: etching the cap layer and the first dielectric layer in an area corresponding to the gate line isolation structure to form a gate lead hole; and filling the gate lead hole with a conductive material to form a gap contact structure.

[0033] In some embodiments, the method further includes: removing the substrate to expose a substrate end portion, where the substrate end portion is a portion where the channel structure extends to the substrate.

[0034] In some embodiments, the method includes forming a semiconductor layer on a side of the stacked layer away from the first dielectric layer, wherein the semiconductor layer covers the end of the substrate.

[0035] The semiconductor device and preparation method thereof provided by the embodiments of the present disclosure, after forming the gate line isolation structure, a first dielectric layer is formed on the top selection gate layer as an etching stop layer, and a channel local contact is further formed on the first dielectric layer. On the one hand, since the gate line isolation structure is in a state of being covered by the first dielectric layer during the process of etching the first dielectric layer to form the channel local contact window of the channel local contact, on the other hand, the first dielectric layer adopts an insulating medium different from the contact layer of the gate line isolation structure. The first dielectric layer is used as the medium to be etched, and the contact layer of the gate isolation structure is used as the medium to be protected. By reasonably setting the etching selectivity ratio of the two media, it is beneficial to reduce the influence of the etching operation of the first dielectric layer on the contact layer of the gate line isolation structure, thereby improving the yield of the semiconductor device.

[0036] Other features and advantages of the present invention, as well as the structure and operation of various embodiments of the present invention are described in detail below with reference to the accompanying drawings. It should be noted that the present invention is not limited to the specific embodiments described herein. Such embodiments are presented herein for illustrative purposes only. Based on the teachings contained herein, additional embodiments will be apparent to those skilled in the relevant art. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification are used to explain the principles of the present disclosure. Obviously, the accompanying drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without creative work.

[0038] Figure 1 A semiconductor device according to some embodiments of the present disclosure is shown;

[0039] Figure 2-18 A cross-sectional view of a semiconductor device during a manufacturing process according to some embodiments of the present disclosure is shown;

[0040] Fig.19 A plan view showing a cross section of a semiconductor device according to some embodiments of the present disclosure;

[0041] Fig. 20 A flow chart showing a method for forming a semiconductor device according to some embodiments of the present disclosure is shown;

[0042] Fig.21 A schematic diagram showing a memory system according to some embodiments of the present disclosure is shown;

[0043] Fig. 22 A schematic diagram of a memory card according to an embodiment of the present disclosure is shown;

[0044] Fig.23 A schematic diagram of a solid state drive SSD according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0045] Although specific configurations and arrangements have been discussed, it should be understood that this is done for exemplary purposes only. Those skilled in the art will recognize that other configurations and arrangements may be used without departing from the spirit and scope of the present disclosure. It will be apparent to those skilled in the art that the present disclosure may also be used for a variety of other applications.

[0046] It is noted that references to "one embodiment", "an embodiment", "an exemplary embodiment", "some embodiments", etc. in the specification indicate that the described embodiments may include a particular feature, structure or characteristic, but not every embodiment may include the particular feature, structure or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. In addition, when a particular feature, structure or characteristic is described in conjunction with an embodiment, it should be within the knowledge of those skilled in the art to implement such feature, structure or characteristic in conjunction with other embodiments (whether or not explicitly described).

[0047] In general, a term can be understood, at least in part, from its use in context. For example, depending, at least in part, on the context, the term "one or more" as used herein can be used to describe a feature, structure, or characteristic in a singular sense, or can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, depending, at least in part, on the context, terms such as "a," "an," or "the" can be understood to convey singular use or to convey plural use.

[0048] It should be readily understood that the meanings of “on,” “over,” and “over…” in the present disclosure should be interpreted in the broadest manner, such that “on…” means not only “directly on” something, but also includes the meaning of being “on” something with intervening features or layers therebetween, and “over…” or “over…” means not only “on” or “above” something, but also includes the meaning of being “on” or “above” something with no intervening features or layers therebetween (i.e., directly on something).

[0049] Additionally, spatially relative terms such as "below," "beneath," "lower," "above," "upper," and the like may be used herein for descriptive convenience to describe the relationship of one element or feature to another element or features as illustrated in the accompanying drawings. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the accompanying drawings. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein may be similarly interpreted accordingly.

[0050] As used herein, the term "substrate" refers to a material to which subsequent materials are added or otherwise disposed. The substrate itself can be patterned. The material disposed on the substrate (e.g., the top) can be patterned or can remain unpatterned. In addition, the substrate can include a wide range of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be made of a non-conductive material such as glass, plastic, or sapphire wafer.

[0051] As used herein, the term "layer" refers to a material portion including an area with a thickness. A layer may extend over the entirety of a lower or upper structure, or may have a range that is less than the range of a lower or upper structure. In addition, a layer may be a region of a homogeneous or inhomogeneous continuous structure having a thickness that is less than the thickness of a continuous structure. A layer may extend horizontally, vertically and / or along an inclined surface. A substrate may be a layer, which may include one or more layers, and / or may have one or more layers thereon, above and / or below. A layer may include multiple layers. For example, a stacked layer may include one or more conductors and contact layers (wherein contacts, interconnects and / or vias are formed) and one or more dielectric layers.

[0052] As used herein, the term "nominal / nominally" refers to an expected or target value for a characteristic or parameter of a component or process operation set during the design phase of production or a process, as well as a range of values ​​above and / or below the expected value. The range of values ​​may be due to slight variations in the manufacturing process or tolerances. As used herein, the term "about" indicates a value of a given quantity that may vary based on a particular technology node associated with the subject semiconductor device. Based on a particular technology node, the term "about" may indicate a value of a given quantity that varies, for example, within 10%-30% of the value (e.g., ±10%, ±20%, or ±30% of the value).

[0053] As used herein, a "semiconductor device" is a semiconductor device having a vertically oriented string of memory cell transistors (referred to herein as a "memory string", such as a NAND string) on ​​a laterally oriented substrate, such that the memory string extends in a vertical direction relative to the substrate. As used herein, the term "vertical / vertically" means nominally perpendicular to a lateral surface of the substrate.

[0054] As used herein, the terms “horizontal / horizontally / lateral / laterally” mean nominally parallel to a lateral surface of a substrate, and the terms “vertical” or “vertically” mean nominally perpendicular to a lateral surface of a substrate.

[0055] As used herein, a "semiconductor device" may specifically be a "3D memory device". In certain 3D memory devices such as 3D NAND memory devices, a gap structure (e.g., a gate line isolation structure (GLS)) is used to provide an electrical connection from the front side of the device to a source of a memory array (e.g., an array common source (ACS)).

[0056] like Figure 1As shown, in order to form a channel local contact 102 (C1CH) on the top selection gate layer 106 (TSG), the process used is to perform an etching operation on the etch stop layer 108 above the top selection gate layer and stop at the dielectric layer 104, wherein the etch stop layer 108 can be an oxide material, and a channel local contact window is formed by using wet etching and / or dry etching (such as RIE) to penetrate the etch stop layer 108, and a conductive material is filled in the channel local contact window to form a channel local contact. Since there is a gap between the channel local contact 102 and the gate line isolation structure 110 (GLS), The distance is small, and sufficient etching window margin needs to be ensured during etching, and the material used for the contact layer in the gate line isolation structure 110 that passes through the top selection gate layer 106 and contacts the top selection gate layer 106 is the same oxide material as the etching stop layer 108. Since the etching parameters for the same material are the same, there is a greater risk of etching onto the contact layer of the gate line isolation structure 110 during etching, causing the contact layer to be damaged, resulting in abnormal electrical connection between the top selection gate layer 106 and the conductive part in the gate line isolation structure 110, and ultimately reducing the yield of the semiconductor device.

[0057] In addition, in order to form local channel contacts and other contact structures separately, different masks need to be configured during etching operations to respectively etch the local channel contact windows and the contact openings of other contact structures. This process also results in an increase in the number of masks and corresponding steps.

[0058] According to various embodiments of the present disclosure, a semiconductor device is provided, which includes a stacked layer, a top selection gate layer located on the stacked layer, and a gate line isolation structure that penetrates the top selection gate layer and the stacked layer. After the gate line isolation structure is formed, a first dielectric layer is formed on the top selection gate layer as an etch stop layer, and a channel local contact is further formed on the etch stop layer. On the one hand, during the process of etching the etch stop layer to form a channel local contact window of the channel local contact, the gate line isolation structure is in a state of being covered by the etch stop layer. On the other hand, the etch stop layer adopts an insulating medium different from the contact layer of the gate line isolation structure. The etch stop layer serves as a dielectric layer to be etched, and the contact layer of the gate isolation structure serves as a dielectric layer to be protected. By reasonably setting the etching selectivity ratio of the two dielectrics, it is beneficial to reduce the influence of the etching operation of the etch stop layer on the contact layer of the gate line isolation structure, thereby improving the yield of the semiconductor device.

[0059] It should be noted that Figures 1 to 19The x, y, and z axes are included in the semiconductor device to illustrate the spatial relationship of components in the semiconductor device. The x-direction and the y-direction are two orthogonal directions in the semiconductor plane: the x-direction is the word line direction, and the y-direction is the bit line direction. The z-axis is perpendicular to the x- and y-axes. As used herein, when a substrate (e.g., substrate 10) is located in the lowest plane of the semiconductor device in the z-direction (a vertical direction perpendicular to the xy plane), whether a component of the semiconductor device is "on", "above", or "below" another component (e.g., a layer or device) in the z-direction can be determined relative to the substrate 10 of the semiconductor device. Throughout the present disclosure, the same concept for describing spatial relationships is applied.

[0060] In addition, if Figures 1 to 19 As shown, the semiconductor device includes a core area CA (Core Array) and a step area SS (Staircase).

[0061] like Figure 2 As shown, in some embodiments, the semiconductor device includes a semiconductor layer 10 .

[0062] In some embodiments, the semiconductor layer 10 may be a substrate 10 which may include silicon (e.g., single crystal silicon, c-Si), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), or any other suitable material.

[0063] The semiconductor device also includes a stacked layer 20 formed on the substrate 10. In the initial stage, the stacked layer 20 includes alternating interlayer insulating layers 202 and interlayer sacrificial layers 204, wherein the interlayer insulating layer 202 is specifically an oxide, and the interlayer sacrificial layer 204 is specifically a nitride. The interlayer sacrificial layer 204 will be replaced by a conductor layer in a subsequent process. The interlayer insulating layer 202 and the interlayer sacrificial layer 204 alternate in a vertical direction (for example, along the z-axis). In other words, except for the top or bottom layer of the stacked layer 20, each interlayer insulating layer 202 can be adjacent to two interlayer sacrificial layers 204 on both sides, or each interlayer sacrificial layer 204 can be adjacent to two interlayer insulating layers 202 on both sides, and the interlayer insulating layers 202 can all have the same thickness or different thicknesses. Similarly, the interlayer sacrificial layers 204 can all have the same thickness or different thicknesses. For example, but not limitation, the thickness of each interlayer insulating layer 202 may be in a range from about 25 nm to about 40 nm, and the thickness of each interlayer sacrificial layer 204 may be in a range from about 20 nm to about 35 nm.

[0064] In some embodiments, Figure 3As shown, the semiconductor device further includes a channel structure 50 penetrating the stacked layer 20. Specifically, the channel structure 50 may include a channel hole CH (Channel Hole) and a blocking dielectric layer 502, a charge capture layer 504, a tunnel dielectric layer 506, a channel layer 508 and a filling layer 510 stacked in sequence along the radial direction of the channel hole. In practical applications, the blocking dielectric layer 502, the charge capture layer 504, the tunnel dielectric layer 506 and the channel layer 508 are formed in this order along the sidewall and bottom surface of the channel hole, the blocking dielectric layer 502 is used to block the outflow of charges in the storage layer, and the charge capture layer 504 is used to capture and store charges.

[0065] In some embodiments, Figure 4 As shown, after the channel structure 50 is formed, a top selection gate layer 30 (TSG deck) is further formed.

[0066] In some embodiments, in other process flows, the top selection gate layer 30 may be formed first, and then the channel structure 50 penetrating the top selection gate layer 30 and the stacked layer 20 may be formed.

[0067] Among them, as a method of forming the top selection gate layer 30, specific steps may include: first forming a top stack on the stacked layer 20, removing the top sacrificial layer through the gate gap in the top stack to form a top interlayer gap, and forming the top selection gate layer 30 in the top interlayer gap.

[0068] like Figure 8 As shown, in some embodiments, the semiconductor device also includes a gate line isolation structure 40, the gate line isolation structure 40 passes through the top selection gate layer 30 and the stacked layer 20, and the portion of the gate line isolation structure 40 that passes through the top selection gate layer 30 is a first isolation structure 402, and the first isolation structure 402 includes a contact layer 4022 that contacts the top selection gate layer.

[0069] In order to form a gate isolation structure, it is necessary to first form a gate gap (not shown in the figure) that penetrates the top selection gate layer 30 and the stacked layer 20, remove the interlayer sacrificial layer 204 through the gate gap, and form a conductor layer 206 at the position of the original interlayer sacrificial layer 204, such as Figure 8 As shown, the conductor layer may include a metal layer (not shown in the figure), and the metal specifically includes tungsten and the like.

[0070] Specifically, the gate line isolation structure 40 is configured to separate a memory block of the semiconductor device into a plurality of memory fingers.

[0071] In some embodiments, the gate line isolation structure 40 further extends into the substrate.

[0072] Specifically, in order to form the gate line isolation structure 40 , a gate line gap is first formed in the stacked layer 20 and the top selection gate layer 30 , and the gate line gap vertically penetrates the top selection gate layer 30 along the Z direction.

[0073] like Fig.10 As shown, in some embodiments, the semiconductor device further includes: a cap layer 120, which is disposed on the first dielectric layer 60, and the first dielectric layer 60 can be used as an etch stop layer, and the channel local contact 70 passes through the cap layer 120 and the first dielectric layer 60 and contacts the channel structure 50. The cap layer 120 may include silicon oxide, silicon nitride, silicon oxynitride, TEOS or a combination thereof. The cap layer 120 may be deposited by CVD (chemical vapor deposition), PVD (physical vapor deposition), ALD (atomic layer deposition) or sputtering, etc.

[0074] In some embodiments, the gate line gaps also penetrate the capping layer 120 .

[0075] In some embodiments, the gate line gap extends into the substrate, the gate line gap can be formed by a photolithography process and an etching process, the etching process can include any suitable dry etching, wet etching and / or a combination thereof, and the gate line gap can extend laterally along the WL direction.

[0076] Specifically, the gate line isolation structure 40 includes a GLS isolation layer 406 disposed on the sidewalls of the gate line gap. The gate line isolation layer 406 may include any suitable insulator, such as silicon oxide, silicon nitride, silicon oxynitride, boron or phosphorus doped silicon oxide, carbon-doped oxide (CDO or SiOC or SiOC:H) or fluorine-doped oxide (SiOF), or any combination thereof. The gate line isolation layer 406 may be deposited by using, for example, ALD, CVD (such as PECVD, RTCVD, LPCVD, etc.), PVD, sputtering, evaporation or any other suitable film deposition technology.

[0077] In some embodiments, before depositing the gate line isolation layer 406, a portion of the substrate 10 may be exposed inside the gate line gap. In some embodiments, after depositing the gate line isolation layer 406, a portion of the gate line isolation layer 406 at the bottom of the gate line gap may be removed by a dry or wet etching process to expose the portion of the substrate 10 inside the gate line gap.

[0078] The gate line isolation structure 40 further includes a GLS conductive core 408 disposed inside the gate line gap. The GLS conductive core 408 fills the gate line gap with a conductive material and can contact the exposed portion of the substrate inside the gate line gap to form an electrical connection with the substrate 10 .

[0079] The gate line isolation layer 406 and the GLS conductive core 408 penetrate the portion of the top selection gate layer 30 to form a first isolation structure 402 , and the gate line isolation layer 406 and the GLS conductive core 408 penetrate the portion of the stacked layer 20 to form a second isolation structure 404 .

[0080] In addition, the contact layer 4022 where the first isolation structure 402 contacts the top selection gate layer is a part of the gate line isolation layer 406 .

[0081] like Fig. 9 As shown, in some embodiments, the semiconductor device also includes: a first dielectric layer 60, as an etching stop layer, located on the top selection gate layer 30, the first dielectric layer 60 and the contact layer 4022 include different insulating media, for example, the contact layer 4022 includes silicon oxide, and the first dielectric layer 60 includes silicon nitride. By configuring different insulating media for the first dielectric layer 60 and the contact layer 4022, the etching operation on the first dielectric layer 60 has less impact on the contact layer 4022 adjacent thereto, thereby reducing the probability of the gate line isolation layer 406 being damaged and causing leakage.

[0082] like Fig.14 As shown, in some embodiments, the semiconductor device further includes: a channel local contact (C1CH) 70, which penetrates the first dielectric layer and is arranged corresponding to the channel structure 50 to be electrically connected to the channel structure 50, so that each channel local contact 70 is electrically connected to a bit line contact for bit line fan-out.

[0083] like Figure 6 As shown, in some embodiments, the present invention further includes: a second dielectric layer 90 located between the top selection gate layer 30 and the first dielectric layer 60 .

[0084] In some embodiments, to form the communicating local contact 70, a second dielectric layer 90 may be formed on the top select gate layer 30 by depositing a dielectric material such as silicon oxide or silicon nitride on top of the top select gate layer 30 using one or more thin film deposition processes such as CVD, PVD, ALD, or any combination thereof. A channel local contact 70 is formed by etching a channel local contact window 702 through the first dielectric layer 60 and the cap layer 120 (and any other ILD layer) on the upper side of the second dielectric layer 90 using wet etching and / or dry etching (e.g., RIE), and then filling the channel local contact window 702 with a conductive material using one or more thin film deposition processes (e.g., ALD, CVD, PVD, any other suitable process, or any combination thereof).

[0085] In some embodiments, Fig.11 As shown, the cap layer 120 is first etched to form a partial channel local contact window 702A.

[0086] In some embodiments, Fig.12 As shown, the first dielectric layer 60 is further etched to form a complete channel local contact window 702 .

[0087] like Figure 7 As shown, in some embodiments, the semiconductor device further includes: a connection structure 80, which passes through the top selection gate layer 30, one end of the connection structure 80 contacts the channel structure 50, and the other end of the connection structure 80 contacts the channel local contact 70, and the connection structure 80 passes through the second dielectric layer 90 to contact the channel local contact 70, so that the channel local contact 70 is electrically connected to the channel structure 50.

[0088] After forming the channel structure 50, a connection structure 80 penetrating the second dielectric layer 90 and the top selection gate layer 30 may be formed at a position corresponding to the channel structure 50 by, for example, a dry etching process or a combination of dry and wet etching processes. In addition, other manufacturing processes may also be performed, such as a patterning process including photolithography, cleaning, and chemical mechanical polishing. The connection structure 80 may have a cylindrical or pillar shape similar to the channel structure 50 in the Z direction.

[0089] The connection structure 80 includes a connection structure opening, a conductive layer formed on the inner wall of the connection structure opening, and an opening filling layer, wherein the conductive layer is electrically connected to the channel structure 50, and the conductive layer can be formed on the inner wall of the connection structure opening by one or more thin film deposition processes such as CVD, PVD, ALD or any combination thereof. In some embodiments, the conductive layer may include silicon, such as amorphous silicon, polycrystalline silicon or single crystal silicon, and the material of the conductive layer may include but is not limited to P-type doped polycrystalline silicon. In addition, the channel structure 50 also includes a top contact structure 512 located at the top of the structure, and the top contact structure 512 is configured to provide electrical contact to the channel structure 50. The top contact structure 512 may be amorphous silicon or polycrystalline silicon, and may include metal, metal alloy and / or metal silicide, such as tungsten, titanium, tantalum, tungsten nitride, titanium nitride, tantalum nitride, nickel silicide, cobalt silicide, tungsten silicide, titanium silicide or a combination thereof. As an option, the conductive layer of the connection structure 80 may be prepared using the same material as the top contact structure 512.

[0090] In some embodiments, the semiconductor device may be a NAND memory, and the top contact structure 512 serves as a drain of a NAND memory string.

[0091] like Figure 5As shown, in some embodiments, the semiconductor device further includes: a top selection gate cut line 130 , which is located between the first dielectric layer 60 and the stacked layer 20 and passes through the top selection gate layer 30 , and the top selection gate cut line 130 and the first dielectric layer 60 include the same or different insulating media.

[0092] like Figure 7 As shown, the top selection gate cut 130 and the connection structure 80 are arranged in parallel. By making the size of the connection structure 80 in the Y direction smaller than the opening size of the top of the channel structure 50 located on the side away from the substrate 10, it is more conducive to forming the top selection gate cut 130 arranged in parallel with the connection structure 80 in the Y direction in the three-dimensional storage structure.

[0093] In some embodiments, the semiconductor device further includes: a third dielectric layer 140 disposed between the top selection gate layer 30 and the stacked layer 20,

[0094] The top selection gate cut line 130 penetrates the top selection gate layer 30 and extends into the third dielectric layer 140 , wherein a top selection transistor controlled by the top selection gate layer 30 may be formed in a subsequent process.

[0095] In some embodiments, the top select gate cut line 130 may be formed by a photolithography process and an etching process, and the etching process may include any suitable dry etching, wet etching, and / or a combination thereof.

[0096] In some embodiments, the portion of the gate line isolation structure 40 that passes through the stacked layer 20 is a second isolation structure 404 , and along a direction parallel to the first dielectric layer 60 , the width of the first isolation structure 402 is greater than the width of the second isolation structure 404 .

[0097] In this embodiment, in the Y direction, by configuring the width of the first isolation structure 402 to be greater than the width of the second isolation structure 404, the thickness of the gate line isolation layer 406 of the first isolation structure 402 can be increased to further reduce the probability of electrical damage to the gate line isolation structure 40.

[0098] In some embodiments, the semiconductor device includes a core area CA (Core Array) and a staircase area SS (Staircase), and the top selection gate layer 30 is arranged in the core area. The semiconductor device also includes: a first contact structure 100, which is arranged in the core area and penetrates the first dielectric layer 60 and the second dielectric layer 90, and extends to the top selection gate layer 30.

[0099] In some embodiments, the semiconductor device further includes: a second contact structure 110 disposed in the stepped region, penetrating the first dielectric layer 60 , and extending to the step of the stepped region.

[0100] The core area CA (Core Array) includes the area where the channel structure 50 and the gate line isolation structure 40 are located. Fig.19 As shown, the core area CA further includes a top selection gate cut line 130 , and a channel local contact 70 divided by the top selection gate cut line 130 .

[0101] The staircase region SS (Staircase) includes a step region in the stacked structure 20. Based on the setting of the step region, a second contact structure 110 is used to lead out the gate electrode layer on each step in the stacked structure 20 and connect it to the bit line.

[0102] In addition, through the gate line isolation structure 50 , the gate line isolation structure 50 vertically penetrates the stacked layer 20 and is configured to separate the memory block into a plurality of memory fingers.

[0103] In some embodiments, since the formation of the channel local contact window 702 and the other first contact openings 1006 and the second contact openings 1106 are all achieved through etching operations on the first dielectric layer, only one mask template can be used to form the channel local contact window and other contact openings. This method can reduce the use of mask templates and reduce process steps.

[0104] In some other embodiments, different masks may be used to etch the channel local contact window 702 , the first contact opening 1006 , and the second contact opening 1106 .

[0105] In some embodiments, the first contact structure 100 includes a first substructure 1002 passing through the first dielectric layer 60 and a second substructure 1004 passing through the dielectric layer 90 .

[0106] In some embodiments, in a semiconductor structure provided with a cap layer 120 , the first contact structure 100 includes a first substructure 1002 passing through the cap layer 120 and the first dielectric layer 60 , and a second substructure 1004 passing through the dielectric layer 90 .

[0107] like Fig.13 As shown, the first substructure 1002 corresponds to the first contact opening 1006 , and the second sub-interface 1004 corresponds to the first sub-hole 1008 .

[0108] In some embodiments, along a direction parallel to the first dielectric layer 60 , at the position where the first substructure 1002 and the second substructure 1004 are connected, the width of the first substructure 1002 is greater than the width of the second substructure 1004 , that is, a step structure is formed at the position where the first substructure 1002 and the second substructure 1004 are connected.

[0109] In other embodiments, the first substructure 1002 and the second substructure 1004 are an integrated structure, that is, there is no step structure at the position where the first substructure 1002 and the second substructure 1004 are connected, but the width of the first contact opening 100 along the Y direction gradually decreases in the direction close to the substrate 10, forming a truncated cone structure, such as Fig.18 A first contact structure 100 is shown.

[0110] The first contact structure 100 is specifically a top selection gate layer contact structure (TSGCT), which is used to achieve electrical connection with the top selection gate layer 30 .

[0111] In this embodiment, the width of the first substructure 1002 is configured to be greater than the width of the second substructure 1004 at the position where the first substructure 1002 and the second substructure 1004 are connected, that is, the width of the structure gradually decreases in the direction close to the substrate 10, so as to facilitate the setting of the adjacent connection structure 80 while ensuring electrical connection.

[0112] In some embodiments, the second contact structure 110 includes a third substructure 1102 penetrating the first dielectric layer 60 and a fourth substructure 1104 extending to the step of the stepped region.

[0113] like Fig.13 As shown, the third substructure 1102 corresponds to the second contact opening 1106 , and the fourth sub-interface 1104 corresponds to the second sub-hole 1108 .

[0114] Among them, Fig.14 As shown, the second contact structure 110 is specifically a word line contact structure, and the stacked layer 20 may have a plurality of second contact structures 110, which are formed in the third dielectric layer 150 and are placed on the corresponding word line layer 202 in the step region SS to connect to the word line layer 202, and the second contact structure 110 may include W, Co or other suitable conductive materials. In some embodiments, a transition layer may also be formed between the second contact structure 110 and the third dielectric layer 109.

[0115] In some embodiments, along a direction parallel to the first dielectric layer 60, at the position where the third substructure 1102 and the fourth substructure 1104 are connected, the width of the third substructure 1102 is configured to be greater than the width of the fourth substructure 1104, that is, a step structure is formed at the position where the third substructure 1102 and the fourth substructure 1104 are connected, wherein the fourth substructure 1104 is connected to the corresponding word line layer 202 by extending toward the step area.

[0116] In this embodiment, at the position where the third substructure 1102 and the fourth substructure 1104 are connected, the width of the third substructure 1102 is configured to be larger than the width of the fourth substructure 1104, that is, the width of the structure gradually decreases along the direction close to the substrate 10 to ensure the reliability of the connection with the corresponding word line layer 202.

[0117] In some embodiments, along a direction parallel to the first dielectric layer 60, a portion of the channel local contact 70 passing through the first dielectric layer 60 has a first width, a portion of the first contact structure 100 passing through the first dielectric layer 60 has a second width, and a portion of the second contact structure 110 passing through the first dielectric layer 60 has a third width; wherein the second width is greater than the first width, and the first width is greater than the third width.

[0118] In this embodiment, the local contact 70 is formed through a portion of the first dielectric layer 60 by defining a trench.

[0119] In some embodiments, the method further includes: a gap contact structure 408 penetrating through the first dielectric layer 60 and communicating with the gate line isolation structure 40 .

[0120] like Fig.16 As shown, an etching operation is performed on the cap layer 120 and the first dielectric layer 60 in the region corresponding to the gate line isolation structure 40 to form a gate lead hole 406 .

[0121] like Fig.17 As shown, a conductive material is filled in the gate lead hole 408 to form a gap contact structure 408, so as to realize that the gate line isolation structure 40 is electrically led out as an ACS and electrically connected to other external structures of the semiconductor device.

[0122] In some embodiments, since the formation of the gate lead hole 408 and the channel local contact window 702, the formation of the first contact opening 1006 and the second contact opening 1106 are all achieved through etching operations on the first dielectric layer, only one mask template can be used to form the channel local contact window and other contact openings. This method can reduce the use of mask templates and reduce process steps.

[0123] In some other embodiments, different masks may be used to etch the gate lead hole 408 , the channel local contact window 702 , and the first contact opening 1006 and the second contact opening 1106 .

[0124] In some embodiments, the first dielectric layer 60 and the capping layer 120 include different insulating media; the first dielectric layer 60 and the second dielectric layer 90 include different insulating media.

[0125] If the first dielectric layer 60 is silicon carbide, the cap layer 120 and the second dielectric layer 90 may be silicon oxide, silicon oxynitride, TEOS or a combination thereof.

[0126] In the embodiment where the substrate 10 is retained, the gate line isolation structure 40 is used to provide an electrical connection from the front side of the device to the source of the memory array (eg, array common source (ACS)). Fig.15 As shown, in some embodiments, the substrate 10 is removed to expose a substrate end portion, where the substrate end portion is a portion where the channel structure 50 extends to the substrate.

[0127] Specifically, CMP, grinding, dry etching and / or wet etching may be used to remove the substrate 10 . A new semiconductor layer 160 is formed on the stacked layer 20 away from the top selection gate layer 30 .

[0128] In an embodiment in which the substrate 10 is removed, a new semiconductor layer 160 is formed, and the new semiconductor layer 160 can serve as a source layer. The gate line isolation structure 40 can extend to the source layer. The gate line isolation structure 40 can also include a conductive portion (not shown in the figure). The conductive portion can include a conductive material, and the conductive material can be a combination of one or more of tungsten, cobalt, copper, aluminum, doped silicon, and silicide. The conductive portion can extend to the source layer to be coupled to the source layer.

[0129] Among them, the semiconductor layer 160 serving as the source layer can be single crystal silicon, single crystal germanium, III-V compound semiconductor materials, II-VI compound semiconductor materials and other suitable semiconductor materials. In addition, it can be formed by a thin film deposition process, and the thin film deposition process can be a combination of one or more of chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) and electroplating process.

[0130] In addition, after removing the substrate 10 , the channel structure 50 may be exposed, and thus the formed source layer may contact the exposed channel structure to achieve coupling between the source layer and the channel layer 508 in the channel structure 50 .

[0131] On one side of the stacked layer 20 close to the substrate end, a doped semiconductor layer connecting the substrate ends of each channel structure 50 is formed.

[0132] In one embodiment, the material of the doped semiconductor layer includes N-type doped polysilicon.

[0133] In one embodiment, a laser annealing process is performed on the doped semiconductor layer.

[0134] In one embodiment, a peripheral circuit chip is connected to a side of the stack layer 20 away from the substrate 10 .

[0135] In some embodiments, the gate line isolation structure 40 extends into the new semiconductor layer 160 .

[0136] In some embodiments, the different insulating dielectrics include at least two of silicon nitride, insulating oxide, and silicon oxynitride.

[0137] According to an embodiment of the present disclosure, a semiconductor device includes: a stacked layer 20; a top selection gate layer 30, which is located on the stacked layer 20; a gate line isolation structure 40, which passes through the top selection gate layer 30 and the stacked layer 20, and the portion of the gate line isolation structure 40 that passes through the top selection gate layer 30 is a first isolation structure 402, and the first isolation structure 402 includes a contact layer 4022 in contact with the top selection gate layer; a channel structure 50, which passes through the stacked layer 20; a first dielectric layer 60, which is located on the top selection gate layer 30, and the first dielectric layer 60 and the contact layer 4022 include different insulating media; a channel local contact 70, which passes through the first dielectric layer and is arranged corresponding to the channel structure 50.

[0138] like Fig. 9 As shown, a semiconductor device according to another embodiment of the present disclosure includes: a stacked layer 20; a top selection gate layer 30, located on the stacked layer 20; a gate line isolation structure 40, penetrating the top selection gate layer 30 and the stacked layer 20; a channel structure 50, penetrating the stacked layer 20; a first dielectric layer 60, located on the top selection gate layer 30, and the first dielectric layer covers the gate line isolation structure; a channel local contact 70, penetrating the first dielectric layer, and arranged corresponding to the channel structure 50.

[0139] Fig. 20 is a flow chart for manufacturing a semiconductor device disclosed according to some embodiments of the present disclosure, comprising:

[0140] Step S2002, providing a substrate, the substrate comprising a substrate, a stacked layer located on the substrate, a top selection gate layer located on the stacked layer, a channel structure extending through the stacked layer to the substrate, and a gate line isolation structure extending through the top selection gate layer and the stacked layer to the substrate.

[0141] like Figure 2 As shown, a stacked layer 20 is formed on a substrate 10 .

[0142] like Figure 3 As shown, a channel structure 50 is formed extending through the stacked layer 20 to the substrate.

[0143] like Figure 4 As shown, a top select gate layer 30 is formed on the stacked layer 20 .

[0144] like Figure 5 As shown, a top select gate cut line 130 is formed through the top select gate layer 30 .

[0145] like Figure 6 As shown, a second dielectric layer 90 is formed on the top select gate layer 30 .

[0146] like Figure 7 As shown, a connection structure 80 is formed which passes through the top selection gate layer 30 and the second dielectric layer 90 and is connected to the channel structure 50 .

[0147] like Figure 8 As shown, a gate line isolation structure 40 is formed to extend through the top selection gate layer 30 and the stacked layer 20 to the substrate 10 .

[0148] Step S2004, forming a first dielectric layer, the first dielectric layer being located on the top selection gate layer as an etch stop layer.

[0149] like Fig. 9 As shown, an etch stop layer 60 is formed on the second dielectric layer 90 to cover the gate line isolation structure 40 .

[0150] like Fig.10 As shown, a capping layer 130 is formed on the first dielectric layer 60 .

[0151] Step S2006, forming a local channel contact, the local channel contact passes through the etch stop layer and is arranged corresponding to the channel structure.

[0152] In this embodiment, the base of the provided semiconductor device includes a stacked layer, a top selection gate layer located on the stacked layer, and a gate line isolation structure that penetrates the top selection gate layer and the stacked layer. After the gate line isolation structure is formed, a first dielectric layer is formed on the top selection gate layer as an etch stop layer, and a channel local contact is further formed on the etch stop layer. On the one hand, during the process of etching the etch stop layer to form a channel local contact window of the channel local contact, the gate line isolation structure is in a state of being covered by the etch stop layer. On the other hand, the etch stop layer adopts an insulating medium different from the contact layer of the gate line isolation structure. The etch stop layer serves as a dielectric layer to be etched, and the contact layer of the gate isolation structure serves as a dielectric layer to be protected. By reasonably setting the etching selectivity ratio of the two dielectrics, it is beneficial to reduce the influence of the etching operation of the etch stop layer on the contact layer of the gate line isolation structure, thereby improving the yield of the semiconductor device.

[0153] In some embodiments, forming a first dielectric layer includes: forming a dielectric layer on the top selection gate layer; planarizing the dielectric layer; and forming a first dielectric layer on the dielectric layer.

[0154] In some embodiments, the method further includes: forming a capping layer, wherein the capping layer is located on the first dielectric layer.

[0155] In some embodiments, the semiconductor device includes a core area (CA) and a step area (SS) to form a local channel contact, including: performing an etching operation on a cap layer and a first dielectric layer in the core area to form a local channel contact window; filling a conductive material in the local channel contact window to form a local channel contact.

[0156] In some embodiments, etching operations are performed on the cap layer and the first dielectric layer in the core region, including: etching the cap layer in the core region to form a local channel opening; etching the first dielectric layer in the local channel opening to form a local channel contact window.

[0157] like Fig.11 As shown, the cap layer 120 is etched using a first mask to form a local channel opening 702A.

[0158] like Fig.12 As shown, the first dielectric layer 60 is etched using a first mask to form a channel local contact window 702 .

[0159] In some embodiments, performing an etching operation on the cap layer and the first dielectric layer in the core region further includes:

[0160] like Fig.11 and Fig.12 As shown, the first mask is used to perform etching operations on the cap layer 120 and the first dielectric layer 60 in the core area, and the first contact opening 1006 is formed synchronously with the channel local contact window 702. The opening size of the first contact opening is larger than the window size of the channel local contact window.

[0161] like Fig.11 and Fig.12 As shown, a first mask is used to perform etching operations on the cap layer 120 and the first dielectric layer 60 in the step area, and a second contact opening 1106 is formed synchronously with the local contact window of the channel. Both the first contact opening and the second contact opening pass through the cap layer and the first dielectric layer and extend to the second dielectric layer 90.

[0162] In this embodiment, the first mask is used to simultaneously form the channel local contact window 702 , the first contact opening 1006 , and the second contact opening 1106 .

[0163] In some embodiments, after etching the cap layer and the first dielectric layer in the core area to form a local contact window of the channel, it also includes: etching the cap layer and the first dielectric layer in the core area to form a first contact opening, the opening size of the first contact opening is larger than the window size of the local contact window of the channel; etching the cap layer and the first dielectric layer in the step area to form a second contact opening.

[0164] In this embodiment, a first mask is used to form the channel local contact window 702 , and a second mask is used to form the first contact opening 1006 and the second contact opening 1106 .

[0165] In some embodiments, it also includes: performing an etching operation on the dielectric layer and the top selection gate layer in the first contact opening to form a first sub-hole; performing an etching operation on the dielectric layer and the stacked layer in the second contact opening to form a second sub-hole extending to the step of the step area.

[0166] like Fig.13 As shown, a first sub-hole 1008 is formed in the first contact opening 1006 , and a second sub-hole 1108 is formed in the second contact opening 1106 .

[0167] In some embodiments, filling the local contact window of the channel with a conductive material further includes: filling the first contact opening and the first sub-hole with a conductive material to form a first contact structure; and filling the second contact opening and the second sub-hole with a conductive material to form a first contact structure.

[0168] like Fig.14 As shown, a conductive material is filled in the first contact opening to form a first opening structure 1002 , and a conductive material is filled in the first sub-hole to form a first sub-hole structure 1004 . The first opening structure 1002 and the first sub-hole structure 1004 form a first contact structure 100 .

[0169] A conductive material is filled in the second contact opening to form a second opening structure 1102 , and a conductive material is filled in the second sub-hole to form a second sub-hole structure 1104 . The second opening structure 1102 and the second sub-hole structure 1104 form a second contact structure 110 .

[0170] In addition, if Fig.18 As shown, the first contact opening and the second contact opening 1106 directly extend to penetrate the dielectric layer and reach the top selection gate layer, correspondingly forming the first contact structure 100 and the second contact structure 110 .

[0171] In some embodiments, the method further includes: removing the substrate to expose an end portion of the substrate, where the end portion of the substrate is a portion where the channel structure extends to the substrate.

[0172] In some embodiments, the method includes forming a semiconductor layer on a side of the stacked layer away from the first dielectric layer, wherein the semiconductor layer covers an end portion of the substrate.

[0173] Furthermore, if Fig.15 As shown, the substrate is removed to expose the end of the substrate, and a semiconductor layer 160 connected to the end of the substrate is formed.

[0174] In some embodiments, the method further includes: etching the cap layer and the first dielectric layer in an area corresponding to the gate line isolation structure to form a gate lead hole; and filling the gate lead hole with a conductive material to form a gap contact structure.

[0175] like Fig.16 As shown, a gate lead hole 406 is formed in a region corresponding to the gate line isolation structure 40 .

[0176] like Fig.17 As shown, a conductive material is filled in the gate lead hole 406 to form a gap contact structure 408 .

[0177] In addition, an embodiment of the present application also provides a memory system. The memory system includes at least one semiconductor device described in any of the above embodiments, and a controller electrically connected to the memory, wherein the controller is also connected to an external host, and the external host can transmit user instructions and storage data to the controller, and the user instructions may include write instructions, erase instructions, and read instructions, etc. The controller can determine which storage location in the semiconductor device to write, erase, and read based on these contents.

[0178] For example, Fig.21 A block diagram of a memory system provided in an embodiment of the present disclosure. The memory system 2100 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a memory therein. Fig.21 As shown in , the memory system 2100 may include a host 2104 and a storage subsystem 2102, the storage subsystem 2102 includes one or more memories 2102A and a controller (controller) 2102B, and the memory 2102A includes a storage cell array and a plurality of page buffers. The host 2104 may be a processor (e.g., a central processing unit (CPU)) or a system on chip (SoC) (e.g., an application processor (AP)) of an electronic device. The host 2104 may be configured to send data to the memory 2102A or receive data from the memory 2102A.

[0179] The semiconductor device of the present disclosure is a memory 2102A, or a part of the memory 2102A. According to some embodiments, the controller 2102B is coupled to the memory 2102A and the host 2104, and is configured to control the memory. The controller 2102B can manage the data stored in the memory and communicate with the host 2104. In some embodiments, the controller 2102B is designed to operate in a low duty cycle environment, such as a secure digital (SD) card, a compact flash (CF) card, a universal serial bus (USB) flash drive, or other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc. In some embodiments, the controller 2102B is designed to operate in a high duty cycle environment SSD or embedded multimedia card (eMMC), which is used as a data storage device and enterprise storage device for mobile devices such as smart phones, tablet computers, laptop computers, etc. The controller 2102B can be configured to control the operation of the memory 2102A, such as read, erase and program operations. The controller 2102B may also be configured to manage various functions regarding data stored or to be stored in the memory 2102A, including but not limited to bad block management, garbage collection, logical to physical address conversion, wear leveling, etc. In some embodiments, the controller 2102B is also configured to process error correction codes (ECC) regarding data read from or written to the memory 2102A. The controller 2102B may also perform any other suitable functions, such as formatting the memory 2102A. The controller 2102B may communicate with an external device (e.g., a host 2104) according to a specific communication protocol. For example, the controller 2102B may communicate with an external device through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a peripheral component interconnect (PCI) protocol, a PCI Express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer small interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, a Firewire protocol, etc.

[0180] The controller 2102B and one or more memories 2102A can be integrated into various types of storage devices, for example, included in the same package (e.g., a universal flash storage (UFS) package or an eMMC package). That is, the storage subsystem 2102 can be implemented and packaged into different types of terminal electronic products.

[0181] Fig. 22 Schematic diagram of a memory card provided by an embodiment of the present disclosure. Fig. 22In one example shown in FIG. 2 , a controller 2102B and a single memory 2102A may be integrated into a memory card 2200. The memory card 2202 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 2202 may also include a processor that connects the memory card 2202 to a host (e.g., Fig.10 A memory card connector 2202 coupled to the host 1008).

[0182] Fig.23 A schematic diagram of a solid state drive (SSD) provided in an embodiment of the present disclosure. Fig.23 As shown in FIG. 2 , the controller 2102B and the plurality of memories 2102A may be integrated into the SSD 2300. The SSD 2300 may also include a processor that connects the SSD 2300 to a host (eg, Fig.21 The host 1004 in the memory card 2300 is coupled to an SSD connector 2302. In some embodiments, the storage capacity and / or operating speed of 2300 is greater than the storage capacity and / or operating speed of the memory card 2200.

[0183] It should be noted that the structure of the memory described above is only an exemplary structure, and other types of memories, or memories of other structures, are also applicable to the operating method of the present application.

[0184] The above description of specific embodiments will fully demonstrate the general nature of the present disclosure, so that others can easily modify and / or adjust such specific embodiments for various applications by applying knowledge within the technical scope of the art without excessive experimentation and without departing from the general concept of the present disclosure. Therefore, based on the teachings and guidance presented herein, such adjustments and modifications are intended to be within the meaning and scope of the equivalents of the disclosed embodiments. It should be understood that the wording or terminology herein is for illustrative purposes, not for limitation, so that the terms or wording of this specification will be interpreted by the technician in accordance with the teachings and guidance.

[0185] Embodiments of the present disclosure have been described above with the aid of functional building blocks, which illustrate implementation methods of specified functions and their relationships. The boundaries of these functional building blocks are arbitrarily defined herein for the purpose of convenience of description. Alternative boundaries may be defined as long as the specified functions and their relationships are appropriately performed.

[0186] The Summary and Abstract sections may set forth one or more, but not necessarily all, exemplary embodiments of the present disclosure as contemplated by the inventor(s), and thus, are not intended to limit the present disclosure and the appended claims in any way.

[0187] The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.

Claims

1. A semiconductor device, characterized in that: include: Stacking layers; a top select gate layer located on the stacked layers; a gate line isolation structure, which passes through the top selection gate layer and the stacked layer, wherein a portion of the gate line isolation structure that passes through the top selection gate layer is a first isolation structure, and the first isolation structure includes a contact layer that contacts the top selection gate layer; A channel structure, penetrating the stacked layers; a first dielectric layer located on the top selection gate layer, the first dielectric layer and the contact layer comprising different insulating media; The channel local contact penetrates the first dielectric layer and is arranged corresponding to the channel structure.

2. The semiconductor device according to claim 1, wherein: Also includes: A connection structure penetrates the top selection gate layer, one end of the connection structure contacts the channel structure, and the other end of the connection structure contacts the channel local contact.

3. The semiconductor device according to claim 2, characterized in that Also includes: A second dielectric layer is located between the top selection gate layer and the first dielectric layer, and the connection structure contacts the channel local contact through the second dielectric layer.

4. The semiconductor device according to claim 3, characterized in that A portion of the gate line isolation structure that passes through the stacked layer is a second isolation structure. Along a direction parallel to the first dielectric layer, a width of the first isolation structure is greater than a width of the second isolation structure.

5. The semiconductor device according to claim 3, characterized in that The semiconductor device comprises a core region and a step region, the top selection gate layer is arranged in the core region, and the semiconductor device further comprises: a first contact structure, disposed in the core region, penetrating the first dielectric layer and the second dielectric layer, and extending to the top selection gate layer; The second contact structure is arranged in the step region, penetrates the first dielectric layer, and extends to the step of the step region.

6. The semiconductor device according to claim 5, characterized in that The first contact structure includes a first substructure passing through the first dielectric layer and a second substructure passing through the dielectric layer, and along a direction parallel to the first dielectric layer, at a position where the first substructure and the second substructure are connected, a width of the first substructure is greater than a width of the second substructure; The second contact structure includes a third substructure passing through the first dielectric layer and a fourth substructure extending to the steps of the step area. Along a direction parallel to the first dielectric layer, at a position where the third substructure and the fourth substructure are connected, a width of the third substructure is greater than a width of the fourth substructure.

7. The semiconductor device according to claim 5, characterized in that Along a direction parallel to the first dielectric layer, a portion of the channel local contact passing through the first dielectric layer has a first width, a portion of the first contact structure passing through the first dielectric layer has a second width, and a portion of the second contact structure passing through the first dielectric layer has a third width; The second width is greater than the first width, and the first width is greater than the third width.

8. The semiconductor device according to claim 1, wherein: Also includes: A gap contact structure penetrates the first dielectric layer and is connected to the gate line isolation structure.

9. The semiconductor device according to claim 1, wherein: Also includes: The semiconductor layer is arranged on a side of the stacked layer away from the top selection gate layer.

10. The semiconductor device according to claim 3, wherein: Also includes: A cap layer is disposed on the first dielectric layer, and the channel local contact passes through the cap layer and the first dielectric layer and contacts the channel structure.

11. The semiconductor device according to claim 10, characterized in that The first dielectric layer and the cap layer include different insulating media; The first dielectric layer and the second dielectric layer include different insulating media.

12. The semiconductor device according to any one of claims 1 to 11, characterized in that Also includes: A top selection gate cut line is located between the first dielectric layer and the stacked layer and penetrates the top selection gate layer. The top selection gate cut line and the first dielectric layer include the same or different insulating medium.

13. The semiconductor device according to claim 12, characterized in that The different insulating medium includes at least two of silicon nitride, insulating oxide and silicon oxynitride.

14. A semiconductor device, characterized in that: include: Stacking layers; a top select gate layer located on the stacked layers; A gate line isolation structure, penetrating the top selection gate layer and the stacked layer; A channel structure, penetrating the stacked layers; A first dielectric layer, located on the top selection gate layer, and the first dielectric layer covers the gate line isolation structure; The channel local contact penetrates the first dielectric layer and is arranged corresponding to the channel structure.

15. A method for preparing a semiconductor device, characterized in that: include: Providing a substrate, the substrate comprising a substrate, a stacked layer located on the substrate, a top selection gate layer located on the stacked layer, a channel structure extending through the stacked layer to the substrate, and a gate line isolation structure extending through the top selection gate layer and the stacked layer to the substrate; forming a first dielectric layer, the first dielectric layer being located on the top select gate layer; A channel local contact is formed, wherein the channel local contact passes through the first dielectric layer and is arranged corresponding to the channel structure.

16. The preparation method according to claim 15, characterized in that: The forming of the first dielectric layer comprises: forming a second dielectric layer on the top select gate layer; performing a planarization process on the second dielectric layer; The first dielectric layer is formed on the second dielectric layer.

17. The preparation method according to claim 16, characterized in that: Also includes: A capping layer is formed, wherein the capping layer is located on the first dielectric layer.

18. The preparation method according to claim 17, characterized in that: The semiconductor device comprises a core region and a step region, and the forming of a channel local contact comprises: Performing an etching operation on the cap layer and the first dielectric layer in the core region to form a channel local contact window; A conductive material is filled in the local contact window of the channel to form the local contact of the channel.

19. The preparation method according to claim 18, characterized in that: The etching operation on the cap layer and the first dielectric layer in the core region includes: Performing an etching operation on the cap layer in the core region to form a partial opening of the channel; The first dielectric layer is etched in the local channel opening to form the channel local contact window.

20. The preparation method according to claim 18, characterized in that: The etching operation on the cap layer and the first dielectric layer in the core region further includes: forming a first contact opening in the core region synchronously with the channel local contact window, wherein the opening size of the first contact opening is larger than the window size of the channel local contact window; and A second contact opening is formed in the step region synchronously with the channel local contact window. Both the first contact opening and the second contact opening pass through the cap layer and the first dielectric layer and extend to the second dielectric layer.

21. The preparation method according to claim 18, characterized in that: After etching the cap layer and the first dielectric layer in the core region to form a channel local contact window, the method further includes: Etching the cap layer and the first dielectric layer in the core region to form a first contact opening, wherein the opening size of the first contact opening is larger than the window size of the channel local contact window; The cap layer and the first dielectric layer are etched in the stepped region to form a second contact opening.

22. The preparation method according to claim 20 or 21, characterized in that: Also includes: Performing an etching operation on the second dielectric layer and the top selection gate layer in the first contact opening to form a first sub-hole; An etching operation is performed on the second dielectric layer and the stacked layer in the second contact opening to form a second sub-hole extending to a step of the stepped region.

23. The preparation method according to claim 22, characterized in that: The method of filling the local contact window of the channel with a conductive material further comprises: Filling the first contact opening and the first sub-hole with the conductive material to form a first contact structure; The second contact opening and the second sub-hole are filled with the conductive material to form a second contact structure.

24. The preparation method according to any one of claims 17 to 21, characterized in that Also includes: In an area corresponding to the gate line isolation structure, etching the cap layer and the first dielectric layer to form a gate lead hole; A conductive material is filled in the gate lead hole to form a gap contact structure.

25. The preparation method according to any one of claims 15 to 21, characterized in that: Also includes: The substrate is removed to expose a substrate end portion, where the substrate end portion is a portion of the channel structure extending to the substrate.

26. The preparation method according to claim 25, characterized in that: Also includes: A semiconductor layer is formed on a side of the stacked layer away from the first dielectric layer, and the semiconductor layer covers the end of the substrate.

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