Gallium oxide Schottky diode with passivated two-dimensional semimetal insertion layer and preparation method of gallium oxide Schottky diode

Abstract

The invention discloses a gallium oxide Schottky diode with a passivated two-dimensional semimetal insertion layer and a preparation method thereof, and the gallium oxide Schottky diode comprises a substrate which is made of N-type heavily doped beta-Ga2O3 with different crystal orientations; the epitaxial layer is located on the substrate; wherein the material of the epitaxial layer is N-type unintentionally doped beta-Ga2O3; the two-dimensional semimetal growth insertion layer is located on the epitaxial layer; the protection layer is located on the two-dimensional semimetal growth insertion layer, and the orthographic projection of the protection layer and the orthographic projection of the two-dimensional semimetal growth insertion layer are overlapped in the direction perpendicular to the substrate; the terminal structure is located on the epitaxial layer, the terminal structure is of an annular structure, and the terminal structure is arranged around the two-dimensional semimetal growth insertion layer and the protection layer; the anode covers the protective layer and a part of the terminal structure; and the cathode is positioned on one side, deviating from the epitaxial layer, of the substrate. According to the beta-Ga2O3-based SBD device provided by the invention, the two-dimensional material can adjust the energy band of the Ga2O3 surface by virtue of the inherent Van der Waals surface, and endow the Schottky barrier with extremely strong flexibility.

Description

Technical Field

[0001] The invention belongs to the field of semiconductor technology, and in particular relates to a two-dimensional semi-metal insertion layer passivated gallium oxide Schottky diode and a preparation method thereof. Background Art

[0002] With the rapid development of power electronics technology, Ga2O3 has attracted extensive attention as an emerging ultra-wide bandgap oxide semiconductor. It has the advantages of large bandgap, good thermal stability, high breakdown field strength, and good radiation resistance, and is an ideal candidate material for high-frequency and high-power devices. Gallium oxide has five different phases of isomers: α, β, γ, δ, and ε (κ). Among them, β-Ga2O3 is the first thermodynamically stable phase, and the other phases are metastable. Compared with third-generation semiconductor materials such as GaN and SiC, β-Ga2O3 has an ultra-wide quasi-direct band gap (~4.8eV), extremely high breakdown field strength (8MV / cm) and electron saturation drift velocity (2×10 7 cm / s), and its Baliga figure of merit (BFOM) is 4 times that of gallium nitride and 10 times that of silicon carbide. These excellent properties have made Schottky barrier diodes (SBDs) based on β-Ga2O3 gradually become a research hotspot in the field of power devices. Among them, monoclinic β-Ga2O3 has large anisotropic electrical and optical properties, and the surface potential energy of different crystal orientations is different, so the metal-semiconductor contact of β-Ga2O3 with different crystal orientations has obvious differences. At the same time, the electrical and optoelectronic properties of Schottky devices prepared in different directions will also change with the crystal orientation. Therefore, a unified electrical contact modulation method is needed to modulate the surface potential energy and realize β-Ga2O3 Schottky devices with different crystal orientations.

[0003] In the prior art, as a key unit of power control, the physical and chemical properties of the metal-semiconductor interface structure in SBD determine the charge conduction mechanism. The quality of the metal-semiconductor contact plays a decisive role in achieving the ideal characteristics of higher breakdown voltage and lower on-resistance: Among them, the surface state or metal-induced gap state plays a key role in the Schottky barrier formation mechanism. The ionization of defective donors on the surface will cause the turn-on voltage to drift and the breakdown voltage to drop, causing the instability of the power device. At the same time, the atomic structure and physical and chemical property fluctuations of the gold-semiconductor contact interface will also aggravate the inhomogeneity of the Schottky barrier (SBH), thereby causing changes in transport properties. Therefore, how to effectively improve the non-ideal surface state and gap state of the gold-semiconductor interface has always been an important challenge that gallium oxide Schottky devices urgently need to break through. Studies have found that in wide bandgap semiconductor-based SBD devices, surface pretreatment can reduce Ga2O3 surface defects and modulate surface energy band bending. Among them, Professor Long Shibing's research group reduced the impurity oxygen content on the Ga2O3 surface and the related O 2p hybrid orbital density by surface etching and reducing the contact between the surface and air, thereby improving the surface work function. The Schottky device prepared has a power of more than 1GW / cm 2Power quality factor (see Q. He, W. Hao, X. Zhou, Y. Li, K. Zhou, C. Chen, W. Xiong, G. Jian, G. Xu, X. Zhao, et al. Over 1 GW / cm2 vertical Ga2O3 Schottky barrier diodes without edge termination. IEEE Electron Device Letters, 2022, 43, 264.). Professor Ye Jiandong's research group used piranha solution and oxygen plasma treatment after etching the Ga2O3 surface to reduce the trap density associated with divacancies, thereby alleviating the surface energy band bending and improving the interface transport properties (see Z. Wang, X. Yu, H. Gong, T. Hu, Y. Zhang, X. Ji, F. Ren, S. Gu, Y. Zheng, R. Zhang, AY Kuznetsov, J. Ye. Identification and suppression of majority surface states in the dry-etched β-Ga2O3. Journal of Physical Chemistry Letters, 2022, 13, 7094.). Professor Zheng Xuefeng's research group found that low-temperature annealing after evaporation of Ni anode can not only form partial p-type NiO, but also reduce the trap state density and surface adsorbed carbon at the Ni-Ga2O3 interface, thereby reducing the on-state resistance and increasing the breakdown voltage (see Y. Hong, X. Zheng, Y. He, F. Zhang, X. Zhang, X. Wang, J. Li, D. Wang, X. Lu, H. Han, X. Ma, Y. Hao. The optimized interface characteristics of β-Ga2O3 Schottky barrier diode with low temperature annealing. Applied Physics Letters, 2021, 119, 132103.). It can be seen that the interface characteristics between Ga2O3 and metal significantly affect the surface energy band structure, and the physical and chemical process of surface treatment can passivate surface defects, improve interface orderliness and reduce environmental adsorption.

[0004] However, for SBD devices, the "disorder" of the interface significantly affects the surface energy band structure, and the physical and chemical properties of the metal semiconductor interface structure have an important influence on the device performance. The existing technology uses the physical and chemical process of surface treatment to passivate surface defects, thereby improving the orderliness of the interface and reducing environmental adsorption. However, it is difficult to avoid long-term air contact in the preparation of SBD devices. The local diffusion of metal atoms in the evaporation process and the reaction of the Ga2O3 surface are likely to form an uneven gap state. After metal deposition, the chemical adsorption state of the anode edge and the Ga2O3 surface may still change. The adsorption and desorption of oxygen ions at the interface can adjust the surface filling state many times, and even increase oxygen vacancy traps to cause Fermi pinning. This rough contact interface and the possibility of repeated defects exacerbate the unevenness of the Schottky barrier, causing the output current of the Schottky device to deviate from the ideal transport characteristics. At the same time, the traditional metal evaporation method cannot overcome the direct physical contact between metal and Ga2O3 from the root, and it is difficult to avoid the influence of surface potential energy on the gold-semiconductor contact. Therefore, the development of surface defect passivation technology is an important path to achieve high-quality gold-semiconductor interfaces and improve the reliability of gallium oxide power devices.

[0005] It is worth noting that two-dimensional (2D) materials, with their inherent van der Waals (vdW) surfaces, can form mixed-dimensional heterojunctions with atomically flat interfaces with wide bandgap materials by growth or transfer, which can provide great flexibility for band adjustment and modulation of Schottky barriers on the Ga2O3 surface. Junxue Ran et al. used graphene interlayers in GaN-based SBD structures and confirmed the role of graphene interlayers in improving the uniformity of Schottky barriers (see J. Ran, R. He, L. Wang, B. Liu, X. Ji, J. Su, J. Wang, J. Li, T. Wei. Improved barrier homogeneity in Pt / Al0.75Ga0.25N Schottky barrier diodes by graphene interlayer. Journal of Physics D: Applied Physics, 2022, 55, 304001.). Yuji Zhao et al. grew a hexagonal boron nitride (BN) insertion layer on the surface of the Ga2O3 device, passivated surface defects, reduced leakage current, and increased the SBD breakdown voltage to 1035V while increasing the turn-on voltage (see M.Xu, A.Biswas, T.Li, Z.He, S.Luo, Z.Mei, J.Zhou, C.Chang, ABPuthirath, R.Vajtai, PMAjayan, Y.Zhao.Verticalβ-Ga2O3metal-insulator-semiconductor diodes with an ultrathin boron nitrideinterlayer.Applied Physics Letters, 2023, 23, 232107.). Chloe Leblanc et al. used two-dimensional P-type materials to study their electrical transport on different crystal orientation surfaces of Ga2O3 (Vertical van der Waalsheterojunction diodes comprising 2D semiconductors on 3Dβ-Ga2O3, Nanoscale, 2023, 15, 9964). However, due to the large thickness of the transferred material, the band gap and affinity of different P-type materials vary greatly, and in this work, the P-type material is only used as an independent unit in the PN structure instead of an inserted modified structure, so the law of modulating the surface potential energy cannot be obtained, and the surface regulation effect of two-dimensional semi-metallic materials is not explored. Therefore, how to design on the Ga2O3 surface is of great significance for improving the performance of SBD and modulating its surface potential energy. Summary of the invention

[0006] In order to solve the above problems existing in the prior art, the present invention provides a two-dimensional semi-metal insertion layer passivated gallium oxide Schottky diode and a preparation method thereof. The technical problem to be solved by the present invention is achieved by the following technical solutions:

[0007] In a first aspect, the present invention provides a two-dimensional semi-metal insertion layer passivated gallium oxide Schottky diode, comprising:

[0008] Substrate, the material of the substrate includes N-type heavily doped β-Ga2O3 with different crystal orientations;

[0009] An epitaxial layer is located on the substrate; wherein the material of the epitaxial layer includes N-type unintentionally doped β-Ga2O3;

[0010] A two-dimensional semi-metal growth insertion layer is located on the epitaxial layer;

[0011] A protective layer is located on the two-dimensional semi-metal growth insertion layer, and along a direction perpendicular to the substrate, the protective layer overlaps with the orthographic projection of the two-dimensional semi-metal growth insertion layer;

[0012] A terminal structure is located on the epitaxial layer, the terminal structure is a ring structure, and is arranged around the two-dimensional semi-metal growth insertion layer and the protective layer;

[0013] an anode, covering the protective layer and a portion of the terminal structure;

[0014] The cathode is located on the side of the substrate facing away from the epitaxial layer.

[0015] In a second aspect, the present invention further provides a two-dimensional semi-metal insertion layer passivated gallium oxide Schottky diode and a preparation method thereof, comprising:

[0016] Providing a substrate with different crystal orientations; the material of the substrate includes N-type heavily doped β-Ga2O3;

[0017] Growing an epitaxial layer on a substrate; wherein the material of the epitaxial layer includes N-type unintentionally doped β-Ga2O3;

[0018] Cleaning the upper surface of the epitaxial layer, and growing a two-dimensional semi-metal growth insertion layer on the cleaned upper surface of the epitaxial layer;

[0019] A protective layer is prepared by transfer on the two-dimensional semi-metal growth insertion layer;

[0020] A cathode is prepared on a side of the substrate facing away from the epitaxial layer;

[0021] Performing patterning on the protective layer and the two-dimensional semi-metal growth insertion layer, etching away a portion of the stacked protective layer and the two-dimensional semi-metal growth insertion layer, so that the stacked protective layer and the two-dimensional semi-metal growth insertion layer have an orthographic projection on the substrate that is circular; and preparing a terminal structure around the stacked protective layer and the two-dimensional semi-metal growth insertion layer;

[0022] An anode is prepared on the protective layer and a portion of the terminal structure.

[0023] Beneficial effects of the present invention:

[0024] The present invention provides a two-dimensional semi-metal insertion layer passivated gallium oxide Schottky diode and a preparation method thereof, which is stacked with a substrate, an epitaxial layer, a two-dimensional semi-metal growth insertion layer and a protective layer, the epitaxial layer is made of β-Ga2O3, a two-dimensional semi-metal growth insertion layer is arranged on the epitaxial layer, and a protective layer is arranged on the two-dimensional semi-metal growth insertion layer to protect the two-dimensional semi-metal growth insertion layer; wherein a terminal structure is arranged around the two-dimensional semi-metal growth insertion layer and the protective layer, an anode is arranged on the protective layer and the terminal structure, and a cathode is arranged on the side of the substrate away from the epitaxial layer. In this way, the current researchers use in-situ BN growth to passivate Ga2O3 surface defects, and the SBD breakdown voltage is improved under the premise of increasing the turn-on voltage; while the use of P-type two-dimensional materials cannot effectively modulate the surface potential energy, thereby changing the gold-semiconductor contact characteristics. In the β-Ga2O3-based SBD device provided in this embodiment, the 2D material can give extremely strong flexibility to the band adjustment and Schottky barrier modulation of the Ga2O3 surface by virtue of the inherent van der Waals (vdW) surface. Specifically, during the two-dimensional van der Waals epitaxial growth kinetics, atomic reconstruction will first occur on the Ga2O3 surface, resulting in a flat surface structure such as a Ga double layer to compensate for surface dangling bonds. The epitaxially grown two-dimensional semimetal is regularly arranged and laterally expanded under the induction of the reconstructed surface and its buffer layer. Therefore, on the one hand, the surface reconstruction of the Ga2O3 material itself reduces surface defects and reduces unnecessary charge capture during device operation. The van der Waals gap between the two-dimensional material can avoid direct contact between the metal semiconductor and the metal semiconductor, reduce the disorder of the interface, and improve the uniformity and stability of the metal-semiconductor interface. On the other hand, the van der Waals gap cannot propagate non-polar potential energy, but can shield the surface potential of Ga2O3 with different crystal orientations, thereby reducing the anisotropy of the metal-semiconductor contact from the root and helping to achieve unified electrical regulation.

[0025] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 It is a schematic structural diagram of a two-dimensional semi-metal insertion layer passivated gallium oxide Schottky diode provided by an embodiment of the present invention;

[0027] Figure 2 It is a schematic diagram of a two-dimensional semi-metal insertion layer passivated gallium oxide Schottky diode and a preparation method thereof provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0028] The present invention is further described in detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.

[0029] See also Figure 1 , Figure 1 1 is a schematic diagram of a two-dimensional semi-metal insertion layer passivated gallium oxide Schottky diode provided by an embodiment of the present invention. The present invention provides a two-dimensional semi-metal insertion layer passivated gallium oxide Schottky diode, comprising:

[0030] A substrate 10, wherein the material of the substrate 10 includes N-type heavily doped β-Ga2O3 with different crystal orientations;

[0031] The epitaxial layer 20 is located on the substrate 10; wherein the material of the epitaxial layer 20 includes N-type unintentionally doped β-Ga2O3;

[0032] A two-dimensional semi-metal growth insertion layer 30 is located on the epitaxial layer 20;

[0033] The protective layer 40 is located on the two-dimensional semi-metal growth insertion layer 30, and along a direction D1 perpendicular to the substrate, the protective layer 40 overlaps with the orthographic projection of the two-dimensional semi-metal growth insertion layer 30;

[0034] The terminal structure 50 is located on the epitaxial layer 20. The terminal structure 50 is a ring structure and is arranged around the two-dimensional semi-metal growth insertion layer 30 and the protective layer 40.

[0035] an anode 60 covering the protective layer 40 and at least a portion of the terminal structure 50;

[0036] The cathode 70 is located on a side of the substrate 10 facing away from the epitaxial layer 20 .

[0037] For more details, please see Figure 1The present invention provides a two-dimensional semi-metal insertion layer passivated gallium oxide Schottky diode, which is stacked with a substrate 10, an epitaxial layer 20, a two-dimensional semi-metal growth insertion layer 30, and a protective layer 40; wherein a terminal structure 50 is arranged around the two-dimensional semi-metal growth insertion layer 30 and the protective layer 40, an anode 60 is arranged on the protective layer 40 and the terminal structure 50, and a cathode 70 is arranged on the side of the substrate 10 away from the epitaxial layer 20; the material of the epitaxial layer 20 is β-Ga2O3, a two-dimensional semi-metal growth insertion layer 30 is arranged on the epitaxial layer 20, and a protective layer 40 is arranged on the two-dimensional semi-metal growth insertion layer 30, which is used to protect the two-dimensional semi-metal growth insertion layer 30. This embodiment takes into account that two-dimensional (2D) materials can form mixed-dimensional heterojunctions with atomically flat interfaces with wide bandgap materials by growth or transfer due to their inherent van der Waals (vdW) surfaces, which can provide great flexibility for band adjustment and Schottky barrier modulation on the Ga2O3 surface; specifically, in the two-dimensional van der Waals epitaxial growth kinetics, the Ga2O3 surface will first undergo atomic reconstruction, and a flat surface structure such as a Ga double layer will appear to compensate for surface dangling bonds. The epitaxially grown two-dimensional semimetal is regularly arranged and laterally extended epitaxially under the induction of the reconstructed surface and its buffer layer. Therefore, on the one hand, the surface reconstruction of the Ga2O3 material itself reduces surface defects and unnecessary charge capture during device operation. The van der Waals gap between the two-dimensional material can avoid direct contact between the metal semiconductor and the semiconductor, reduce the disorder of the interface, and improve the uniformity and stability of the metal-semiconductor interface. On the other hand, the van der Waals gap cannot propagate non-polar potential energy, and can shield the surface potential energy of Ga2O3 in different crystal orientations, thereby reducing the anisotropy of the metal-semiconductor contact from the root, which is conducive to achieving unified electrical regulation.

[0038] It should be noted that Figure 1 The illustrated embodiment only schematically shows the positional relationship of the various film layers and does not represent their actual sizes.

[0039] In an optional embodiment of the present invention, the material of the two-dimensional semi-metal growth insertion layer 30 includes any one of the semi-metal phases tungsten ditelluride (WTe2), molybdenum ditelluride (MoTe2), platinum ditelluride (PtTe2), palladium ditelluride (PdTe2) or platinum diselenide (PtSe2).

[0040] Specifically, in this embodiment, tungsten ditelluride, molybdenum ditelluride, platinum telluride, platinum selenide and palladium telluride have high charge mobility, zero bandgap topological state and low state density, and at the same time transfer a stable high-temperature resistant and highly hydrophobic graphene protective layer. The high-temperature resistance can avoid damage to the interface between the semi-metal and gallium oxide in subsequent processes, and the extremely strong hydrophobicity can avoid the adsorption of water and oxygen on the gold semi-interface, thereby improving the chemical stability of the interface, thereby solving the non-ideal transport problem existing in the Schottky contact of the β-Ga2O3 gold semi-interface, and realizing a high-performance Ga2O3-based SBD device with low anisotropy, low surface state and high breakdown characteristics, while reducing the turn-on voltage of the SBD device and improving the breakdown characteristics.

[0041] In an optional embodiment of the present invention, along a direction D1 perpendicular to the substrate, the thickness of the epitaxial layer 20 is 5 to 10 μm, and the doping concentration of the epitaxial layer 20 is less than or equal to 1×10 17 / cm 3 .

[0042] In an optional embodiment of the present invention, the doping concentration of the substrate 10 is greater than 5×10 18 / cm 3 .

[0043] Based on the same inventive concept, see Figure 2 , Figure 2 Schematic diagram of a two-dimensional semi-metal insertion layer passivated gallium oxide Schottky diode and a preparation method thereof provided in an embodiment of the present invention, which is used to prepare a two-dimensional semi-metal insertion layer passivated gallium oxide Schottky diode provided in the above embodiment of the present invention. The embodiment of the diode device is referred to above and will not be repeated here; the preparation method comprises:

[0044] S101, providing a substrate 10 with different crystal orientations, wherein the material of the substrate 10 includes N-type heavily doped β-Ga2O3;

[0045] S102, growing an epitaxial layer 20 on the substrate 10; wherein the material of the epitaxial layer 20 includes N-type unintentionally doped β-Ga2O3;

[0046] S103, cleaning the upper surface of the epitaxial layer 20, and growing a two-dimensional semi-metal growth insertion layer 30 on the cleaned upper surface of the epitaxial layer 20;

[0047] S104, preparing a protective layer 40 on the two-dimensional semi-metal growth insertion layer 30 by transfer;

[0048] S105, preparing a cathode 70 on a side of the substrate 10 away from the epitaxial layer 20;

[0049] S106, patterning the protective layer 40 and the two-dimensional semi-metal growth insertion layer 30, etching away a portion of the stacked protective layer 40 and the two-dimensional semi-metal growth insertion layer 30, so that the orthographic projection of the stacked protective layer 40 and the two-dimensional semi-metal growth insertion layer 30 on the substrate 10 is circular; preparing a terminal structure 50 around the stacked protective layer 40 and the two-dimensional semi-metal growth insertion layer 30;

[0050] S107 , preparing an anode 60 on the protective layer 40 and a portion of the terminal structure 50 .

[0051] In an optional embodiment of the present invention, growing a two-dimensional semi-metal growth insertion layer 30 on the cleaned epitaxial layer 20 comprises:

[0052] Put the precursor mixture and the epitaxial layer into the central temperature zone of the reaction furnace; wherein the epitaxial layer is located above the precursor mixture and is spaced 3 to 5 mm from the precursor mixture;

[0053] Put 200-500 mg of tellurium powder or selenium powder in a quartz sleeve, put the quartz sleeve into the upstream area of ​​the gas flow of the reactor, the distance between the tellurium powder or selenium powder and the precursor mixture is 10-15 cm, and use a magnet to control the position of the tellurium powder or selenium powder in the reactor;

[0054] Argon is introduced into the reaction furnace for purging at a rate of 300 to 500 sccm, the reaction furnace is heated to 250 to 300°C, and kept warm for 10 to 15 minutes to complete the atmosphere purification of the reaction furnace;

[0055] The reactor is heated up at a rate of 15 to 25°C / min, the argon flow rate is adjusted to 80 to 120 sccm, hydrogen is introduced, the hydrogen flow rate is adjusted to 10 to 20 sccm, and the central temperature zone of the reactor is heated up to 550 to 850°C; when the central temperature zone of the reactor is heated up to 450 to 750°C, a magnet is used to move the tellurium powder or selenium powder to the central temperature zone of the reactor, so that the tellurium powder temperature is greater than 500°C, or the selenium powder temperature is greater than 240°C, the tellurium powder or selenium powder melts, evaporates and grows for 20 to 30 minutes, so as to grow a uniform two-dimensional semi-metal growth insertion layer 30 on the upper surface of the epitaxial layer 20; optionally, along the direction D1 perpendicular to the substrate, the thickness of the two-dimensional semi-metal growth insertion layer is 1 to 3 nm.

[0056] In an optional embodiment of the present invention, the precursor mixture includes a mixture of sodium chloride and an oxide, and the oxide includes tungsten oxide or molybdenum oxide or platinum oxide or palladium oxide; optionally, the precursor mixture includes 1 to 15 mg of NaCl and 30 to 50 mg of tungsten trioxide powder, or the precursor mixture includes 1 to 15 mg of NaCl and 30 to 50 mg of molybdenum dioxide powder, or the precursor mixture includes 1 to 15 mg of NaCl and 50 to 150 mg of palladium oxide powder, or the precursor mixture includes 1 to 15 mg of NaCl and 50 to 150 mg of platinum dioxide powder.

[0057] In an optional embodiment of the present invention, a protective layer 40 is prepared on the two-dimensional semi-metal growth insertion layer 30 by transfer, comprising:

[0058] Spin-coating a photoresist support layer with a thickness of 300 to 500 nm on the prefabricated film layer, and heating it on a hot plate at 100 to 120° C. for 60 to 100 seconds; soaking the prefabricated film layer with the photoresist support layer in a ferric chloride (FeCl3) solution for 10 to 15 minutes to separate the graphene from the copper substrate, and rinsing it in deionized water for 5 to 7 times, at which point the copper in the prefabricated film layer has been separated; wherein the prefabricated film layer includes graphene and copper;

[0059] Use the transfer platform to adjust the X-axis and Y-axis, and adjust the rotation angle axis θ, align the graphene spin-coated with the photoresist support layer with the two-dimensional semi-metal growth insertion layer 30 and press it down to fix it, heat it at 80-90°C for 5-10 minutes to cure it to form a protective layer 40, and soak it in acetone at 70-80°C for 5-8 minutes to remove the photoresist support layer.

[0060] In an optional embodiment of the present invention, a cathode 70 is prepared on a side of the substrate 10 facing away from the epitaxial layer 20, comprising:

[0061] On the side of the substrate 10 facing away from the epitaxial layer 20 , a 20-30 nm Ti layer is first evaporated as an adhesion layer, and then an 80-200 nm Au layer is evaporated as the cathode 70 ; in a N 2 atmosphere, annealing is performed in an annealing furnace at a temperature of 480-520° C. for 1-2 min to obtain an ohmic contact to prepare the cathode 70 .

[0062] In an optional embodiment of the present invention, the protective layer 40 and the two-dimensional semi-metal growth insertion layer 30 are patterned, and a portion of the stacked protective layer 40 and the two-dimensional semi-metal growth insertion layer 30 is etched away, so that the stacked protective layer 40 and the two-dimensional semi-metal growth insertion layer 30 have a circular orthographic projection on the substrate 10; a terminal structure 50 is prepared around the stacked protective layer 40 and the two-dimensional semi-metal growth insertion layer 30, and an anode 60 is prepared on the protective layer 40 and a portion of the terminal structure 50, including:

[0063] Spin-coating a photoresist on the protective layer, etching the exposed protective layer and the two-dimensional semi-metal growth insertion layer by using oxygen plasma treatment and F-based inductively coupled plasma after photolithography, and patterning the protective layer and the two-dimensional semi-metal growth insertion layer so that the stacked protective layer and the two-dimensional semi-metal growth insertion layer have an orthographic projection on the substrate that is circular;

[0064] Around the stacked two-dimensional semi-metal growth insertion layer and protective layer, the terminal structure area is defined by photolithography patterning process, and NiO film is prepared by magnetron sputtering as the terminal structure, with a carrier concentration of 5x10 16 ~5x10 18 / cm 3 , thickness is 30~40nm;

[0065] Photoresist is spin-coated on the protective layer and the terminal structure. After the photoresist is photolithographically coated, a 20-50 nm Ni layer and a 100-200 nm Au layer are respectively evaporated as anode metals using electron beam evaporation, or a 100-200 nm Pt layer is deposited as anode metal using magnetron sputtering, and the photoresist is stripped in an acetone solution to prepare an anode.

[0066] In an optional embodiment of the present invention, Ti / Au is used as the cathode 70 and Ni / Au is used as the anode 60 to construct a β-Ga2O3-based SBD device with a semi-metallic phase WTe2 as a two-dimensional semi-metallic growth insertion layer.

[0067] S1. Provide a β-Ga2O3 epitaxial wafer with a (001) crystal orientation, wherein the doping concentration of the substrate in the epitaxial wafer is greater than 5×10 18 / cm 3 , the doping concentration of the epitaxial layer in the epitaxial wafer is less than or equal to 1×10 17 / cm 3 , along the direction perpendicular to the substrate, the thickness of the epitaxial layer is 5 to 10 μm.

[0068] S2. Clean the purchased (001) crystal orientation β-Ga2O3 epitaxial wafer; specifically, cleaning the epitaxial wafer includes ultrasonic cleaning with acetone and isopropanol for 4 to 6 minutes respectively, then rinsing with deionized water for 4 to 6 minutes, and drying with a nitrogen gun.

[0069] S3, preparing a two-dimensional semi-metallic WTe2 material by direct growth on a β-Ga2O3 epitaxial wafer, placing the epitaxial wafer substrate and a precursor mixture to be reacted into a reactor, and growing a high-quality two-dimensional semi-metallic WTe2 material film by a CVD method; S3 includes:

[0070] S31, placing a precursor mixture of WO3 (30-50 mg) and NaCl (5-10 mg) and a β-Ga2O3 epitaxial wafer into the central temperature zone of the reaction furnace, wherein the epitaxial wafer is located above the precursor mixture with a spacing of 3-5 mm;

[0071] S32, placing 200-500 mg of tellurium powder and a quartz sleeve into the upstream area of ​​the gas flow of the reactor, with the distance between the tellurium powder and the precursor mixture being 10-15 cm, and using a magnet to control the position of the mobile tellurium powder in the reactor;

[0072] S33, introducing argon gas into the reaction furnace for purging, the introduction rate of argon gas is 300-500 sccm, the reaction furnace is heated to 250-300° C. and kept warm for 10-15 minutes to complete the atmosphere purification of the reaction furnace, and the reaction furnace is optionally a tubular furnace;

[0073] S34. Heat up the reaction furnace body, set the heating rate to 15-25°C / min, adjust the argon flow rate to 100sccm, introduce H2, adjust the H2 flow rate to 20sccm, heat the central temperature zone to 750-850°C, when the central temperature zone is heated to 650-750°C, use a magnet to move the tellurium powder in the quartz sleeve to the central temperature zone, so that the distance between the tellurium powder and the precursor mixed powder is 5cm, the temperature is greater than 500°C, melt, evaporate and grow for 20-30min, and finally obtain a uniform WTe2 epitaxial thin film material on the surface of the β-Ga2O3 epitaxial wafer, that is, a two-dimensional semi-metallic growth insertion layer, and the thickness of the two-dimensional semi-metallic growth insertion layer is 1-3nm.

[0074] S4, constructing graphene on the grown two-dimensional semi-metal growth insertion layer by transfer on the prepared two-dimensional WTe2 / Ga2O3 material, so as to achieve the purpose of protecting the two-dimensional semi-metal growth insertion layer; S4 includes:

[0075] S41, spin coating a photoresist (PMMA) support layer with a thickness of 300-500 nm on a commercially purchased graphene / Cu substrate, heating it on a hot plate at 100° C. for 60-100 s to enhance adhesion, soaking the photoresist support layer / graphene and its Cu substrate in a FeCl3 solution for 10-15 min, etching the Cu substrate to obtain a support layer / graphene structure, and rinsing it in deionized water for 5-7 times;

[0076] S42. Use the transfer platform to move the X and Y axes and adjust the rotation angle axis θ to align the photoresist support layer / graphene with the WTe2 / β-Ga2O3 epitaxial wafer, then press down and fix, heat at 80°C for 5 to 10 minutes to cure, and soak in acetone at 70°C for 5 to 8 minutes to remove the PMMA support layer.

[0077] S5, using the first metal material to prepare a bottom electrode, that is, a cathode; S5 includes:

[0078] S51, using electron beam evaporation to deposit a 20-30 nm Ti layer as an adhesion layer and an 80-200 nm Au layer as a bottom electrode on the substrate;

[0079] S52. In an N2 atmosphere, annealing is performed in an annealing furnace at a temperature of 480 to 520° C. for 1 to 2 minutes to achieve ohmic contact between the bottom electrode and gallium oxide.

[0080] S6, graphene / two-dimensional semi-metal material is patterned and an anode terminal structure is constructed; S6 includes:

[0081] S61, spin-coating a photoresist on the graphene / two-dimensional semi-metal material / β-Ga2O3 epitaxial wafer, and etching the exposed graphene / two-dimensional semi-metal material using oxygen plasma treatment and F-based inductively coupled plasma treatment after photolithography to complete the patterning of the graphene / two-dimensional semi-metal material;

[0082] S62, the terminal structure area is defined by photolithography patterning process, and a 35nm thick NiO film is prepared by magnetron sputtering as the terminal structure, with a carrier concentration of 5x10 16 ~5x10 18 / cm 3 , reducing edge electric field crowding and leakage.

[0083] S7, photolithography again, evaporation to prepare anode metal, and realize anode Schottky contact;

[0084] The substrate is spin-coated with photoresist, and after photolithography, a 20-50 nm Ni layer and a 100-200 nm Au layer are respectively evaporated as anode metals using electron beam evaporation, and the photoresist is stripped in an acetone solution to complete the device preparation.

[0085] In an optional embodiment of the present invention, Ti / Au is used as the cathode 70 and Ni / Au is used as the anode 60 to construct a β-Ga2O3-based SBD device with a semi-metallic phase MoTe2 as a two-dimensional semi-metallic growth insertion layer.

[0086] S1. Provide a (010) oriented β-Ga2O3 epitaxial wafer, the doping concentration of the substrate in the epitaxial wafer is greater than 5×10 18 / cm 3 , the doping concentration of the epitaxial layer in the epitaxial wafer is less than or equal to 1×10 17 / cm 3 , along the direction perpendicular to the substrate, the thickness of the epitaxial layer is 5 to 10 μm.

[0087] S2. Clean the purchased (010) crystal orientation β-Ga2O3 epitaxial wafers; specifically, cleaning the epitaxial wafers includes ultrasonic cleaning with acetone and isopropanol for 4 to 6 minutes respectively, then rinsing with deionized water for 4 to 6 minutes, and drying with a nitrogen gun.

[0088] S3, preparing a two-dimensional semi-metallic MoTe2 material by direct growth on a β-Ga2O3 epitaxial wafer, placing an epitaxial wafer substrate and a precursor mixture to be reacted into a reactor, and growing a high-quality two-dimensional semi-metallic MoTe2 material film by a CVD method, S3 includes:

[0089] S31, placing a precursor mixture of MoO2 (30-50 mg) and NaCl (1-5 mg) and a β-Ga2O3 epitaxial wafer into the central temperature zone of a reaction furnace, wherein the epitaxial wafer is located above the precursor mixture with a spacing of 3-5 mm;

[0090] S32, placing 200-500 mg of tellurium powder and a quartz sleeve into the upstream area of ​​the gas flow of the reactor, with the distance between the tellurium powder and the precursor mixture being 10-15 cm, and using a magnet to control the position of the mobile tellurium powder in the reactor;

[0091] S33, introducing argon gas into the reaction furnace for purging, the introduction rate of argon gas is 300-500 sccm, the reaction furnace is heated to 250-300° C. and kept warm for 10-15 minutes to complete the atmosphere purification of the reaction furnace; optionally, the reaction furnace is a tubular furnace;

[0092] S34. Heat up the reaction furnace body, set the heating rate to 15-25°C / min, adjust the argon flow rate to 100sccm, introduce H2, adjust the H2 flow rate to 15sccm, heat the central temperature zone to 700-800°C, when the central temperature zone is heated to 600-700°C, use a magnet to move the tellurium powder in the quartz sleeve to the central temperature zone, so that the distance between the tellurium powder and the precursor mixed powder is 5cm, the temperature is greater than 500°C, melt, evaporate and grow for 20-30min, and finally obtain a uniform MoTe2 epitaxial thin film material on the surface of the β-Ga2O3 epitaxial wafer, that is, a two-dimensional semi-metallic growth insertion layer, and the thickness of the two-dimensional semi-metallic growth insertion layer is 1-3nm.

[0093] S4, constructing graphene on the grown two-dimensional semi-metal growth insertion layer by transfer on the prepared two-dimensional MoTe2 / Ga2O3 material, so as to achieve the purpose of protecting the two-dimensional semi-metal growth insertion layer; S4 includes:

[0094] S41, spin coating a photoresist (PMMA) support layer with a thickness of 300-500 nm on a commercially purchased graphene / Cu substrate, heating it on a hot plate at 100° C. for 60-100 s to enhance adhesion, soaking the photoresist support layer / graphene and its Cu substrate in a FeCl3 solution for 10-15 min, etching the Cu substrate to obtain a support layer / graphene structure, and rinsing it in deionized water for 5-7 times;

[0095] S42. Use the transfer platform to move the X and Y axes and adjust the rotation angle axis θ to align the photoresist support layer / graphene with the MoTe2 / β-Ga2O3 epitaxial wafer, then press down and fix, heat at 80°C for 5 to 10 minutes to cure, and soak in acetone at 70°C for 5 to 8 minutes to remove the PMMA support layer.

[0096] S5, using the first metal material to prepare a bottom electrode; S5 includes:

[0097] S51, using electron beam evaporation to deposit a 20-30 nm Ti layer as an adhesion layer and an 80-200 nm Au layer as a bottom electrode on the substrate;

[0098] S52. In an N2 atmosphere, annealing is performed in an annealing furnace at a temperature of 480 to 520° C. for 1 to 2 minutes to achieve ohmic contact between the bottom electrode and gallium oxide.

[0099] S6, patterning the graphene / two-dimensional semi-metal material and constructing an anode terminal structure, S6 includes:

[0100] S61, spin-coating a photoresist on the graphene / two-dimensional semi-metal material / β-Ga2O3 epitaxial wafer, and etching the exposed graphene / two-dimensional semi-metal material using oxygen plasma treatment and F-based inductively coupled plasma treatment after photolithography to complete the patterning of the graphene / two-dimensional semi-metal material;

[0101] S62, using photolithography patterning process to define the terminal structure area, magnetron sputtering was used to prepare a 38nm thick NiO film as the terminal structure, with a carrier concentration of 5x10 16 ~5x10 18 / cm 3 , reducing edge electric field crowding and leakage.

[0102] S7, photolithography again, evaporation to prepare anode metal, and realize anode Schottky contact;

[0103] The substrate is spin-coated with photoresist, and after photolithography, a 20-50 nm Ni layer and a 100-200 nm Au layer are respectively evaporated as anode metals using electron beam evaporation, and the photoresist is stripped in an acetone solution to complete the device preparation.

[0104] In an optional embodiment of the present invention, Ti / Au is used as the cathode and Pt is used as the anode to construct a β-Ga2O3-based SBD device with a semi-metallic phase PtSe2 as a two-dimensional semi-metallic growth insertion layer.

[0105] S1. Provide a (100) oriented β-Ga2O3 epitaxial wafer, the doping concentration of the substrate in the epitaxial wafer is greater than 5×10 18 / cm 3 , the doping concentration of the epitaxial layer in the epitaxial wafer is less than or equal to 1×10 17 / cm 3 , along the direction perpendicular to the substrate, the thickness of the epitaxial layer is 5 to 10 μm.

[0106] S2. Clean the purchased (100) oriented β-Ga2O3 epitaxial wafers; specifically, cleaning the epitaxial wafers includes ultrasonic cleaning with acetone and isopropanol for 4 to 6 minutes respectively, followed by rinsing with deionized water for 4 to 6 minutes, and drying with a nitrogen gun.

[0107] S3, preparing a two-dimensional semi-metallic PtSe2 material by direct growth on a β-Ga2O3 epitaxial wafer, placing an epitaxial wafer substrate and a precursor mixture to be reacted into a reactor, and growing a high-quality two-dimensional semi-metallic PtSe2 material film by a CVD method, S3 includes:

[0108] S31, placing a precursor mixture of PtO2 (50-150 mg) and NaCl (10-15 mg) and a β-Ga2O3 epitaxial wafer into the central temperature zone of the reactor, wherein the epitaxial wafer is located 3-5 mm above the precursor mixture;

[0109] S32, placing 300-500 mg of selenium powder and a quartz sleeve into the upstream area of ​​the airflow of the reactor, with the distance between the selenium powder and the epitaxial wafer being 10-15 cm, and using a magnet to control the position of the mobile selenium powder in the reactor;

[0110] S33, introducing argon gas into the reaction furnace for purging, the introduction rate of argon gas is 300-500 sccm, the reaction furnace is heated to 250-300° C. and kept warm for 10-15 minutes to complete the atmosphere purification of the reaction furnace; optionally, the reaction furnace is a tubular furnace;

[0111] S34. Heat up the reaction furnace body, set the heating rate to 15-25°C / min, adjust the argon flow rate to 80-120sccm, introduce H2, adjust the H2 flow rate to 10-20sccm, heat the central temperature zone to 650-750°C, when the central temperature zone is heated to 550-650°C, use a magnet to move the selenium powder to the central temperature zone, so that the distance between the selenium powder and the precursor mixed powder is 10cm, the temperature is greater than 240°C, melt, evaporate and grow for 20-30min, and finally obtain a uniform PtSe2 epitaxial thin film material on the surface of the β-Ga2O3 epitaxial wafer, that is, a two-dimensional semi-metallic growth insertion layer, and the thickness of the two-dimensional semi-metallic growth insertion layer is 1-3nm.

[0112] S4, constructing graphene on the grown two-dimensional semi-metal growth insertion layer by transfer on the prepared two-dimensional PtSe2 / Ga2O3 material, so as to achieve the purpose of protecting the two-dimensional semi-metal growth insertion layer; S4 includes:

[0113] S41, spin coating a photoresist (PMMA) support layer with a thickness of 300-500 nm on a commercially purchased graphene / Cu substrate, heating it on a hot plate at 100° C. for 60-100 s to enhance adhesion, soaking the photoresist support layer / graphene and its Cu substrate in a FeCl3 solution for 10-15 min, etching the Cu substrate to obtain a support layer / graphene structure, and rinsing it in deionized water for 5-7 times;

[0114] S42. Use the transfer platform to move the X and Y axes and adjust the rotation angle axis θ to align the photoresist support layer / graphene with the PtSe2 / β-Ga2O3 epitaxial wafer, then press down to fix, heat at 80°C for 5 to 10 minutes to cure, and soak in acetone at 70°C for 5 to 8 minutes to remove the PMMA support layer.

[0115] S5, using the first metal material to prepare a bottom electrode; S5 includes:

[0116] S51, using electron beam evaporation to deposit a 20-30 nm Ti layer as an adhesion layer and an 80-200 nm Au layer as a bottom electrode on the substrate;

[0117] S52. In an N2 atmosphere, annealing is performed in an annealing furnace at a temperature of 480 to 520° C. for 1 to 2 minutes to achieve ohmic contact between the bottom electrode and gallium oxide.

[0118] S6, graphene / two-dimensional semi-metal material is patterned and an anode terminal structure is constructed; S6 includes:

[0119] S61, spin coating a photoresist on the graphene / two-dimensional semi-metal PtSe2 / β-Ga2O3 epitaxial wafer, and etching the exposed graphene / two-dimensional semi-metal material using oxygen plasma treatment and F-based inductively coupled plasma treatment after photolithography to complete the patterning of the graphene / two-dimensional semi-metal material;

[0120] S62, the terminal structure area is defined by photolithography patterning process, and a 40nm thick NiO film is prepared by magnetron sputtering as the terminal structure, with a carrier concentration of 5x10 16 ~5x10 18 / cm 3 , reducing edge electric field crowding and leakage.

[0121] S7, photolithography again, evaporation to prepare anode metal, and realize anode Schottky contact;

[0122] The substrate is spin-coated with photoresist, and after photolithography, a 100-200 nm Pt layer is deposited as an anode metal using magnetron sputtering. The photoresist is stripped in an acetone solution, and the device is prepared.

[0123] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is any such actual relationship or order between these entities or operations. Moreover, the term "include", "comprise" or any other variant is intended to cover non-exclusive inclusion, so that the article or device including a series of elements includes not only those elements, but also other elements that are not explicitly listed. In the absence of more restrictions, the elements defined by the sentence "including one..." do not exclude the existence of other identical elements in the article or device including the elements. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The orientation or position relationship indicated by "up", "down", "left", "right", etc. is based on the orientation or position relationship shown in the accompanying drawings, which is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation of the present invention.

[0124] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine different embodiments or examples described in this specification.

[0125] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the protection scope of the present invention.

Claims

1. A two-dimensional semi-metal insertion layer passivated gallium oxide Schottky diode, characterized in that: include: A substrate, wherein the material of the substrate comprises N-type heavily doped β-Ga2O3 with different crystal orientations; An epitaxial layer is located on the substrate; wherein the material of the epitaxial layer includes N-type unintentionally doped β-Ga2O3; A two-dimensional semi-metal growth insertion layer is located on the epitaxial layer; A protective layer, located on the two-dimensional semi-metal growth insertion layer, wherein the protective layer overlaps with the orthographic projection of the two-dimensional semi-metal growth insertion layer along a direction perpendicular to the substrate; A terminal structure, located on the epitaxial layer, wherein the terminal structure is a ring structure and is arranged around the two-dimensional semi-metal growth insertion layer and the protective layer; an anode, covering the protective layer and a portion of the terminal structure; The cathode is located on a side of the substrate away from the epitaxial layer.

2. The two-dimensional semi-metal insertion layer passivated gallium oxide Schottky diode according to claim 1, characterized in that: The material of the two-dimensional semi-metal growth insertion layer includes any one of semi-metal phase tungsten ditelluride, molybdenum ditelluride, platinum ditelluride, palladium ditelluride or platinum diselenide.

3. The two-dimensional semi-metal insertion layer passivated gallium oxide Schottky diode according to claim 1, characterized in that: The material of the protection layer includes single-layer graphene.

4. The two-dimensional semi-metal insertion layer passivated gallium oxide Schottky diode according to claim 1, characterized in that: The doping concentration of the substrate is greater than 5×10 18 / cm 3 , along the direction perpendicular to the substrate, the thickness of the epitaxial layer is 5 to 10 μm, and the doping concentration of the epitaxial layer is less than or equal to 1×10 17 / cm 3 .

5. A method for preparing a two-dimensional semi-metal insertion layer passivated gallium oxide Schottky diode, characterized in that: include: Providing a substrate with different crystal orientations, wherein the material of the substrate includes N-type heavily doped β-Ga2O3; Growing an epitaxial layer on the substrate; wherein the material of the epitaxial layer includes N-type unintentionally doped β-Ga2O3; Cleaning the upper surface of the epitaxial layer, and growing a two-dimensional semi-metal growth insertion layer on the cleaned upper surface of the epitaxial layer; Preparing a protective layer on the two-dimensional semi-metal growth insertion layer by transfer; preparing a cathode on a side of the substrate facing away from the epitaxial layer; The protective layer and the two-dimensional semi-metal growth insertion layer are patterned, and a partial area of ​​the stacked protective layer and the two-dimensional semi-metal growth insertion layer is etched away, so that the stacked protective layer and the two-dimensional semi-metal growth insertion layer are projected onto the substrate in a circular shape; and a terminal structure is prepared around the stacked protective layer and the two-dimensional semi-metal growth insertion layer; An anode is prepared on the protective layer and a portion of the terminal structure.

6. The method for preparing the two-dimensional semi-metal insertion layer passivated gallium oxide Schottky diode according to claim 5, characterized in that: The step of growing a two-dimensional semi-metal growth insertion layer on the cleaned upper surface of the epitaxial layer comprises: Putting the precursor mixture and the epitaxial layer into the central temperature zone of the reaction furnace; wherein the epitaxial layer is located above the precursor mixture and is spaced 3 to 5 mm from the precursor mixture; Put 200-500 mg of tellurium powder or selenium powder in a quartz sleeve, put the quartz sleeve into the upstream area of ​​the gas flow of the reactor, the distance between the tellurium powder or selenium powder and the precursor mixture is 10-15 cm, and use a magnet to control the position of the tellurium powder or selenium powder in the reactor; Passing argon into the reaction furnace for purging, the passing rate of the argon is 300-500 sccm, heating the reaction furnace to 250-300° C., and keeping the temperature for 10-15 minutes to complete the atmosphere purification of the reaction furnace; The reaction furnace is heated up, the argon flow rate is adjusted to 80-120 sccm, hydrogen is introduced, the flow rate of the hydrogen is adjusted to 10-20 sccm, the heating rate is 15-25°C / min, the central temperature zone of the reaction furnace is heated up to 550-850°C, when the central temperature zone of the reaction furnace is heated up to 450-750°C, the tellurium powder or selenium powder is moved to the central temperature zone of the reaction furnace by a magnet, so that the temperature of the tellurium powder is greater than 500°C, or the temperature of the selenium powder is greater than 240°C, the tellurium powder or selenium powder is melted, evaporated and grown for 20-30 minutes, so as to grow the uniform two-dimensional semi-metal growth insertion layer on the upper surface of the epitaxial layer, the thickness of the two-dimensional semi-metal growth insertion layer is 1-3nm.

7. The method for preparing the two-dimensional semi-metal insertion layer passivated gallium oxide Schottky diode according to claim 6, characterized in that: The precursor mixture includes a mixture of sodium chloride and an oxide, the oxide includes tungsten oxide or molybdenum oxide or platinum oxide or palladium oxide, the precursor mixture includes 1 to 15 mg of sodium chloride and 30 to 50 mg of tungsten trioxide powder, or the precursor mixture includes 1 to 15 mg of sodium chloride and 30 to 50 mg of molybdenum dioxide powder, or the precursor mixture includes 1 to 15 mg of sodium chloride and 50 to 150 mg of palladium oxide powder, or the precursor mixture includes 1 to 15 mg of sodium chloride and 50 to 150 mg of platinum dioxide powder.

8. The method for preparing the two-dimensional semi-metal insertion layer passivated gallium oxide Schottky diode according to claim 5, characterized in that: The protective layer is prepared on the two-dimensional semi-metal growth insertion layer by transfer, comprising: Spin-coating a photoresist support layer with a thickness of 300 to 500 nm on the prefabricated film layer, and heating it on a hot plate at 100 to 120° C. for 60 to 100 seconds; soaking the prefabricated film layer with the photoresist support layer in a ferric chloride solution for 10 to 15 minutes, and rinsing it in deionized water for 5 to 7 times, at which time, the copper in the prefabricated film layer has been separated; wherein the prefabricated film layer includes graphene and copper; Use the transfer platform to adjust the X-axis and Y-axis, and adjust the rotation angle axis θ, align the graphene spin-coated with the photoresist support layer with the two-dimensional semi-metal growth insertion layer and press it down to fix it, heat it at 80-90°C for 5-10 minutes to form the protective layer, and soak it in acetone at 70-80°C for 5-8 minutes to remove the photoresist support layer.

9. The method for preparing the two-dimensional semi-metal insertion layer passivated gallium oxide Schottky diode according to claim 5, characterized in that: Preparing a cathode on a side of the substrate facing away from the epitaxial layer, comprising: On the side of the substrate away from the epitaxial layer, a 20-30 nm titanium layer is first evaporated as an adhesion layer by electron beam evaporation, and then an 80-200 nm gold layer is evaporated as the cathode; in an N2 atmosphere, annealing is performed in an annealing furnace at a temperature of 480-520°C for 1-2 minutes to obtain an ohmic contact to prepare a cathode.

10. The method for preparing the two-dimensional semi-metal insertion layer passivated gallium oxide Schottky diode according to claim 5, characterized in that: The protective layer and the two-dimensional semi-metal growth insertion layer are patterned, and a portion of the stacked protective layer and the two-dimensional semi-metal growth insertion layer is etched away, so that the stacked protective layer and the two-dimensional semi-metal growth insertion layer are projected onto the substrate in a circular shape; a terminal structure is prepared around the stacked protective layer and the two-dimensional semi-metal growth insertion layer, and an anode is prepared on the protective layer and a portion of the terminal structure, including: Spin-coating a photoresist on the protective layer, etching the exposed protective layer and the two-dimensional semi-metal growth insertion layer by oxygen plasma treatment and F-based inductively coupled plasma after photolithography of the photoresist, and patterning the protective layer and the two-dimensional semi-metal growth insertion layer so that the stacked protective layer and the two-dimensional semi-metal growth insertion layer are projected in a circular shape on the substrate; Around the stacked two-dimensional semi-metal growth insertion layer and the protective layer, a terminal structure region is defined by a photolithography patterning process, and a NiO film is prepared by magnetron sputtering as a terminal structure, and the carrier concentration is 5x10 16 ~5x10 18 / cm 3 , thickness is 30~40nm; A photoresist is spin-coated on the protective layer and the terminal structure. After the photoresist is photolithographically processed, a 20-50 nm Ni layer and a 100-200 nm Au layer are respectively evaporated as anode metals using electron beam evaporation, or a 100-200 nm Pt layer is deposited as anode metal using magnetron sputtering, and the photoresist is stripped in an acetone solution to prepare an anode.

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