Low-voltage low-capacitance bidirectional transient suppression diode

Abstract

The invention relates to a low-voltage low-capacitance bidirectional transient suppression diode, and belongs to the field of diode design. A chip bonding area is arranged on the upper surface of the bottom of the inner cavity of the ceramic tube shell; bottom electrodes of the N + NP + N + structure transient suppression diode core and the P + PN + P + structure transient suppression diode core are welded on the chip bonding area in an eutectic mode. The pressure point is arranged on the upper surface of the inner cavity bottom of the ceramic tube shell; the top of the N + NP + N + structure transient voltage suppressor tube core and the top of the P + PN + P + structure transient voltage suppressor tube core are respectively bonded with the top of the pressure point through leads; the first tube shell pin is connected with the pressing point and then extends out of the lower surface of the ceramic tube shell; the second tube shell pin extends out of the lower surface of the ceramic tube shell after being connected with the chip bonding area; the invention adopts a simple NPN bipolar process and a PNP bipolar process to respectively realize integrated manufacturing of two paths of voltage stabilizing diodes and a common diode, and provides a low-voltage low-capacitance bidirectional transient suppression diode through a conventional dual-chip ceramic packaging process.

Description

Technical Field

[0001] The invention belongs to the field of diode design and relates to a low-voltage and low-capacitance bidirectional transient suppression diode. Background Art

[0002] As the transmission speed of communication signals becomes faster and faster, the capacitance of transient suppression diodes for low-voltage protection is required to be lower and lower, and ordinary low-voltage transient suppression diodes are increasingly unable to meet the use requirements. At present, the solution for low-capacitance transient suppression diodes is to connect a low-capacitance ordinary diode in series with the common cathode or common anode of the voltage-stabilizing diode circuit. According to the relationship between the series capacitances, the total capacitance mainly depends on the capacitance of the ordinary diode, thereby achieving the purpose of reducing the capacitance. A bidirectional transient suppression diode requires 2 paths with a total of 4 diodes connected. At present, most bidirectional low-capacitance transient suppression diodes on the market are 4 discrete voltage-stabilizing diodes and ordinary low-capacitance diodes that are packaged in series and parallel in a tube shell through wire bonding and welding, which not only increases the difficulty of packaging technology, but also increases the lead resistance between the series connections. Recently, a patent report has been published that these 4 diodes are integrated into a chip through chip technology. Although the packaging process is simplified, there are two epitaxial processes and multiple doping processes in the manufacturing process of the bidirectional transient suppression diode die, which greatly increases the process complexity and is not conducive to mass production. Summary of the invention

[0003] The technical problem solved by the present invention is: to overcome the shortcomings of the prior art, to propose a low-voltage and low-capacitance bidirectional transient suppression diode, to respectively realize the integrated manufacturing of a two-way voltage stabilizing diode and a common diode by using a simple NPN bipolar process and a PNP bipolar process, and to provide a low-voltage and low-capacitance bidirectional transient suppression diode by using a conventional double-chip ceramic packaging process.

[0004] The solution of the present invention is:

[0005] A low-voltage and low-capacitance bidirectional transient suppression diode comprises an N+NP+N+ structure transient suppression diode die, a P+PN+P+ structure transient suppression diode die, a ceramic tube shell, leads, pressure points, a bonding area, a first tube shell pin, a second tube shell pin and a cover plate;

[0006] Among them, the ceramic tube shell is a hollow rectangular structure; an opening is set at the top of the ceramic tube shell; a bonding area is set on the upper surface of the bottom of the inner cavity of the ceramic tube shell; the bottom electrodes of the N+NP+N+ structure transient suppression diode core and the P+PN+P+ structure transient suppression diode core are eutectic welded on the bonding area; the pressure point is set on the upper surface of the bottom of the inner cavity of the ceramic tube shell; the top of the N+NP+N+ structure transient suppression diode core and the top of the P+PN+P+ structure transient suppression diode core are bonded to the top of the pressure point through leads respectively; the cover plate covers the opening at the top of the ceramic tube shell; after the first tube shell pin is connected to the pressure point, it extends from the lower surface of the ceramic tube shell; after the second tube shell pin is connected to the bonding area, it extends from the lower surface of the ceramic tube shell; the positive and negative transient pulse current discharge channels are formed between the first tube shell pin and the second tube shell pin by the N+NP+N+ structure transient suppression diode core and the P+PN+P+ structure transient suppression diode core.

[0007] In the above-mentioned low-voltage and low-capacitance bidirectional transient suppression diode, the process temperature of the electrode eutectic welding is 300℃±5℃, the vacuum degree is less than 0.5mbar, and the time is 1-2min; the lead wire is a silicon aluminum wire with a diameter of 32μm; the cover plate is used to seal the ceramic tube shell through a melting sealing process or parallel seam welding, and the material of the cover plate is a kovar alloy with a gold-plated surface.

[0008] In the above-mentioned low-voltage and low-capacitance bidirectional transient suppression diode, the method for manufacturing the N+NP+N+ structure transient suppression diode die is as follows:

[0009] The N-type epitaxial layer is doped with boron to form a P+ base region; the P+ base region layer is doped with concentrated phosphorus to form N+;

[0010] Wherein, the N-type epitaxial layer includes a substrate and an epitaxial layer; the epitaxial layer is located on the outer surface of the substrate;

[0011] The material parameters of the substrate are: N <111> / Arsenic doped, resistivity less than 0.005Ω·cm, thickness 450±5μm;

[0012] The material parameters of the epitaxial layer are: phosphorus doped, resistivity of 50-300Ω·cm, and thickness of 8-10μm.

[0013] In the above-mentioned low-voltage and low-capacitance bidirectional transient suppression diode, the P+ base layer is formed by a boron ion implantation process, the implantation window is 250 μm×250 μm, the implantation energy is 40 kev, and the implantation dose is 3-5E14 / cm 2 The post-injection annealing process is 1100℃, 30min.

[0014] In the above-mentioned low-voltage and low-capacitance bidirectional transient suppression diode, the concentrated phosphorus N+ region on the P+ base layer is formed by a phosphorus ion implantation process, the implantation window is 200 μm×200 μm, the implantation energy is 30 kev, and the implantation dose is 2E16 / cm 2 The post-injection annealing process is 950℃, 30min.

[0015] In the above-mentioned low-voltage and low-capacitance bidirectional transient suppression diode, the front metal layer of the N+NP+N+ structure transient suppression diode core is aluminum metal with a thickness of 2μm±0.2μm; the passivation layer on the metal is SiO2 with a thickness greater than 800nm; after thinning to 250μm±10μm, back metallization is performed, and the back metal layer of the N+NP+N+ structure transient suppression diode core is Au with a thickness greater than 200nm.

[0016] In the above-mentioned low-voltage and low-capacitance bidirectional transient suppression diode, the manufacturing method of the P+PN+P+ structure transient suppression diode die is:

[0017] The P-type epitaxial layer is doped with phosphorus to form an N+ base region, and then concentrated boron is doped on the N+ base region layer to form P+.

[0018] In the above-mentioned low-voltage and low-capacitance bidirectional transient suppression diode, the P-type epitaxial layer includes a substrate and an epitaxial layer; the epitaxial layer is located on the outer surface of the substrate;

[0019] The material parameters of the substrate are: <111> / Boron-doped, resistivity less than 0.004Ω.cm, thickness 450±5μm;

[0020] The material parameters of the epitaxial layer are: boron doped, resistivity of 50-300Ω·cm, and thickness of 8-10μm.

[0021] In the above-mentioned low-voltage and low-capacitance bidirectional transient suppression diode, the N+ base region is formed by phosphorus ion implantation process, the implantation window is 250 μm×250 μm, the implantation energy is 60 kev, and the implantation dose is 1-2E14 / cm 2 , the post-implantation annealing process is 1000℃, 30min;

[0022] The boron-concentrated N+ region on the N+ base layer is formed by boron ion implantation, with an implantation window of 200μm×200μm, an implantation energy of 40kev, and an implantation dose of 1E16 / cm 2 The rapid annealing process after implantation is 1180℃, 10s.

[0023] In the above-mentioned low-voltage and low-capacitance bidirectional transient suppression diode, the front metal layer of the P+PN+P+ structure transient suppression diode core is aluminum metal with a thickness of 2μm±0.2μm; the passivation layer on the metal is SiO2 with a thickness greater than 800nm; the back side of the P+PN+P+ structure transient suppression diode core is metallized after being thinned to 250μm±10μm, and the back side metal layer is Au with a thickness greater than 200nm.

[0024] The beneficial effects of the present invention compared with the prior art are:

[0025] (1) The present invention realizes two discharge channels of different transient currents by adopting NPN bipolar process and PNP bipolar process respectively;

[0026] (2) The present invention not only simplifies the manufacturing process of the TVS diode core and improves the integration of the voltage regulator diode and the common low-capacitance diode in each path, but also simplifies the overall packaging process, making the product easier to achieve mass production and reducing the production cost;

[0027] (3) The present invention realizes that when a positive transient current pulse appears at the tube shell lead bonding point, the voltage regulator diode of the N+NP+N+ structure transient suppression diode core reversely breaks down and the transient current flows forward through a low-capacitance ordinary diode for discharge; when a negative transient current pulse appears at the tube shell lead bonding point, the transient current flows forward through the low-capacitance ordinary diode of the P+PN+P+ structure transient suppression diode core and then breaks down reversely and discharges, thereby achieving the purpose of bidirectionally suppressing transient voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 It is a package assembly diagram of the low-voltage capacitor bidirectional transient suppression diode of the present invention;

[0029] Figure 2 It is a manufacturing process diagram of the N+NP+N+ structure transient suppression diode tube core of the present invention;

[0030] Figure 3 This is a manufacturing process diagram of the P+PN+P+ structure transient suppression diode core of the present invention. DETAILED DESCRIPTION

[0031] The present invention will be further described below in conjunction with the embodiments.

[0032] The present invention provides a low-voltage and low-capacitance bidirectional transient suppression diode, which adopts a simple NPN bipolar process and a PNP bipolar process to respectively realize the integrated manufacturing of a two-way voltage regulator diode and a common diode, and provides a low-voltage and low-capacitance bidirectional transient suppression diode through a conventional double-chip ceramic packaging process.

[0033] Low voltage low capacitance bidirectional TVS diodes, such as Figure 1 As shown, it specifically includes an N+NP+N+ structure transient suppression diode die 1, a P+PN+P+ structure transient suppression diode die 2, a ceramic tube shell 3, a lead 4, a pressure point 5, a bonding area 6, a first tube shell pin 7, a second tube shell pin 8 and a cover plate 9. Among them, the ceramic tube shell 3 is a hollow rectangular parallelepiped structure; the top of the ceramic tube shell 3 is provided with an opening; the upper surface of the bottom of the inner cavity of the ceramic tube shell 3 is provided with a bonding area 6; the bottom electrodes of the N+NP+N+ structure transient suppression diode die 1 and the P+PN+P+ structure transient suppression diode die 2 are eutectic welded on the bonding area 6; the pressure point 5 is provided on the upper surface of the bottom of the inner cavity of the ceramic tube shell 3; the top of the N+NP+N+ structure transient suppression diode die 1, the P+PN+P+ structure transient suppression diode die 2 is bonded to the top of the pressure point 5 through the lead 4; the cover plate 9 covers the opening at the top of the ceramic tube shell 3; after the first tube shell pin 7 is connected to the pressure point 5, it extends from the lower surface of the ceramic tube shell 3; after the second tube shell pin 8 is connected to the adhesive area 6, it extends from the lower surface of the ceramic tube shell 3; the positive and negative transient pulse current discharge channels are formed between the first tube shell pin 7 and the second tube shell pin 8 by the N+NP+N+ structure transient suppression diode core 1 and the P+PN+P+ structure transient suppression diode core 2.

[0034] The process temperature of electrode eutectic welding is 300℃±5℃, the vacuum degree is less than 0.5mbar, and the time is 1-2min; the lead wire 4 is a silicon aluminum wire with a diameter of 32μm; the cover plate 9 is used to seal the ceramic tube shell 3 through a melting process or parallel seam welding, and the material of the cover plate 9 is a gold-plated Kovar alloy.

[0035] like Figure 2 As shown, the manufacturing method of the N+NP+N+ structure transient suppression diode die 1 is:

[0036] The N-type epitaxial layer is doped with boron to form a P+ base region; and the P+ base region layer is doped with concentrated phosphorus to form N+.

[0037] The N-type epitaxial layer includes a substrate and an epitaxial layer; the epitaxial layer is located on the outer surface of the substrate.

[0038] The material parameters of the substrate are: N <111> / Arsenic doped, resistivity less than 0.005Ω·cm, thickness 450±5μm. Material parameters of the epitaxial layer are: phosphorus doped, resistivity 50-300Ω·cm, thickness 8-10μm.

[0039] The P+ base layer is formed by boron ion implantation, with an implantation window of 250μm×250μm, an implantation energy of 40kev, and an implantation dose of 3~5E14 / cm 2 The post-injection annealing process is 1100℃, 30min.

[0040] The phosphorus-rich N+ region on the P+ base layer is formed by phosphorus ion implantation, with an implantation window of 200μm×200μm, an implantation energy of 30kev, and an implantation dose of 2E16 / cm 2 The post-injection annealing process is 950℃, 30min.

[0041] The front metal layer of the N+NP+N+ structure transient suppression diode core 1 is aluminum metal with a thickness of 2μm±0.2μm; the passivation layer on the metal is SiO2 with a thickness greater than 800nm; after thinning to 250μm±10μm, the back metallization is performed, and the back metal layer of the N+NP+N+ structure transient suppression diode core 1 is Au with a thickness greater than 200nm.

[0042] like Figure 3 As shown, the manufacturing method of the P+PN+P+ structure transient suppression diode die 2 is:

[0043] The P-type epitaxial layer is doped with phosphorus to form an N+ base region, and then concentrated boron is doped on the N+ base region layer to form P+.

[0044] The P-type epitaxial layer includes a substrate and an epitaxial layer; the epitaxial layer is located on the outer surface of the substrate. The material parameters of the substrate are: <111> / Boron-doped, resistivity less than 0.004Ω.cm, thickness 450±5μm;

[0045] The material parameters of the epitaxial layer are: boron doped, resistivity of 50-300Ω·cm, and thickness of 8-10μm.

[0046] The N+ base region is formed by phosphorus ion implantation, with an implantation window of 250μm×250μm, an implantation energy of 60kev, and an implantation dose of 1~2E14 / cm 2 , the post-implantation annealing process is 1000℃, 30min;

[0047] The boron-concentrated N+ region on the N+ base layer is formed by boron ion implantation, with an implantation window of 200μm×200μm, an implantation energy of 40kev, and an implantation dose of 1E16 / cm 2 The rapid annealing process after implantation is 1180℃, 10s.

[0048] The front metal layer of the P+PN+P+ structure transient suppression diode core 2 is aluminum metal with a thickness of 2μm±0.2μm; the passivation layer on the metal is SiO2 with a thickness greater than 800nm; the back metallization is performed after the P+PN+P+ structure transient suppression diode core 2 is thinned to 250μm±10μm, and the back metal layer is Au with a thickness greater than 200nm.

[0049] The bidirectional transient suppression diode manufactured by the above method has a breakdown voltage of 5V~6V, a clamping voltage of 8V, a capacitance of 1.5pf, and a maximum bidirectional transient pulse current suppression of 15A, which can meet the transient pulse current protection requirements of most low-voltage and high-speed communication signal circuits.

[0050] When a positive transient current pulse appears at the bonding point of the tube shell lead, the Zener diode of the N+NP+N+ structure transient suppression diode core breaks down in reverse, and the transient current flows forward through a low-capacitance ordinary diode for discharge; when a negative transient current pulse appears at the bonding point of the tube shell lead, the transient current passes forward through the low-capacitance ordinary diode of the P+PN+P+ structure transient suppression diode core, and then breaks down in reverse through the Zener diode for discharge, thereby achieving the purpose of bidirectional transient voltage suppression.

[0051] The present invention adopts the NPN bipolar process and the PNP bipolar process to respectively realize two discharge channels of different transient currents, which not only simplifies the manufacturing process of the transient suppression diode core and improves the integration of each voltage regulator diode and ordinary low-capacitance diode, but also simplifies the overall packaging process, making it easier to realize mass production of the product and reducing the production cost.

[0052] Although the present invention has been disclosed as above in the form of a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art may make possible changes and modifications to the technical solution of the present invention by using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention shall fall within the protection scope of the technical solution of the present invention.

Claims

1. A low voltage and low capacitance bidirectional transient suppression diode, characterized in that: It comprises an N+NP+N+ structure transient suppression diode tube core (1), a P+PN+P+ structure transient suppression diode tube core (2), a ceramic tube shell (3), a lead (4), a pressure point (5), a bonding area (6), a first tube shell pin (7), a second tube shell pin (8) and a cover plate (9); The ceramic tube shell (3) is a hollow rectangular parallelepiped structure; the top of the ceramic tube shell (3) is provided with an opening; the upper surface of the bottom of the inner cavity of the ceramic tube shell (3) is provided with a bonding area (6); the bottom electrodes of the N+NP+N+ structure transient suppression diode tube core (1) and the P+PN+P+ structure transient suppression diode tube core (2) are eutectically welded on the bonding area (6); the pressure point (5) is provided on the upper surface of the bottom of the inner cavity of the ceramic tube shell (3); the top of the N+NP+N+ structure transient suppression diode tube core (1) and the top of the P+PN+P+ structure transient suppression diode tube core (2) are eutectic welded on the bonding area (6); the pressure point (5) is provided on the upper surface of the bottom of the inner cavity of the ceramic tube shell (3); The parts are bonded to the top of the pressure point (5) through the lead wire (4); the cover plate (9) covers the opening at the top of the ceramic tube shell (3); after the first tube shell pin (7) is connected to the pressure point (5), it extends from the lower surface of the ceramic tube shell (3); after the second tube shell pin (8) is connected to the adhesive area (6), it extends from the lower surface of the ceramic tube shell (3); between the first tube shell pin (7) and the second tube shell pin (8), a positive and negative transient pulse current discharge channel is formed by the N+NP+N+ structure transient suppression diode tube core (1) and the P+PN+P+ structure transient suppression diode tube core (2).

2. The low-voltage and low-capacitance bidirectional transient suppression diode according to claim 1, characterized in that: The process temperature of the electrode eutectic welding is 300°C ± 5°C, the vacuum degree is less than 0.5 mbar, and the time is 1-2 min; the lead wire (4) is a silicon aluminum wire with a diameter of 32 μm; The cover plate (9) is used to seal the ceramic tube shell (3) through a melting and sealing process or parallel seam welding, and the material of the cover plate (9) is a kovar alloy with a gold-plated surface.

3. The low-voltage and low-capacitance bidirectional transient suppression diode according to claim 1, characterized in that: The manufacturing method of the N+NP+N+ structure transient suppression diode core (1) is as follows: The N-type epitaxial layer is doped with boron to form a P+ base region; the P+ base region layer is doped with concentrated phosphorus to form N+; Wherein, the N-type epitaxial layer includes a substrate and an epitaxial layer; the epitaxial layer is located on the outer surface of the substrate; The material parameters of the substrate are: N <111> / Arsenic doped, resistivity less than 0.005Ω·cm, thickness 450±5μm; The material parameters of the epitaxial layer are: phosphorus doped, resistivity of 50-300Ω·cm, and thickness of 8-10μm.

4. The low-voltage and low-capacitance bidirectional transient suppression diode according to claim 3, characterized in that: The P+ base layer is formed by boron ion implantation, with an implantation window of 250 μm×250 μm, an implantation energy of 40 kev, and an implantation dose of 3 to 5 E14 / cm 2 The post-injection annealing process is 1100℃, 30min.

5. The low-voltage and low-capacitance bidirectional transient suppression diode according to claim 4, characterized in that: The concentrated phosphorus N+ region on the P+ base layer is formed by phosphorus ion implantation, with an implantation window of 200 μm×200 μm, an implantation energy of 30 kev, and an implantation dose of 2E16 / cm 2 The post-injection annealing process is 950℃, 30min.

6. The low-voltage and low-capacitance bidirectional transient suppression diode according to claim 5, characterized in that: The front metal layer of the N+NP+N+ structure transient suppression diode tube core (1) is aluminum metal with a thickness of 2μm±0.2μm; the passivation layer on the metal is SiO2 with a thickness greater than 800nm; after the chip is thinned to 250μm±10μm, back metallization is performed, and the back metal layer of the N+NP+N+ structure transient suppression diode tube core (1) is Au with a thickness greater than 200nm.

7. The low-voltage and low-capacitance bidirectional transient suppression diode according to claim 1, characterized in that: The manufacturing method of the P+PN+P+ structure transient suppression diode core (2) is as follows: The P-type epitaxial layer is doped with phosphorus to form an N+ base region, and then concentrated boron is doped on the N+ base region layer to form P+.

8. The low-voltage and low-capacitance bidirectional transient suppression diode according to claim 7, characterized in that: The P-type epitaxial layer includes a substrate and an epitaxial layer; the epitaxial layer is located on the outer surface of the substrate; The material parameters of the substrate are: <111> / Boron-doped, resistivity less than 0.004Ω.cm, thickness 450±5μm; The material parameters of the epitaxial layer are: boron doped, resistivity of 50-300Ω·cm, and thickness of 8-10μm.

9. The low-voltage and low-capacitance bidirectional transient suppression diode according to claim 8, characterized in that: The N+ base region is formed by phosphorus ion implantation, with an implantation window of 250 μm×250 μm, an implantation energy of 60 kev, and an implantation dose of 1 to 2E14 / cm 2 , the post-implantation annealing process is 1000℃, 30min; The boron-concentrated N+ region on the N+ base layer is formed by boron ion implantation, with an implantation window of 200μm×200μm, an implantation energy of 40kev, and an implantation dose of 1E16 / cm 2 The rapid annealing process after implantation is 1180℃, 10s.

10. The low-voltage and low-capacitance bidirectional transient suppression diode according to claim 9, characterized in that: The front metal layer of the P+PN+P+ structure transient suppression diode tube core (2) is aluminum metal with a thickness of 2μm±0.2μm; the passivation layer on the metal is SiO2 with a thickness greater than 800nm; the P+PN+P+ structure transient suppression diode tube core (2) is thinned to 250μm±10μm and then metallized on the back side; the back metal layer is Au with a thickness greater than 200nm.

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