Semiconductor structure and preparation method thereof

Abstract

The embodiment of the invention relates to the field of semiconductors, and provides a semiconductor structure and a preparation method thereof, and the preparation method comprises the steps: providing a substrate, and enabling the surface of the substrate to be provided with a sacrificial layer; forming a plurality of conductive columns, wherein each conductive column is located on the surface of the substrate and penetrates through the thickness of the sacrificial layer; along the thickness direction of the substrate, the sectional areas of the conductive columns are gradually reduced along the direction parallel to the surface of the substrate; removing the sacrificial layer and exposing the outer side surface of the conductive column; laterally removing a part of thickness of the conductive column along the outer side surface of the conductive column pointing to the axis direction of the conductive column; wherein in the process step of removing a part of thickness of the conductive column, the thickness of the removed conductive column is gradually reduced along the thickness direction of the substrate. According to the semiconductor structure and the preparation method thereof provided by the embodiment of the invention, the yield of the semiconductor structure can be improved at least.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the semiconductor field, and in particular to a semiconductor structure and a method for preparing the same. Background Art

[0002] With the continuous development of integrated circuit process technology, in order to improve the integration of integrated circuits, while increasing the operating speed of memory and reducing its power consumption, for example, the characteristic size of Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) devices continues to shrink, and MOSFET devices face a series of challenges.

[0003] The reduction of feature size brings about an increase in integration, but at the same time it will cause problems with the lower electrode between two adjacent transistors. For example, due to the requirement for transistor storage area, in the vertical direction, the ratio of the height to the width of the lower electrode is relatively large. In the process of forming the capacitor hole for accommodating the lower electrode, due to the etching effect of the aspect ratio, it may be impossible to etch through, that is, the bottom of the capacitor hole does not expose the capacitor window, and thus cannot meet the needs of the device; if the capacitor hole is completely etched through, the distance between the tops of the two adjacent capacitor holes is small or intersecting, resulting in the problem of short circuit between the two lower electrodes. How to improve the yield of the lower electrode and thus improve the yield of the semiconductor structure has become an important problem that needs to be solved by those skilled in the art. Summary of the invention

[0004] The embodiments of the present disclosure provide a semiconductor structure and a method for manufacturing the same, which are at least beneficial to improving the yield of the semiconductor structure.

[0005] According to some embodiments of the present disclosure, on the one hand, an embodiment of the present disclosure provides a method for preparing a semiconductor structure, comprising: providing a substrate, wherein the surface of the substrate has a sacrificial layer; forming a plurality of conductive pillars, each of the conductive pillars being located on the surface of the substrate and penetrating the thickness of the sacrificial layer; along the thickness direction of the substrate, the cross-sectional area of ​​the conductive pillar parallel to the surface of the substrate gradually decreases; removing the sacrificial layer and exposing the outer side surface of the conductive pillar; and laterally removing a portion of the thickness of the conductive pillar along the outer side surface of the conductive pillar pointing to the axial direction of the conductive pillar; wherein, in the process step of removing a portion of the thickness of the conductive pillar, the thickness of the removed conductive pillar gradually decreases along the thickness direction of the substrate.

[0006] In some embodiments, during the process step of removing the sacrificial layer, a portion of the thickness of the conductive pillar is removed laterally simultaneously.

[0007] In some embodiments, the process steps of removing the sacrificial layer and removing a portion of the thickness of the conductive column include: alternating a first etching process and a second etching process until the sacrificial layer is removed; the number X of the first etching process is equal to the number of the second etching process, and X is greater than or equal to 2; the process steps of the first etching process include: removing a portion of the sacrificial layer at a height of 1 / X and exposing an outer side surface of the conductive column at a height of 1 / X; the process steps of the second etching process include: laterally removing a portion of the thickness of the conductive column at a height of 1 / X along the outer side surface of the conductive column pointing to the axial direction of the conductive column; wherein, in the process step of removing a portion of the thickness of the conductive column, the thickness of the conductive column removed gradually decreases along the direction from the sacrificial layer to the substrate.

[0008] In some embodiments, during at least one process step of performing the first etching process, the second etching process is performed simultaneously.

[0009] In some embodiments, the second etching process is performed using a wet etching process; the concentration of the etching solution of the second etching process or the etching time gradually decreases as the number of times the second etching process is performed increases.

[0010] In some embodiments, the sacrificial layer includes at least two stacked sub-sacrificial layers, with a stop layer between every two sub-sacrificial layers; each of the first etching processes removes each of the sub-sacrificial layers; and before every two of the first etching processes, it also includes: performing a third etching process, wherein the third etching process removes part of the stop layer to expose the surface of the sub-sacrificial layer.

[0011] In some embodiments, the sacrificial layer includes a first sub-sacrificial layer and a second sub-sacrificial layer, and the first sub-sacrificial layer is located between the second sub-sacrificial layer and the substrate; the process steps of removing the sacrificial layer and removing a portion of the thickness of the conductive column include: performing the first etching process for the first time to remove the second sub-sacrificial layer; performing the second etching process for the first time, and the process steps of the first second etching process include: laterally removing the conductive column of the first thickness along the outer side surface of the conductive column pointing to the axial direction of the conductive column; performing the third etching process; performing the first etching process for the second time to remove the first sub-sacrificial layer; performing the second etching process for the second time, and the process steps of the second second etching process for the second time include: laterally removing the conductive column of the second thickness along the outer side surface of the conductive column pointing to the axial direction of the conductive column; wherein the second thickness is less than the first thickness.

[0012] In some embodiments, each remaining conductive column serves as a first electrode; after laterally removing a portion of the thickness of the conductive column, it also includes: forming a dielectric layer and a second electrode, the second electrode is located between multiple first electrodes, the dielectric layer is located between the first electrode and the second electrode, and the first electrode, the dielectric layer and the second electrode constitute a capacitor structure.

[0013] In some embodiments, after partially removing the conductive pillars in the laterally direction, the method further includes: performing a repair process on the remaining conductive pillars; the repair process includes a hydrogenation process and an annealing process.

[0014] According to some embodiments of the present disclosure, on the other hand, the embodiments of the present disclosure further provide a semiconductor structure, including: a substrate; a capacitor structure, the capacitor structure is located on the surface of the substrate, the capacitor structure includes: a plurality of first electrodes, a dielectric layer and a second electrode, the plurality of first electrodes are located on the surface of the substrate, the second electrodes are located between adjacent first electrodes, and the dielectric layer is located between the first electrode and the second electrode; each of the first electrodes includes a first side and a second side opposite to each other, the first side contacts the substrate, and the ratio of a first size of the first side to a second size of the second side is 90% to 110%.

[0015] The technical solution provided by the embodiments of the present disclosure has at least the following advantages:

[0016] In the method for preparing the semiconductor structure provided by the embodiment of the present disclosure, a conductive column with a partial thickness is removed laterally along the outer side surface of the conductive column pointing to the axial direction of the conductive column; wherein, in the process step of removing a conductive column with a partial thickness, the thickness of the removed conductive column gradually decreases along the thickness direction of the substrate. In this way, the thickness of the conductive column is etched to different degrees along the thickness direction of the substrate, thereby offsetting the problem caused by the top-wide and bottom-narrow morphology caused by the deep grooves forming the capacitor holes, so that the characteristic size of the end of the conductive column away from the substrate and the characteristic size of the end of the conductive column close to the substrate are basically consistent, solving the bending problem caused by the electrode plate formed by the conductive column and the problem of short circuit between the tops of adjacent electrode plates, and improving the yield of the capacitor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] One or more embodiments are exemplarily illustrated by pictures in the corresponding drawings, and these exemplified descriptions do not constitute a limitation on the embodiments. Unless otherwise specified, the pictures in the drawings do not constitute a scale limitation. In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the drawings required for use in the embodiments are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0018] Figure 1 A first schematic flow chart of a method for preparing a semiconductor junction provided in an embodiment of the present disclosure;

[0019] Figure 2 A second schematic flow chart of a method for preparing a semiconductor junction provided in an embodiment of the present disclosure;

[0020] Figure 3 A third schematic flow chart of a method for preparing a semiconductor junction provided in an embodiment of the present disclosure;

[0021] Figure 4 A fourth schematic flow chart of a method for preparing a semiconductor junction provided in an embodiment of the present disclosure;

[0022] Figure 5 A fifth schematic flow chart of a method for preparing a semiconductor junction provided in an embodiment of the present disclosure;

[0023] Figures 6 to 18 A schematic diagram of the structure of a semiconductor structure corresponding to each step in a method for preparing a semiconductor junction provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0024] As known from the background art, the yield rate of capacitor structures in current semiconductor structures is poor.

[0025] Analysis found that one of the reasons for the poor yield of the capacitor structure in the semiconductor structure is that in order to increase the capacitance area of ​​the capacitor structure, a higher first electrode is generally set in the direction perpendicular to the surface of the substrate to increase the storage area. In this way, the thickness of the sacrificial layer formed to accommodate the first electrode will also be set larger accordingly, that is, the depth of the capacitor hole to be formed later is larger. But at the same time, the positions in the active area are set more densely to ensure that more transistors can be formed within a unit area, so the distance between the first electrodes of the active area used for connection is smaller, so it can be deduced that the depth-to-width ratio of the capacitor hole is larger. Due to the load effect of etching, that is, the etching rate will show a nonlinear relationship corresponding to the etching pattern area, etching line width, etc. under the characteristic variable. In this way, the obtained capacitor hole presents the problem of gradually decreasing line width, and the first electrode located in the capacitor hole also has the same morphology, so there may be a problem that the sacrificial layer is not completely etched through and the capacitor plug located under the sacrificial layer cannot be exposed or there is a short circuit between adjacent first electrodes.

[0026] The disclosed embodiment provides a method for preparing a semiconductor structure, wherein after forming a conductive column, a portion of the thickness of the conductive column is laterally removed along the outer side surface of the conductive column pointing to the axial direction of the conductive column; wherein, in the process step of removing the portion of the thickness of the conductive column, the thickness of the removed conductive column gradually decreases along the thickness direction of the substrate. In this way, the thickness of the conductive column is etched to different degrees along the thickness direction of the substrate, thereby offsetting the problem caused by the top-wide and bottom-narrow morphology caused by the deep grooves forming the capacitor holes, so that the characteristic size of the end of the conductive column away from the substrate and the characteristic size of the end of the conductive column close to the substrate are basically consistent, solving the bending problem caused by the electrode plate formed by the conductive column and the problem of short circuit between the tops of adjacent electrode plates, and improving the yield of the semiconductor structure.

[0027] The following will describe the various embodiments of the present disclosure in detail with reference to the accompanying drawings. However, it will be appreciated by those skilled in the art that in the various embodiments of the present disclosure, many technical details are provided in order to enable the reader to better understand the present disclosure. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in the present disclosure can be implemented.

[0028] Figure 1 A first schematic flow chart of a method for preparing a semiconductor junction provided in an embodiment of the present disclosure; Figure 2 A second schematic flow chart of a method for preparing a semiconductor junction provided in an embodiment of the present disclosure; Figure 3 A third schematic flow chart of a method for preparing a semiconductor junction provided in an embodiment of the present disclosure; Figure 4 A fourth schematic flow chart of a method for preparing a semiconductor junction provided in an embodiment of the present disclosure; Figure 5A fifth schematic flow chart of a method for preparing a semiconductor junction provided in an embodiment of the present disclosure; Figures 6 to 18 This is a schematic diagram of the structure of the semiconductor structure corresponding to each step in the method for preparing a semiconductor junction provided in an embodiment of the present disclosure. Figure 7 for Figure 6 Schematic diagram of the cross-sectional structure along section A1-A2. Fig.18 for Fig.17 Schematic diagram of the cross-sectional structure along section A1-A2.

[0029] According to some embodiments of the present disclosure, on one hand, a method for preparing a semiconductor structure is provided to improve the yield of the semiconductor structure.

[0030] refer to Figure 1 to Figure 5 An embodiment of the present disclosure provides a preparation method, comprising: S10, providing a substrate, wherein the surface of the substrate has a sacrificial layer.

[0031] S20, forming a plurality of conductive pillars, each of which is located on the surface of the substrate and penetrates the thickness of the sacrificial layer; along the thickness direction of the substrate, the cross-sectional area of ​​the conductive pillar parallel to the surface of the substrate gradually decreases.

[0032] S30, removing the sacrificial layer and exposing the outer side of the conductive pillar.

[0033] S40, removing a portion of the thickness of the conductive column laterally along the outer side of the conductive column pointing to the axial direction of the conductive column; wherein, in the process step of removing a portion of the thickness of the conductive column, the thickness of the removed conductive column gradually decreases along the thickness direction of the substrate. In this way, the thickness of the conductive column is etched to different degrees along the thickness direction of the substrate, thereby offsetting the problem caused by the top-wide and bottom-narrow morphology caused by the deep grooves forming the capacitor holes, so that the characteristic size of the end of the conductive column away from the substrate and the characteristic size of the end of the conductive column close to the substrate are basically consistent, solving the bending problem caused by the electrode plate formed by the conductive column and the problem of short circuit between the tops of adjacent electrode plates, and improving the yield of the semiconductor structure.

[0034] In some embodiments, the thickness of the conductive pillar removed is gradually reduced by adjusting the concentration of the etching solution or the etching time of the second etching process.

[0035] In some embodiments, the concentration of the etching solution or the etching time of the second etching process gradually decreases as the number of times of the second etching process increases.

[0036] Among them, steps S30 and S40 can be performed simultaneously, that is, in the process step of removing the sacrificial layer, the conductive pillars with a partial thickness are removed laterally synchronously. In this way, in one process step, the sacrificial layer and the conductive pillars with a partial thickness are removed synchronously, thereby saving process steps and reducing the waiting time of the two process steps of removing the sacrificial layer and removing the conductive pillars with a partial thickness, thereby saving the time of the entire process.

[0037] In addition, since the waiting time for the two process steps of removing the sacrificial layer and removing the partial thickness conductive pillar is reduced, the poor surface quality caused by the contamination of the conductive pillar can be avoided. The contamination problem includes oxidation reaction or byproducts of removing the sacrificial layer.

[0038] In some embodiments, reference Figures 3 to 5 , the process steps of S30 and S40, i.e., the process steps of removing the sacrificial layer and removing a portion of the thickness of the conductive column, include: alternately performing the first etching process and the second etching process until the sacrificial layer is removed; the number X of the first etching process is equal to the number of the second etching process, and X is greater than or equal to 2; the process steps of the first etching process include: removing a portion of the sacrificial layer of 1 / X height and exposing the outer side surface of the conductive column of 1 / X height; the process steps of the second etching process include: laterally removing a portion of the thickness of the conductive column of 1 / X height along the outer side surface of the conductive column pointing to the axial direction of the conductive column; wherein, in the process step of removing a portion of the thickness of the conductive column, the thickness of the removed conductive column gradually decreases along the direction of the sacrificial layer pointing to the substrate.

[0039] In this way, the conductive column is laterally thinned through multiple repetitive first etching processes and second etching processes to control the thickness range of the conductive column thinning, and the thickness range of each thinning is more accurately controlled, so that the morphology of the conductive column can be accurately obtained as a vertical morphology and characteristic size.

[0040] It is understandable that although the increase in the number of X can increase the accuracy of the vertical morphology of the conductive pillar, the increase in X, that is, the increase in the number of the first etching process and the second etching process, also brings about an increase in the preparation cost. Based on the above reasons, the range of X is within 2 to 10, so as to balance the accuracy of the vertical morphology of the side morphology of the conductive pillar and the preparation cost.

[0041] It is worth noting that Figure 3 The "Y" of S30Y in is equal to 2*X-1, Figure 3 The "P" of S30P in is equal to 2*X. Similarly, Figure 5 The "M" of S30M is equal to 3*X-2, and the "N" of S30N is equal to 3*X-1. For example, when X is 3, S30Y is S305, S30P is S306, S30M is S307, and S30N is S308.

[0042] In some embodiments, reference Figure 4 , in the process step of performing the first etching process at least once, the second etching process is performed synchronously. That is, step S301 includes: performing the first second etching process at the same time as performing the first first etching process. In this way, in one process step, the sacrificial layer of 1 / X thickness and the conductive column of partial thickness are removed synchronously, thereby saving process steps and reducing the waiting time of the two process steps of removing the sacrificial layer and removing the conductive column of partial thickness, thereby saving the time of the entire process. In addition, since the waiting time of the two process steps of removing the sacrificial layer and removing the conductive column of partial thickness is reduced, the poor surface quality caused by the contamination problem of the conductive column can be avoided.

[0043] S50, repairing the remaining conductive columns.

[0044] In some embodiments, the repair process is used to alleviate the etching damage caused by the lateral removal of the conductive column, thereby reducing the surface defects on the surface of the conductive column, improving the contact performance between the conductive column and the subsequently formed dielectric layer and the performance of the conductive column itself, thereby avoiding the problem of leakage current in the conductive column.

[0045] In some embodiments, the repair process includes hydrogenation and annealing. The mechanism of hydrogenation is that hydrogen atoms enter the lattice gaps of the material of the conductive column, so that hydrogen ions occupy the material defect positions, thereby reducing the number of lattice defects of the conductive column, that is, improving the surface defect problem of the conductive column macroscopically. The mechanism of annealing is to accelerate the diffusion of metal particles or element particles in the conductive column itself, thereby eliminating or improving defects and residual stresses that occur in the process and improving the performance of the conductive column itself.

[0046] S60, each remaining conductive column is used as a first electrode; a dielectric layer and a second electrode are formed, wherein the second electrode is located between the plurality of first electrodes, the dielectric layer is located between the first electrode and the second electrode, and the first electrode, the dielectric layer and the second electrode constitute a capacitor structure.

[0047] Among them, reference Figure 2 The method for preparing the semiconductor structure may not include the step of repairing the remaining conductive pillars, but directly form a dielectric layer and a second electrode on the outer side of the etched conductive pillars.

[0048] The following will be combined Figures 6 to 18 right Figure 1 to Figure 5 The method for preparing the semiconductor structure shown is described in detail.

[0049] refer to Figure 6 and Figure 7 , providing a substrate, wherein a sacrificial layer is provided on a surface of the substrate.

[0050] In some embodiments, the semiconductor structure can be a memory. The semiconductor structure includes an array area 11 and a peripheral area 12. The array area 11 is the core area of ​​the memory, which is used to store data; the peripheral area 12 is the control area of ​​the memory, which is used to control the writing and reading of data in the array area 11. The array area 11 includes a storage capacitor and a switch tube, wherein the storage capacitor is used to store data; the switch tube in the array area 11 is used to control the input and output of data in the storage capacitor. The peripheral area 12 also includes a switch tube, which is used to form a control circuit to realize the control of writing and reading data in the array area 11.

[0051] In some embodiments, the base 10 may include a stacked substrate 100 and an isolation layer 102 , and the sacrificial layer 120 is located on the surface of the isolation layer 102 .

[0052] In some embodiments, the substrate 100 may be a semiconductor material, and the semiconductor material includes silicon, silicon germanium, or germanium. The substrate has a P-type doping element or an N-type doping element. The N-type doping element may be a Group V element such as phosphorus (P), bismuth (Bi), antimony (Sb), or arsenic (As), and the P-type doping element may be a Group III element such as boron (B), aluminum (Al), gallium (Ga), or indium (In).

[0053] In some embodiments, the material of the isolation layer 102 may be silicon oxide, silicon nitride, silicon carbonitride or other materials with high dielectric constants. Exemplarily, the material of the isolation layer 102 is silicon nitride, which not only has high dielectric properties, but also has high hardness, thereby ensuring that the bit line 108 and the capacitor plug 112 located in the isolation layer 102 are less likely to deform their profiles, which is beneficial to improving the yield of the semiconductor structure. In some embodiments, the isolation layer 102 may be a multi-layer film layer.

[0054] In some embodiments, the substrate 10 further includes an active layer 101, which is located in the array region 11 and the peripheral region 12. The active layer 101 may include a channel region and a first source and drain region and a second source and drain region located at both ends of the channel region. The bit line 108 and the capacitor plug 112 are both electrically connected to the first source and drain region or the second source and drain region of the active layer 101.

[0055] In some embodiments, the active layer 101 and the substrate 100 can be prepared from the same original substrate. Part of the thickness of the original substrate is patterned to form an active layer 101 arranged at intervals, and the remaining original substrate serves as the substrate 100. There is no interface state between the active layer 101 and the substrate 100. Instead, the active layer 101 and the substrate 100 are two different film layers divided due to different definitions of different functional limited areas. The two are actually the same film layer.

[0056] In some embodiments, adjacent active layers 101 include an isolation structure 105 and a shallow trench isolation structure (STI) 104, and the isolation structure 105 and the shallow trench isolation structure 104 are used to divide and isolate the spaced active layers 101, so as to define transistors one by one in subsequent processes, and select the specified transistor through the bit line and word line to write and read data.

[0057] In some embodiments, the isolation structure 105 and the shallow trench isolation structure 104 are isolation structures formed of isolation materials, and the isolation structure 105 and the shallow trench isolation structure 104 can be a single-layer film layer or a multi-layer film layer.

[0058] In some embodiments, the semiconductor structure includes a bit line 108 and a word line 106, the bit line 108 is located in the array region 11, and the bit line 108 is electrically connected to one of the first source and drain region or the second source and drain region of the active layer 101. The material of the bit line 108 includes at least one of tungsten, tantalum, titanium, tantalum nitride or titanium nitride, which is beneficial to reduce the resistance of the bit line 104 itself.

[0059] The word line 106 is located in the array region 11, and is located in the isolation structure 105 at one side of the channel region. The material of the word line 106 includes at least one of tungsten, tantalum, titanium, tantalum nitride or titanium nitride.

[0060] In some embodiments, a first dielectric layer 109 is disposed on a side of the bit line 108 away from the active layer 101, and the first dielectric layer 109 is used to protect and isolate the bit line 108 from the capacitor plug 112. The material of the first dielectric layer 109 includes silicon nitride or silicon nitride oxide.

[0061] In some embodiments, the semiconductor structure includes: a gate structure 103 , and the gate structure 103 is located in the peripheral region 12 .

[0062] In some embodiments, the semiconductor structure further includes: a contact layer 111 , the contact layer 111 is located between the capacitor plug 112 and the active layer 101 , and the contact layer 111 and the capacitor plug 112 together constitute a capacitor contact structure 107 .

[0063] The contact layer 111 may be a metal silicide layer or a polysilicon layer. The metal silicide layer may reduce the contact resistance between the capacitor contact structure 107 and the active layer 101 .

[0064] In some embodiments, the sacrificial layer 120 includes at least two stacked sub-sacrificial layers, and a stop layer 113 is provided between each two sub-sacrificial layers. In the same etching process, the etching rate of the sub-sacrificial layer is different from the etching rate of the stop layer 113, so that the stop layer 113 can be used as a stop layer for each first etching process, thereby effectively controlling the etching degree of the first etching process.

[0065] In addition, the hardness of the stop layer 113 is greater than that of the sub-sacrificial layer, so that the stop layer 113 can serve as a supporting material in an overall topography with a relatively high height to prevent the sub-sacrificial layer from being deformed.

[0066] In some embodiments, the sacrificial layer 120 includes a first sub-sacrificial layer 121 and a second sub-sacrificial layer 122 . The first sub-sacrificial layer 121 is located between the second sub-sacrificial layer 122 and the substrate 10 . The stop layer 113 is located between the first sub-sacrificial layer 121 and the second sub-sacrificial layer 122 .

[0067] In some embodiments, the material of the first sacrificial sub-layer 121 includes silicon oxide, silicon nitride, silicon oxynitride, or other insulating materials.

[0068] In some embodiments, the material of the second sacrificial sub-layer 122 includes silicon oxide, silicon nitride, silicon oxynitride, or other insulating materials.

[0069] In some embodiments, the material of the first sub-sacrificial layer 121 is the same as the material of the second sub-sacrificial layer 122 .

[0070] In some embodiments, the material of the stop layer 113 includes silicon nitride, silicon oxynitride, or silicon carbide.

[0071] The thickness of each sub-sacrificial layer is greater than the thickness of the stop layer 113 , so that the thickness of each thinning of the conductive pillar 116 can be accurately controlled within a limited height range by the thickness of the sub-sacrificial layer.

[0072] In some embodiments, the top surface of the sacrificial layer 120 away from the substrate 10 further has a hard mask layer 114 , and the hard mask layer 114 is used to ensure the regularity of the morphology of the sacrificial layer 120 during the etching process.

[0073] In some embodiments, the material of the hard mask layer 114 includes silicon nitride, silicon oxynitride, or silicon carbide.

[0074] refer to Figure 8 The hard mask layer 114 , the sacrificial layer 120 , the stop layer 113 , the capacitor plug 112 and the first dielectric layer 109 are patterned to form a capacitor hole 115 .

[0075] The bottom of the capacitor hole 115 exposes the top surface of the capacitor plug 112 .

[0076] Since the thickness of the sacrificial layer 120 is relatively thick and the distance between the capacitor plugs 112 is relatively close, the depth-width ratio of the capacitor hole 115 is relatively large. Due to the loading effect of etching, the obtained capacitor hole 115 presents the problem of gradually decreasing line width.

[0077] refer to Fig. 9 , forming a plurality of conductive pillars 116, each conductive pillar 116 is located on the surface of the substrate 10 and penetrates the thickness of the sacrificial layer 120; along the thickness direction of the substrate 10, the cross-sectional area of ​​the conductive pillar 116 parallel to the surface of the substrate 10 gradually decreases. Each conductive pillar 116 is located in each capacitor hole.

[0078] It can be understood that, since the capacitor hole presents the problem of gradually decreasing line width, the conductive pillar 116 located in the capacitor hole also has the same morphology, that is, along the thickness direction of the substrate 10, the cross-sectional area of ​​the conductive pillar 116 parallel to the surface of the substrate 10 gradually decreases. If the cross section of the conductive pillar 116 is circular, the line width represents the cross-sectional area.

[0079] In some embodiments, the side of the conductive pillar 116 away from the substrate 10 has a first line width D1 , and the side of the conductive pillar 116 close to the substrate 10 has a second line width D2 , and the first line width D1 is greater than the second line width D2 .

[0080] In some embodiments, the material of the conductive pillar 116 includes at least one of tungsten, tantalum, titanium, tantalum nitride, or titanium nitride.

[0081] refer to Fig.10 , Fig.11 as well as Fig.12 , a mask layer 118 having a through hole 119 is formed, the mask layer 118 is located on the surfaces of the conductive pillar 116 and the sacrificial layer 120 , and the through hole 119 at least exposes the surface of the sacrificial layer 120 .

[0082] In some embodiments, the mask layer 118 may be a photoresist or a hard mask.

[0083] In some embodiments, reference Fig.11 , the through hole 119 only exposes the surface of the hard mask layer 114, but does not expose the top surface of the conductive pillar 116. Then, the first etching process is performed first and then the second etching process is performed. Fig.12 , the through hole 119 not only exposes the surface of the hard mask layer 114 , but also exposes a portion of the top surface of the conductive pillar 116 , so the second etching process can be performed simultaneously with the first etching process.

[0084] Understandably, Fig.12 The fact that one through hole 119 can expose the top surfaces of four conductive pillars 116 is only taken as an example. In the embodiment of the present disclosure, the number of conductive pillars 116 that can be exposed by one through hole 119 may be 1, 2, or 3.

[0085] refer to Fig.13 , a first first etching process is performed to remove the second sacrificial sub-layer 122 .

[0086] In some embodiments, a wet etching process is used to remove the second sub-sacrificial layer 122, for example, an acid solution is used to remove the second sub-sacrificial layer 122, and the acid solution may include hydrofluoric acid, a mixed solution of hydrofluoric acid and nitric acid, or a mixed solution of HF, NNO3 and C3H8O3. The content of the fluorine element determines the etching rate of removing the second sub-sacrificial layer 122. When the fluorine element content is greater, the etching rate of removing the second sub-sacrificial layer 122 is greater.

[0087] refer to Fig.14 , performing a first second etching process, the process steps of the first second etching process include: removing the conductive pillar 116 of a first thickness laterally along the outer side surface of the conductive pillar 116 pointing to the axial direction of the conductive pillar 116.

[0088] In some embodiments, the second etching process is performed using a wet etching process.

[0089] In some embodiments, the etching solution of the wet etching process includes any one or more of hydrofluoric acid, sulfuric acid, hydrogen peroxide or ammonium fluoride aqueous solution.

[0090] In some embodiments, the etching solution of the wet etching process can be a mixed solution, including LAL5K (NH4F: HF (49%): H2O = 1:1:5 ~ 1:1:10), DHF (H2O: HF (49%)) = 1000:1 ~ 1:1) or DSP (H2SO4 (96%): H2O2 (30%) = 8.46:3.83 + 300ppm DHF).

[0091] In some embodiments, the etched conductive pillar 116 has a third line width D3 at one end away from the substrate and a fourth line width D4 at one end close to the stop layer 113. The first thickness L1 is equal to the difference between the first line width D1 and the third line width D3. The first thickness L1 is 1 nm to 5 nm.

[0092] It can be understood that the first thickness L1 is the difference between the first line width D1 and the second line width D3, which refers to the conductive column 116 with the maximum thickness etched in the first second etching process, and the partial thickness of the conductive column 116 etched subsequently is less than the first thickness L1.

[0093] Due to the isotropy of the wet etching process, a portion of the conductive pillar 116 located in the stop layer 113 may be etched.

[0094] In some embodiments, the second sub-sacrificial layer 122 is divided into a plurality of regions with the same thickness, and the concentration of the etching solution and the etching time of the second etching process are reduced according to the distance of the region from the substrate. For example, in the first region, the concentration of the etching solution is 49%, in the second region, the concentration of the etching solution is 35%, and in the third region closest to the substrate, the concentration of the etching solution is 28%.

[0095] In some embodiments, the second etching process uses any one of plasma etching process, reactive ion etching process, sputtering etching process, ion milling process, reverse ion beam etching process or ion beam assisted etching process to etch the film. For example, the plasma etching process is used to remove the conductive pillar 116 laterally, and the plasma generated in the gaseous state is used to physically and chemically react with the conductive pillar 116 exposed to the plasma to remove a portion of the thickness of the conductive pillar 116. Since the plasma is also in a gaseous state, the migration speed and distance of the plasma, as well as the etching caliber also affect the thickness of the etched conductive pillar 116. First, since the conductive pillar 116 presents a trend of high aspect ratio, the caliber of the groove after removing the first sub-sacrificial layer is small, and the plasma is blocked from entering the groove. In addition, the depth of the groove is deep, and the plasma cannot reach the bottom of the groove or the amount reaching the bottom of the groove is small, so the etching thickness of the conductive pillar 116 tends to be inversely proportional to the distance between the etched conductive pillar 116 area and the surface of the substrate 10.

[0096] refer to Fig.15 , a third etching process is performed, and the third etching process removes part of the stop layer 113 to expose the surface of the first sacrificial sub-layer 121.

[0097] Among them, removing part of the stop layer 113 and exposing the surface of the first sub-sacrificial layer 121 means etching the stop layer 113 along the first through hole 119 to form a through hole with a size similar to that of the first through hole 119, and the remaining stop layer 113 serves as a supporting layer for the subsequent capacitor structure to ensure the stability of the capacitor structure.

[0098] Continue to refer Fig.15 , a second first etching process is performed to remove the first sacrificial sub-layer 121 .

[0099] refer to Fig.16 , a second second etching process is performed, and the process steps of the second second etching process include: removing the conductive pillar 116 of a second thickness laterally along the outer side surface of the conductive pillar 116 pointing to the axial direction of the conductive pillar 116; wherein the second thickness L2 is less than the first thickness L1.

[0100] In some embodiments, the concentration of the etching solution or the etching time of the second etching process gradually decreases as the number of the second etching process increases. That is, either the concentration of the etching solution or the etching time of the first second etching process is greater than the concentration of the etching solution or the etching time of the second second etching process. For example, the concentration of the etching solution of the first second etching process is 25%, and the concentration of the etching solution of the second second etching process is 12%.

[0101] In some embodiments, the etched conductive pillar 116 has a fifth line width D5 at one end close to the substrate. The second thickness L2 is equal to the difference between the line width of the conductive pillar 116 at the junction of the stop layer 113 and the first sub-sacrificial layer 121 and the fourth line width D4. The second thickness L2 is less than 1 nm.

[0102] In some embodiments, due to the isotropy of etching, the conductive pillar 116 at one end away from the substrate may be etched twice, so that the line width of the conductive pillar 116 away from the substrate 10 is smaller than the line width of the conductive pillar 116 close to the substrate 10 .

[0103] In some embodiments, each remaining conductive pillar 116 serves as a first electrode 131, each first electrode 131 includes a first side 31 and a second side 32 opposite to each other, the first side 31 contacts the substrate 10, and the ratio of the first dimension of the first side 31 to the second dimension of the second side 32 is 90% to 110%. The first dimension is the second line width D2, and the second dimension is the third line width D3.

[0104] In some embodiments, reference Fig.12 , the through hole exposes the top surface of the conductive pillar 116, then the first etching process and the second etching process are performed simultaneously, thereby saving process steps and reducing the waiting time of the two process steps of removing the sacrificial layer and removing a portion of the thickness of the conductive pillar 116, thereby saving the time of the entire process. In addition, since the waiting time of the two process steps of removing the sacrificial layer and removing a portion of the thickness of the conductive pillar 116 is reduced, the poor surface quality caused by the contamination problem of the conductive pillar 116 can be avoided.

[0105] In some embodiments, the sacrificial layer in the array region 11 is removed while the sacrificial layer in the peripheral region 12 is removed simultaneously.

[0106] refer to Figure 17 to Figure 18 , the remaining conductive pillars 116 are repaired.

[0107] In some embodiments, the repair process is used to alleviate the etching damage caused by the lateral removal of the conductive pillar 116, thereby reducing the surface defects on the surface of the conductive pillar 116, improving the contact performance between the conductive pillar 116 and the subsequently formed dielectric layer and the performance of the conductive pillar 116 itself, thereby avoiding the problem of leakage current in the conductive pillar 116.

[0108] In some embodiments, the repair process includes a hydrogenation process and an annealing process.

[0109] Continue to refer Figure 17 to Figure 18 , forming a dielectric layer 132 and a second electrode 133 , the second electrode 133 is located between the plurality of first electrodes 131 , the dielectric layer 132 is located between the first electrode 131 and the second electrode 133 , and the first electrode 131 , the dielectric layer 132 and the second electrode 133 constitute a capacitor structure 130 .

[0110] In some embodiments, the dielectric layer 132 is any one or more of silicon oxide, silicon nitride, and high dielectric constant materials, and the high dielectric constant materials may include hafnium oxide, zirconium oxide, aluminum oxide, lanthanum oxide, titanium oxide, tantalum oxide, niobium oxide, or strontium titanate. The material of the second electrode 133 is titanium, titanium nitride, ruthenium, cobalt, nickel, or tungsten-doped polysilicon. Adjacent transistors share the second electrode, which can increase the area of ​​the storage structure, that is, increase the storage area, thereby improving the charge holding capacity of the semiconductor structure.

[0111] The disclosed embodiment provides a method for preparing a semiconductor structure, wherein after forming a conductive column 116, a portion of the thickness of the conductive column 116 is removed laterally along the outer side surface of the conductive column 116 pointing to the axial direction of the conductive column 116; wherein, in the process step of removing a portion of the thickness of the conductive column 116, the thickness of the removed conductive column 116 gradually decreases along the thickness direction of the substrate. In this way, the thickness of the conductive column 116 is etched to different degrees along the thickness direction of the substrate 10, thereby offsetting the problem caused by the top-wide and bottom-narrow morphology caused by the deep grooves forming the capacitor hole 115, so that the characteristic size of the end of the conductive column 116 away from the substrate and the characteristic size of the end of the conductive column 116 close to the substrate are basically consistent, solving the bending problem caused by the electrode plate formed by the conductive column 116 and the problem of short circuit between the tops of adjacent electrode plates, and improving the yield of the semiconductor structure.

[0112] In addition, since part of the thickness of the conductive column is removed laterally after the conductive column is formed, the risk of top phase short circuit can be ignored during the preparation of the first electrode 131, so that the bottom size of the capacitor hole can be set as large as possible, thereby increasing the contact area between the first electrode and the capacitor plug and improving the first electrode. The problem of bending and breaking caused by insufficient etching of the capacitor hole area is reduced.

[0113] Correspondingly, another aspect of the embodiments of the present disclosure further provides a semiconductor structure, which can be prepared by using any of the methods for preparing the semiconductor structure in the above embodiments. The same elements as those in the above embodiments will not be described in detail here.

[0114] refer to Fig.17 as well as Fig.18 According to some embodiments of the present disclosure, on the other hand, the embodiments of the present disclosure further provide a semiconductor structure, including: a substrate 10; a capacitor structure 130, the capacitor structure 130 is located on the surface of the substrate 10, the capacitor structure 130 includes: a plurality of first electrodes 131, a dielectric layer 132 and a second electrode 133, the plurality of first electrodes 131 are located on the surface of the substrate 10, the second electrode 133 is located between adjacent first electrodes 131, and the dielectric layer 132 is located between the first electrode 131 and the second electrode 133; each first electrode 131 includes a first side 31 and a second side 32 opposite to each other, the first side 31 is in contact with the substrate 10, and the ratio of a first size of the first side 31 to a second size of the second side 32 is 90% to 110%.

[0115] In some embodiments, the semiconductor structure may be a memory, and includes an array region 11 and a peripheral region 12. The array region 11 is a core region of the memory, used to store data; the peripheral region 12 is a control region of the memory, used to control the writing and reading of data in the array region 11.

[0116] In some embodiments, the base 10 may include a stacked substrate 100 and an isolation layer 102. The substrate 100 may be a semiconductor material, and the semiconductor material includes silicon, silicon germanium or germanium. The substrate has a P-type doping element or an N-type doping element. The material of the isolation layer 102 may be silicon oxide, silicon nitride, silicon carbonitride or other materials with a high dielectric constant. The isolation layer 102 may be a multilayer film layer.

[0117] In some embodiments, the substrate 10 further includes an active layer 101, which is located in the array region 11 and the peripheral region 12. The active layer 101 may include a channel region and a first source and drain region and a second source and drain region located at both ends of the channel region. The bit line 108 and the capacitor plug 112 are both electrically connected to the first source and drain region or the second source and drain region of the active layer 101.

[0118] In some embodiments, adjacent active layers 101 include an isolation structure 105 and a shallow trench isolation structure 104, and the isolation structure 105 and the shallow trench isolation structure 104 are used to divide and isolate the spaced active layers 101, so as to define transistors one by one in subsequent processes, and select the specified transistor through the bit line and word line to write and read data.

[0119] In some embodiments, the isolation structure 105 and the shallow trench isolation structure 104 are isolation structures formed of isolation materials, and the isolation structure 105 and the shallow trench isolation structure 104 can be a single-layer film layer or a multi-layer film layer.

[0120] In some embodiments, the semiconductor structure includes a bit line 108 and a word line 106, the bit line 104 is located in the array region 11, and the bit line 104 is electrically connected to one of the first source and drain region or the second source and drain region of the active layer 101. The word line 106 is located in the array region 11, and the word line 106 is located in the isolation structure 105 on one side of the channel region.

[0121] In some embodiments, a first dielectric layer 109 is disposed on a side of the bit line 108 away from the active layer 101, and the first dielectric layer 109 is used to protect and isolate the bit line 108 from the capacitor plug 112. The material of the first dielectric layer 109 includes silicon nitride or silicon nitride oxide.

[0122] In some embodiments, the semiconductor structure includes a gate structure 103 , and the gate structure 103 is located in the peripheral region 12 .

[0123] In some embodiments, the semiconductor structure further includes: a contact layer 111, the contact layer 111 is located between the capacitor plug 112 and the active layer 101, and the contact layer 111 and the capacitor plug 112 together form a capacitor contact structure 107. The contact layer 111 may be a metal silicide layer or a polysilicon layer.

[0124] In some embodiments, the first electrode 131 is in electrical contact with the capacitor plug 112. The end of the first electrode 131 in contact with the capacitor plug 112 is a first side 31, and the first side 31 has a second line width D2. The second line width D2 is the first size. The end of the first electrode 131 away from the substrate 10 is a second side 32, and the second side 32 has a third line width D3, and the third line width D3 is the second size.

[0125] The ratio of the first dimension of the first side 31 to the second dimension of the second side 32 is 90% to 110%, that is, the ratio of the second line width D2 to the third line width D3 is 90% to 110%. In this way, the morphology of the first electrode is a relatively vertical morphology or the bottom and top surfaces of the first electrode 131 are similar in size, which can avoid the bending problem caused by the small bottom line width of the first electrode and the short circuit problem between the tops of adjacent electrode plates, and can improve the yield of the semiconductor structure.

[0126] In some embodiments, the material of the first electrode 131 includes at least one of tungsten, tantalum, titanium, tantalum nitride or titanium nitride. The dielectric layer 132 is any one or more of silicon oxide, silicon nitride, and high dielectric constant materials, and the high dielectric constant material may include hafnium oxide, zirconium oxide, aluminum oxide, lanthanum oxide, titanium oxide, tantalum oxide, niobium oxide or strontium titanate. The material of the second electrode 133 is titanium, titanium nitride, ruthenium, cobalt, nickel, or tungsten-doped polysilicon.

[0127] Those skilled in the art can understand that the above-mentioned embodiments are specific examples for realizing the present disclosure, and in practical applications, various changes can be made to them in form and details without departing from the spirit and scope of the present disclosure. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present disclosure, so the protection scope of the present disclosure shall be based on the scope defined in the claims.

Claims

1. A method for preparing a semiconductor structure, characterized in that: include: Providing a substrate, wherein a surface of the substrate has a sacrificial layer; forming a plurality of conductive pillars, each of which is located on the surface of the substrate and penetrates the thickness of the sacrificial layer; Along the thickness direction of the substrate, the cross-sectional area of ​​the conductive pillar parallel to the surface of the substrate gradually decreases; removing the sacrificial layer and exposing the outer side of the conductive column; A portion of the thickness of the conductive column is removed laterally along the outer side surface of the conductive column pointing to the axial direction of the conductive column; wherein, in the process step of removing a portion of the thickness of the conductive column, the thickness of the removed conductive column gradually decreases along the thickness direction of the substrate.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that: In the process step of removing the sacrificial layer, a portion of the thickness of the conductive pillar is removed laterally simultaneously.

3. The method for preparing a semiconductor structure according to claim 1 or 2, characterized in that: The process steps of removing the sacrificial layer and removing a portion of the thickness of the conductive pillar include: alternately performing a first etching process and a second etching process until the sacrificial layer is removed; the number X of the first etching process is equal to the number of the second etching process, and X is greater than or equal to 2; The process steps of the first etching process include: removing the sacrificial layer at a height of 1 / X and exposing the outer side surface of the conductive pillar at a height of 1 / X; The process steps of the second etching process include: removing part of the thickness of the conductive column by 1 / X of its height laterally along the outer side surface of the conductive column pointing to the axial direction of the conductive column; wherein, in the process step of removing part of the thickness of the conductive column, the thickness of the conductive column removed gradually decreases along the direction of the sacrificial layer pointing to the substrate.

4. The method for preparing a semiconductor structure according to claim 3, characterized in that: The second etching process is performed simultaneously during at least one process step of performing the first etching process.

5. The method for preparing a semiconductor structure according to claim 3, characterized in that: The second etching process is performed by a wet etching process; the concentration of the etching solution of the second etching process or the etching time gradually decreases as the number of times of the second etching process increases.

6. The method for preparing a semiconductor structure according to claim 3, characterized in that: The sacrificial layer comprises at least two stacked sub-sacrificial layers, with a stop layer between every two sub-sacrificial layers; each of the first etching processes removes each of the sub-sacrificial layers; Before every two of the first etching processes, the method further includes: performing a third etching process, wherein the third etching process removes a portion of the stop layer to expose the surface of the sub-sacrificial layer.

7. The method for preparing a semiconductor structure according to claim 6, characterized in that: The sacrificial layer comprises a first sub-sacrificial layer and a second sub-sacrificial layer, wherein the first sub-sacrificial layer is located between the second sub-sacrificial layer and the substrate; The process steps of removing the sacrificial layer and removing a portion of the thickness of the conductive pillar include: performing the first etching process for the first time to remove the second sub-sacrificial layer; Performing the second etching process for the first time, wherein the process steps of the second etching process for the first time include: removing the conductive pillar with a first thickness laterally along the outer side surface of the conductive pillar pointing to the axial direction of the conductive pillar; performing the third etching process; performing the first etching process for a second time to remove the first sacrificial sub-layer; The second etching process is performed for the second time, and the process steps of the second etching process include: removing the conductive column of a second thickness laterally along the outer side surface of the conductive column pointing to the axial direction of the conductive column; wherein the second thickness is less than the first thickness.

8. The method for preparing a semiconductor structure according to claim 1, characterized in that: Each of the remaining conductive pillars serves as a first electrode; After partially removing the conductive pillar in the side, the method further includes: forming a dielectric layer and a second electrode, wherein the second electrode is located between the first electrodes, the dielectric layer is located between the first electrode and the second electrode, and the first electrode, the dielectric layer and the second electrode constitute a capacitor structure.

9. The method for preparing a semiconductor structure according to claim 1 or 8, characterized in that: After partially removing the conductive pillars in the laterally direction, the method further includes: performing a repair process on the remaining conductive pillars; the repair process includes a hydrogenation process and an annealing process.

10. A semiconductor structure, characterized in that: include: substrate; A capacitor structure, the capacitor structure is located on the surface of the substrate, the capacitor structure comprises: a plurality of first electrodes, a dielectric layer and a second electrode, the plurality of first electrodes are located on the surface of the substrate, the second electrodes are located between adjacent first electrodes, and the dielectric layer is located between the first electrode and the second electrode; Each of the first electrodes includes a first side and a second side opposite to each other, the first side contacts the substrate, and a ratio of a first dimension of the first side to a second dimension of the second side is 90% to 110%.

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